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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. h8sx/1655 group, h8sx/1655m group hardware manual 32 users manual rev.2.00 2009.10 renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series h8sx/1655 r5f61655 h8sx/1652 r5f61652 h8sx/1655m r5f61655m h8sx/1652m r5f61652m all information contained in these materials, including products and product specifcations, represents information on the product at the time of publication and is subject to change by renesas electronics corp. without notice. please review the latest information published by renesas electronics corp. through various means, including the renesas electronics corp. website (http://www. renesas.com). rev. 2.00 oct. 20, 2009 page ii of xxx rev. 2.00 oct. 20, 2009 page iii of xxx 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials rev. 2.00 oct. 20, 2009 page iv of xxx general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are gener ally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the ls i are indeterminate and t he states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i. e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products. rev. 2.00 oct. 20, 2009 page v of xxx how to use this manual 1. objective and target users this manual was written to explain the hardware functions and electrical characteristics of this lsi to the target users, i.e. those who will be using this lsi in the design of application systems. target users are expect ed to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. this manual is organized in the following items: an overview of the product, descriptions of the cpu, system control functions, and periphera l functions, electrical characteristics of the device, and usage notes. when designing an application system that includ es this lsi, take all points to note into account. points to note are given in their contex ts and at the final part of each section, and in the section giving usage notes. the list of revisions is a summary of major points of revision or addition for earlier versions. it does not cover all revised items. for details on the revised points, see the actual locations in the manual. the following documents have been prepared for the h8sx/1655 group and the h8sx/1655m group. before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. document type contents document title document no. data sheet overview of hardware and electrical characteristics hardware manual hardware specifications (pin assignments, memory maps, peripheral specificat ions, electrical characteristics, and timing charts) and descriptions of operation h8sx/1655 group, h8sx/1655m group hardware manual this manual software manual detailed descriptions of the cpu and instruction set h8sx family software manual rej09b0102 application note exampl es of applications and sample programs renesas technical update preliminary report on the specifications of a product, document, etc. the latest versions are available from our web site. rev. 2.00 oct. 20, 2009 page vi of xxx 2. description of numbers and symbols aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. cmcsr indicates compare match generation, enables or disables interrupts, and selects the counter input clock. generation of a wdtovf signal or interrupt initializes the tcnt value to 0. 14.3 operation the style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [example] cmcsr_0: indicates the cmcsr register for the compare-match timer of channel 0. in descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (1) overall notation (2) register notation rev. 0.50, 10/04, page 416 of 914 14.2.2 compare match control/status register_0, _1 (cmcsr_0, cmcsr_1) 14.3.1 interval count operation (4) (3) (2) binary numbers are given as b'nnnn (b' may be omitted if the number is obviously binary), hexadecimal numbers are given as h'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [examples] binary: b'11 or 11 hexadecimal: h'efa0 or 0xefa0 decimal: 1234 (3) number notation an overbar on the name indicates that a signal or pin is active-low. [example] wdtovf note: the bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. (4) notation for active-low when an internal clock is selected with the cks1 and cks0 bits in cmcsr and the str bit in cmstr is set to 1, cmcnt starts incrementing using the selected clock. when the values in cmcnt and the compare match constant register (cmcor) match, cmcnt is cleared to h'0000 and the cmf flag in cmcsr is set to 1. when the cks1 and cks0 bits are set to b'01 at this time, a f/4 clock is selected. rev. 2.00 oct. 20, 2009 page vii of xxx 3. description of registers each register description includes a bit chart, illu strating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. the standard format and notation for bit charts and tables are described below. indicates the bit number or numbers. in the case of a 32-bit register, the bits are arranged in order from 31 to 0. in the case of a 16-bit register, the bits are arranged in order from 15 to 0. indicates the name of the bit or bit field. when the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., asid[3:0]). a reserved bit is indicated by " ? ". certain kinds of bits, such as those of timer counters, are not assigned bit names. in such cases, the entry under bit name is blank. (1) bit (2) bit name indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: the initial value is 0 1: the initial value is 1 ? : the initial value is undefined (3) initial value for each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. the notation is as follows: r/w: r/(w): r: w: the bit or field is readable and writable. the bit or field is readable and writable. however, writing is only performed to flag clearing. the bit or field is readable. "r" is indicated for all reserved bits. when writing to the register, write the value under initial value in the bit chart to reserved bits or fields. the bit or field is writable. note: the bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (4) r/w describes the function of the bit or field and specifies the values for writing. (5) description bit 15 13 to 11 10 9 0 all 0 0 0 1 r r/w r r address identifier these bits enable or disable the pin function. reserved this bit is always read as 0. reserved this bit is always read as 1. ? asid2 to asid0 ? ? ? bit name initial value r/w description [bit chart] [table of bits] 14 1514131211109876543210 bit: initial value: r/w: 0000001000000000 r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w ? asid2 ?????? acmp2 q ife ? asid1 asid0 acmp1 acmp0 ? 0 r (1) (2) (3) (4) (5) reserved these bits are always read as 0. rev. 2.00 oct. 20, 2009 page viii of xxx 4. description of abbreviations the abbreviations used in this manual are listed below. ? abbreviations specific to this product abbreviation description bsc bus controller cpg clock pulse generator dtc data transfer controller intc interrupt controller ppg programmable pulse generator sci serial communications interface tmr 8-bit timer tpu 16-bit timer pulse unit wdt watchdog timer ? abbreviations other than those listed above abbreviation description acia asynchronous communications interface adapter bps bits per second crc cyclic redundancy check dma direct memory access dmac direct memory access controller gsm global system for mobile communications hi-z high impedance iebus inter equipment bus (iebus is a trademark of nec electronics corporation.) i/o input/output irda infrared data association lsb least significant bit msb most significant bit nc no connection pll phase-locked loop pwm pulse width modulation sfr special function register sim subscriber identity module uart universal asynchronous receiver/transmitter vco voltage-controlled oscillator all trademarks and registered trademarks ar e the property of th eir respective owners. rev. 2.00 oct. 20, 2009 page ix of xxx contents section 1 overview................................................................................................1 1.1 features....................................................................................................................... .......... 1 1.1.1 applicat ions .......................................................................................................... 1 1.1.2 overview of functions.......................................................................................... 2 1.2 list of products............................................................................................................... ...... 9 1.3 block diagram.................................................................................................................. .. 12 1.4 pin assign ments ................................................................................................................ .13 1.4.1 pin assignments ................................................................................................. 13 1.4.2 correspondence between pin config uration and operating modes ................... 15 1.4.3 pin functions ...................................................................................................... 21 section 2 cpu......................................................................................................27 2.1 features....................................................................................................................... ........ 27 2.2 cpu operating modes........................................................................................................ 29 2.2.1 normal mode...................................................................................................... 29 2.2.2 middle mode....................................................................................................... 31 2.2.3 advanced mode.................................................................................................. 32 2.2.4 maximum mode ................................................................................................. 33 2.3 instructio n fetch .............................................................................................................. ... 35 2.4 address space.................................................................................................................. ... 35 2.5 registers ...................................................................................................................... ....... 36 2.5.1 general registers................................................................................................ 37 2.5.2 program counter (pc) ........................................................................................ 38 2.5.3 condition-code re gister (ccr)......................................................................... 39 2.5.4 extended control re gister (exr) ...................................................................... 40 2.5.5 vector base re gister (vbr)............................................................................... 41 2.5.6 short address base register (sbr).................................................................... 41 2.5.7 multiply-accumulate re gister (mac) ............................................................... 41 2.5.8 initial values of cpu regist ers .......................................................................... 41 2.6 data formats................................................................................................................... .... 42 2.6.1 general register data formats ........................................................................... 42 2.6.2 memory data formats ........................................................................................ 44 2.7 instruction set ................................................................................................................ ..... 45 2.7.1 instructions and a ddressing modes.................................................................... 47 2.7.2 table of instructions cl assified by function ...................................................... 51 2.7.3 basic instructio n formats ................................................................................... 61 rev. 2.00 oct. 20, 2009 page x of xxx 2.8 addressing modes and effec tive address ca lculation....................................................... 62 2.8.1 register di rect?rn ........................................................................................... 62 2.8.2 register indi rect?@ern................................................................................... 63 2.8.3 register indirect with displacement ?@(d:2, ern), @(d:16, ern), or @(d:32, ern).................................................................................................. 63 2.8.4 index register indirect with displacement?@(d:16,rnl.b), @(d:32,rnl.b), @(d:16,rn.w), @(d:32,rn.w), @(d:16,ern.l), or @(d:32,ern.l) ............................................................................................... 63 2.8.5 register indirect with post-incremen t, pre-decrement, pre-increment, or post-decrement?@ern + , @ ? ern, @ + ern, or @ern ? ............................. 64 2.8.6 absolute address?@aa:8, @ aa:16, @aa:24, or @aa:32................................... 65 2.8.7 immediate?#xx ................................................................................................. 66 2.8.8 program-counter relative?@(d: 8, pc) or @(d:16, pc) .................................. 66 2.8.9 program-counter relative with index register?@(rnl.b, pc), @(rn.w, pc), or @(ern.l, pc) ........................................................................ 66 2.8.10 memory indirect?@@aa:8 ............................................................................... 67 2.8.11 extended memory in direct?@@vec:7 ............................................................. 68 2.8.12 effective address calculation ............................................................................ 68 2.8.13 mova instruction.............................................................................................. 70 2.9 processing states .............................................................................................................. .. 71 section 3 mcu operating modes ....................................................................... 73 3.1 operating mode selection .................................................................................................. 73 3.2 register de scriptions.......................................................................................................... 75 3.2.1 mode control regi ster (mdcr) ........................................................................ 75 3.2.2 system control re gister (s yscr)..................................................................... 77 3.3 operating mode descriptions ............................................................................................. 79 3.3.1 mode 1................................................................................................................ 79 3.3.2 mode 2................................................................................................................ 79 3.3.3 mode 3................................................................................................................ 79 3.3.4 mode 4................................................................................................................ 79 3.3.5 mode 5................................................................................................................ 80 3.3.6 mode 6................................................................................................................ 80 3.3.7 mode 7................................................................................................................ 80 3.3.8 pin functions ...................................................................................................... 81 3.4 address map.................................................................................................................... ... 81 3.4.1 address map....................................................................................................... 81 rev. 2.00 oct. 20, 2009 page xi of xxx section 4 reset.....................................................................................................87 4.1 types of reset ................................................................................................................. ... 87 4.2 input/output pin ............................................................................................................... .. 89 4.3 register de scriptions.......................................................................................................... 90 4.3.1 reset status regi ster (rstsr)........................................................................... 90 4.3.2 reset control/status re gister (rstcsr)........................................................... 92 4.4 pin reset ...................................................................................................................... ....... 93 4.5 power-on reset (por) (h8sx/1655m group) .................................................................. 93 4.6 power supply monitoring reset (h8sx/1655 m group).................................................... 95 4.7 deep software st andby reset............................................................................................. 95 4.8 watchdog time r reset ....................................................................................................... 95 4.9 determination of rese t generation source......................................................................... 96 section 5 voltage detection circuit (lvd) ........................................................97 5.1 features....................................................................................................................... ........ 97 5.2 register de scriptions.......................................................................................................... 98 5.2.1 voltage detection contro l register (lvdcr)................................................... 98 5.2.2 reset status regi ster (rstsr)........................................................................... 99 5.3 voltage detecti on circuit ................................................................................................. 101 5.3.1 voltage monitori ng reset................................................................................. 101 5.3.2 voltage monitoring interrupt............................................................................ 102 5.3.3 release from deep software standb y mode by the voltage-detection circuit ............................................................................................................... 104 5.3.4 voltage monitor................................................................................................ 104 section 6 exception handling ...........................................................................105 6.1 exception handling type s and prio rity............................................................................ 105 6.2 exception sources and exception handling vector table ............................................... 106 6.3 reset .......................................................................................................................... ....... 108 6.3.1 reset exception handling................................................................................. 108 6.3.2 interrupts afte r reset......................................................................................... 109 6.3.3 on-chip peripheral functions after reset release ........................................... 109 6.4 traces......................................................................................................................... ....... 111 6.5 address error.................................................................................................................. .. 112 6.5.1 address error source........................................................................................ 112 6.5.2 address error excep tion handlin g ................................................................... 114 6.6 interrupts..................................................................................................................... ...... 116 6.6.1 interrupt sources............................................................................................... 116 6.6.2 interrupt exceptio n handling ........................................................................... 117 rev. 2.00 oct. 20, 2009 page xii of xxx 6.7 instruction excep tion handli ng ........................................................................................ 118 6.7.1 trap instru ction ................................................................................................ 118 6.7.2 sleep instruction ex ception hand ling .............................................................. 119 6.7.3 exception handling by i llegal instru ction ........................................................ 120 6.8 stack status after ex ception hand ling ............................................................................. 121 6.9 usage note ..................................................................................................................... .. 122 section 7 interrupt controller............................................................................ 123 7.1 features....................................................................................................................... ...... 123 7.2 input/output pins.............................................................................................................. 125 7.3 register desc riptions........................................................................................................ 12 5 7.3.1 interrupt control re gister (i ntcr) ................................................................. 126 7.3.2 cpu priority control re gister (cpu pcr) ....................................................... 127 7.3.3 interrupt priority registers a to c, e to o, q, and r (ipra to iprc, ipre to ipro, iprq, and iprr)............................................ 129 7.3.4 irq enable regi ster (ier) ............................................................................... 131 7.3.5 irq sense control registers h and l (iscrh, iscrl).................................. 133 7.3.6 irq status regi ster (isr)................................................................................. 138 7.3.7 software standby release irq en able register (ssier) ................................ 140 7.4 interrupt sources.............................................................................................................. .141 7.4.1 external interrupts ............................................................................................ 141 7.4.2 internal interrupts ............................................................................................. 142 7.5 interrupt exception hand ling vector table...................................................................... 143 7.6 interrupt control modes and interrupt oper ation............................................................. 149 7.6.1 interrupt control mode 0.................................................................................. 149 7.6.2 interrupt control mode 2.................................................................................. 151 7.6.3 interrupt exception ha ndling sequ ence ........................................................... 153 7.6.4 interrupt respon se times ................................................................................. 154 7.6.5 dtc and dmac activatio n by interr upt ......................................................... 155 7.7 cpu priority control function ov er dtc, dmac, and exdmac ............................... 158 7.8 usage notes .................................................................................................................... .. 161 7.8.1 conflict between interrupt ge neration and di sabling ...................................... 161 7.8.2 instructions that di sable interrupts................................................................... 162 7.8.3 times when interrupt s are disabled ................................................................. 162 7.8.4 interrupts during execution of eepmov inst ruction ...................................... 162 7.8.5 interrupts during execution of mo vmd and movsd instructions................ 162 7.8.6 interrupts of periph eral modu les ...................................................................... 163 rev. 2.00 oct. 20, 2009 page xiii of xxx section 8 user break controller (ubc) ............................................................165 8.1 features....................................................................................................................... ...... 165 8.2 block diagram.................................................................................................................. 166 8.3 register desc riptions........................................................................................................ 16 7 8.3.1 break address register n (bar a, barb, barc, bard) ............................ 168 8.3.2 break address mask register n (b amra, bamrb, bamrc, bamrd) .... 169 8.3.3 break control register n (brcra, brcrb, brcrc, brcrd) ................... 170 8.4 operation ...................................................................................................................... .... 172 8.4.1 setting of break cont rol conditions................................................................. 172 8.4.2 pc break........................................................................................................... 172 8.4.3 condition matc h flag ....................................................................................... 173 8.5 usage notes .................................................................................................................... .. 174 section 9 bus controller (bsc).........................................................................177 9.1 features....................................................................................................................... ...... 177 9.2 register desc riptions........................................................................................................ 18 0 9.2.1 bus width control re gister (a bwcr)............................................................ 181 9.2.2 access state control re gister (a stcr) .......................................................... 182 9.2.3 wait control registers a and b (wtcra , wtcrb) ..................................... 183 9.2.4 read strobe timing cont rol register (rdncr) ............................................. 188 9.2.5 cs assertion period contro l registers (csacr) ............................................ 189 9.2.6 idle control register (idlcr) ......................................................................... 192 9.2.7 bus control regist er 1 (bcr1) ........................................................................ 194 9.2.8 bus control regist er 2 (bcr2) ........................................................................ 196 9.2.9 endian control regist er (endiancr)............................................................ 197 9.2.10 sram mode control re gister (sra mcr) ..................................................... 198 9.2.11 burst rom interface control register (b romcr)......................................... 199 9.2.12 address/data multiplexed i/o c ontrol register (mpxcr) ............................. 201 9.3 bus configur ation............................................................................................................. 2 02 9.4 multi-clock function and numb er of access cycles ...................................................... 203 9.5 external bus................................................................................................................... ... 207 9.5.1 input/output pins.............................................................................................. 207 9.5.2 area division.................................................................................................... 210 9.5.3 chip select signals ........................................................................................... 211 9.5.4 external bus interface....................................................................................... 212 9.5.5 area and external bus interface ....................................................................... 216 9.5.6 endian and data alignment.............................................................................. 221 9.6 basic bus in terface ........................................................................................................... 2 24 9.6.1 data bus............................................................................................................ 224 rev. 2.00 oct. 20, 2009 page xiv of xxx 9.6.2 i/o pins used for ba sic bus inte rface .............................................................. 224 9.6.3 basic timi ng..................................................................................................... 225 9.6.4 wait cont rol ..................................................................................................... 231 9.6.5 read strobe ( rd ) timing................................................................................. 233 9.6.6 extension of chip select ( cs ) assertion period............................................... 234 9.6.7 dack and edack signal output timings .................................................... 236 9.7 byte control sram interface .......................................................................................... 237 9.7.1 byte control sram space setti ng................................................................... 237 9.7.2 data bus ........................................................................................................... 237 9.7.3 i/o pins used for byte co ntrol sram in terface ............................................. 238 9.7.4 basic timi ng..................................................................................................... 239 9.7.5 wait cont rol ..................................................................................................... 241 9.7.6 read strobe ( rd ) ............................................................................................. 243 9.7.7 extension of chip select ( cs ) assertion period............................................... 243 9.7.8 dack and edack signal output timings .................................................... 243 9.8 burst rom in terface ........................................................................................................ 245 9.8.1 burst rom space setting................................................................................. 245 9.8.2 data bus ........................................................................................................... 245 9.8.3 i/o pins used for bu rst rom interface............................................................ 246 9.8.4 basic timi ng..................................................................................................... 247 9.8.5 wait cont rol ..................................................................................................... 249 9.8.6 read strobe ( rd ) timing................................................................................. 249 9.8.7 extension of chip select ( cs ) assertion period............................................... 249 9.9 address/data multiplexe d i/o inte rface........................................................................... 250 9.9.1 address/data multiplexed i/o space sett ing ................................................... 250 9.9.2 address/data multiplex.................................................................................... 250 9.9.3 data bus ........................................................................................................... 250 9.9.4 i/o pins used for address/data multiplexed i/o interface.............................. 251 9.9.5 basic timi ng..................................................................................................... 252 9.9.6 address cycle control...................................................................................... 254 9.9.7 wait cont rol ..................................................................................................... 255 9.9.8 read strobe ( rd ) timing................................................................................. 255 9.9.9 extension of chip select ( cs ) assertion period............................................... 257 9.9.10 dack and edack signal output timings .................................................... 259 9.10 idle cycle..................................................................................................................... ..... 260 9.10.1 operation .......................................................................................................... 260 9.10.2 pin states in id le cycle..................................................................................... 269 9.11 bus rel ease.................................................................................................................... ... 270 9.11.1 operation .......................................................................................................... 270 9.11.2 pin states in external bus released state ........................................................ 271 rev. 2.00 oct. 20, 2009 page xv of xxx 9.11.3 transition timing ............................................................................................. 272 9.12 internal bus................................................................................................................... .... 273 9.12.1 access to internal address sp ace ..................................................................... 273 9.13 write data buffe r function .............................................................................................. 274 9.13.1 write data buffer function fo r external data bus........................................... 274 9.13.2 write data buffer function fo r peripheral modules ........................................ 275 9.14 bus arbitr ation ................................................................................................................ .276 9.14.1 operation .......................................................................................................... 276 9.14.2 bus transfer timing ......................................................................................... 277 9.15 bus controller opera tion in reset .................................................................................... 280 9.16 usage notes .................................................................................................................... .. 280 section 10 dma controller (dmac) ...............................................................283 10.1 features....................................................................................................................... ...... 283 10.2 input/output pins.............................................................................................................. 286 10.3 register desc riptions........................................................................................................ 28 7 10.3.1 dma source address re gister (dsar)........................................................... 288 10.3.2 dma destination address register ( ddar)................................................... 289 10.3.3 dma offset regist er (dofr).......................................................................... 290 10.3.4 dma transfer count re gister (d tcr) ........................................................... 291 10.3.5 dma block size regi ster (dbsr) .................................................................. 292 10.3.6 dma mode control re gister (d mdr)............................................................ 293 10.3.7 dma address control re gister (dacr) ......................................................... 302 10.3.8 dma module request select register (dmrsr) ........................................... 308 10.4 transfer modes ................................................................................................................. 309 10.5 operations..................................................................................................................... .... 310 10.5.1 address modes ................................................................................................. 310 10.5.2 transfer modes ................................................................................................. 314 10.5.3 activation so urces............................................................................................ 319 10.5.4 bus access modes ............................................................................................ 321 10.5.5 extended repeat ar ea function ....................................................................... 323 10.5.6 address update functio n using offset ............................................................. 326 10.5.7 register during dma transf er ......................................................................... 330 10.5.8 priority of channels .......................................................................................... 335 10.5.9 dma basic bus cycle...................................................................................... 337 10.5.10 bus cycles in dual address mode ................................................................... 338 10.5.11 bus cycles in singl e address mode................................................................. 347 10.6 dma transfer end ........................................................................................................... 352 10.7 relationship among dmac an d other bus ma sters ........................................................ 355 10.7.1 cpu priority control fu nction over dmac ................................................... 355 rev. 2.00 oct. 20, 2009 page xvi of xxx 10.7.2 bus arbitration among dmac and other bus masters ................................... 356 10.8 interrupt sources.............................................................................................................. .357 10.9 usage notes .................................................................................................................... .. 360 section 11 exdma co ntroller (exdmac) .................................................... 361 11.1 features....................................................................................................................... ...... 361 11.2 input/output pins.............................................................................................................. 364 11.3 registers desc riptions ...................................................................................................... 365 11.3.1 exdma source address re gister (edsar)................................................... 367 11.3.2 exdma destination address register (eddar)........................................... 368 11.3.3 exdma offset regist er (edofr).................................................................. 369 11.3.4 exdma transfer count register (e dtcr).................................................... 370 11.3.5 exdma block size regi ster (edbsr)........................................................... 371 11.3.6 exdma mode control re gister (edmdr) .................................................... 372 11.3.7 exdma address control re gister (edacr) ................................................. 381 11.3.8 cluster buffer registers 0 to 7 (clsbr0 to clsbr7).................................... 387 11.4 transfer modes................................................................................................................. 388 11.4.1 ordinary modes ................................................................................................ 388 11.4.2 cluster transfer modes .................................................................................... 389 11.5 mode oper ation ................................................................................................................ 3 90 11.5.1 address modes ................................................................................................. 390 11.5.2 transfer modes................................................................................................. 394 11.5.3 activation so urces............................................................................................ 399 11.5.4 bus mode.......................................................................................................... 400 11.5.5 extended repeat ar ea function ....................................................................... 401 11.5.6 address update functi on using offset ............................................................ 404 11.5.7 registers during exdma tr ansfer operation ................................................. 408 11.5.8 channel priority order...................................................................................... 413 11.5.9 basic bus cy cles .............................................................................................. 414 11.5.10 bus cycles in dual address mode ................................................................... 415 11.5.11 bus cycles in singl e address mode................................................................. 424 11.5.12 operation timing in each mode ...................................................................... 429 11.6 operation in cluster transfer mode ................................................................................. 440 11.6.1 address mode................................................................................................... 440 11.6.2 setting of address update mode...................................................................... 445 11.6.3 caution for combining with extended repeat area function ......................... 446 11.6.4 bus cycles in cluster transf er dual address mode ........................................ 446 11.6.5 operation timing in clus ter transfer mode .................................................... 449 11.7 ending exdma transfer................................................................................................. 457 11.8 relationship among exdmac an d other bus ma sters................................................... 460 rev. 2.00 oct. 20, 2009 page xvii of xxx 11.8.1 cpu priority control fu nction over exdmac .............................................. 460 11.8.2 bus arbitration with an other bus master ........................................................ 461 11.9 interrupt sources.............................................................................................................. .462 11.10 usage notes .................................................................................................................... .. 465 section 12 data transf er controller (dtc) ......................................................467 12.1 features....................................................................................................................... ...... 467 12.2 register desc riptions........................................................................................................ 46 9 12.2.1 dtc mode register a (mra) ......................................................................... 470 12.2.2 dtc mode regist er b (m rb).......................................................................... 471 12.2.3 dtc source address re gister (sar)............................................................... 472 12.2.4 dtc destination address register (d ar)....................................................... 473 12.2.5 dtc transfer count re gister a (cra) ........................................................... 473 12.2.6 dtc transfer count re gister b (crb)............................................................ 474 12.2.7 dtc enable registers a to f (dtcera to dtcerf)...................................... 474 12.2.8 dtc control regist er (dtccr) ...................................................................... 475 12.2.9 dtc vector base regi ster (dtcvbr)............................................................ 477 12.3 activation sources............................................................................................................ 4 77 12.4 location of transfer informati on and dtc vector table ................................................ 478 12.5 operation ...................................................................................................................... .... 483 12.5.1 bus cycle di vision ........................................................................................... 485 12.5.2 transfer information re ad skip fu nction ........................................................ 487 12.5.3 transfer information write back skip function ................................................ 488 12.5.4 normal transfer mode ..................................................................................... 488 12.5.5 repeat transf er mode....................................................................................... 489 12.5.6 block transfer mode ........................................................................................ 491 12.5.7 chain transfer .................................................................................................. 492 12.5.8 operation timing.............................................................................................. 493 12.5.9 number of dtc exec ution cycl es ................................................................... 495 12.5.10 dtc bus releas e timing ................................................................................. 496 12.5.11 dtc priority level cont rol to the cpu ........................................................... 496 12.6 dtc activation by interrupt............................................................................................. 497 12.7 examples of use of the dtc ............................................................................................ 498 12.7.1 normal transfer mode ..................................................................................... 498 12.7.2 chain transfer .................................................................................................. 498 12.7.3 chain transfer when counter = 0..................................................................... 499 12.8 interrupt sources.............................................................................................................. .501 12.9 usage notes .................................................................................................................... .. 501 12.9.1 module stop stat e setting ................................................................................ 501 12.9.2 on-chip ram .................................................................................................. 501 rev. 2.00 oct. 20, 2009 page xviii of xxx 12.9.3 dmac transfer en d interr upt.......................................................................... 501 12.9.4 dtce bit se tting.............................................................................................. 501 12.9.5 chain transfer .................................................................................................. 502 12.9.6 transfer information start address, source address, and destination address ............................................................................................................. 502 12.9.7 transfer informati on modification ................................................................... 502 12.9.8 endian format .................................................................................................. 502 12.9.9 points for caution when overwriting dtcer ................................................. 503 section 13 i/o ports........................................................................................... 505 13.1 register desc riptions........................................................................................................ 51 2 13.1.1 data direction register (pnddr) (n = 1, 2, 6, a, b, d to f, h to k, and m) ......................................................... 513 13.1.2 data register (pndr) (n = 1, 2, 6, a, b, d to f, h to k, and m)..................... 514 13.1.3 port register (portn) (n = 1, 2, 5, 6, a, b, d to f, h to k, and m) ............... 514 13.1.4 input buffer control register (pnicr) (n = 1, 2, 5, 6, a, b, d to f, h to k, and m) ..................................................... 515 13.1.5 pull-up mos control register (pnpcr) (n = d to f, and h to k).................. 516 13.1.6 open-drain control register (pnodr) (n = 2 and f)...................................... 517 13.2 output buffer control....................................................................................................... 518 13.2.1 port 1................................................................................................................. 518 13.2.2 port 2................................................................................................................. 522 13.2.3 port 5................................................................................................................. 526 13.2.4 port 6................................................................................................................. 527 13.2.5 port a................................................................................................................ 530 13.2.6 port b................................................................................................................ 534 13.2.7 port d................................................................................................................ 536 13.2.8 port e ................................................................................................................ 537 13.2.9 port f ................................................................................................................ 538 13.2.10 port h................................................................................................................ 540 13.2.11 port i ................................................................................................................. 541 13.2.12 port j ................................................................................................................. 542 13.2.13 port k................................................................................................................ 546 13.2.14 port m ............................................................................................................... 550 13.3 port function controller ................................................................................................... 559 13.3.1 port function control re gister 0 (pfcr0)....................................................... 560 13.3.2 port function control re gister 1 (pfcr1)....................................................... 561 13.3.3 port function control re gister 2 (pfcr2)....................................................... 562 13.3.4 port function control re gister 4 (pfcr4)....................................................... 564 13.3.5 port function control re gister 6 (pfcr6)....................................................... 565 rev. 2.00 oct. 20, 2009 page xix of xxx 13.3.6 port function control re gister 7 (pfcr7)....................................................... 566 13.3.7 port function control re gister 8 (pfcr8)....................................................... 567 13.3.8 port function control re gister 9 (pfcr9)....................................................... 568 13.3.9 port function control re gister a ( pfcra) ..................................................... 569 13.3.10 port function control re gister b ( pfcrb)...................................................... 571 13.3.11 port function control re gister c ( pfcrc)...................................................... 573 13.3.12 port function control re gister d ( pfcrd) ..................................................... 574 13.4 usage notes .................................................................................................................... .. 575 13.4.1 notes on input buffer control register (icr) setting ..................................... 575 13.4.2 notes on port function control register (pfcr) settings............................... 575 section 14 16-bit time r pulse unit (tpu) .......................................................577 14.1 features....................................................................................................................... ...... 577 14.2 input/output pins.............................................................................................................. 584 14.3 register desc riptions........................................................................................................ 58 6 14.3.1 timer control regi ster (t cr).......................................................................... 591 14.3.2 timer mode regist er (tmdr) ......................................................................... 596 14.3.3 timer i/o control re gister (tior) .................................................................. 598 14.3.4 timer interrupt enable register (tier) ........................................................... 632 14.3.5 timer status regi ster (tsr)............................................................................. 633 14.3.6 timer counter (tcnt)..................................................................................... 637 14.3.7 timer general regi ster (tgr) ......................................................................... 637 14.3.8 timer start regist er (tstr) ............................................................................ 638 14.3.9 timer synchronous re gister (tsyr)............................................................... 639 14.4 operation ...................................................................................................................... .... 640 14.4.1 basic func tions................................................................................................. 640 14.4.2 synchronous op eration..................................................................................... 646 14.4.3 buffer operation ............................................................................................... 648 14.4.4 cascaded oper ation .......................................................................................... 652 14.4.5 pwm modes ..................................................................................................... 654 14.4.6 phase counting mode ....................................................................................... 660 14.5 interrupt sources.............................................................................................................. .667 14.6 dtc activ ation................................................................................................................. 670 14.7 dmac activa tion............................................................................................................. 670 14.8 a/d converter ac tivation................................................................................................. 670 14.9 operation timing.............................................................................................................. 6 71 14.9.1 input/output timing ......................................................................................... 671 14.9.2 interrupt signal timing..................................................................................... 675 14.10 usage notes .................................................................................................................... .. 679 14.10.1 module stop func tion settin g .......................................................................... 679 rev. 2.00 oct. 20, 2009 page xx of xxx 14.10.2 input clock rest rictions ................................................................................... 679 14.10.3 caution on cycl e setting .................................................................................. 680 14.10.4 conflict between tcnt write and clear oper ations....................................... 680 14.10.5 conflict between tcnt write an d increment operations ............................... 681 14.10.6 conflict between tgr write and compare match........................................... 681 14.10.7 conflict between buffer register write and comp are match .......................... 682 14.10.8 conflict between tgr read and input capture ............................................... 682 14.10.9 conflict between tgr write and input capture .............................................. 683 14.10.10 conflict between buffer register write and inpu t capture.............................. 684 14.10.11 conflict between overflow/underfl ow and counter clearing ......................... 685 14.10.12 conflict between tcnt write and overflow/underflow ................................ 685 14.10.13 interrupts and module stop mode .................................................................... 686 section 15 programmable pulse generator (ppg)............................................ 687 15.1 features....................................................................................................................... ...... 687 15.2 input/output pins.............................................................................................................. 690 15.3 register desc riptions........................................................................................................ 69 1 15.3.1 next data enable register s h, l (nderh, nderl) ..................................... 692 15.3.2 output data registers h, l (podrh, podrl)............................................... 694 15.3.3 next data registers h, l (ndrh, ndrl) ...................................................... 697 15.3.4 ppg output control register (pcr) ................................................................ 701 15.3.5 ppg output mode re gister (pmr) .................................................................. 703 15.4 operation ...................................................................................................................... .... 707 15.4.1 output timing .................................................................................................. 707 15.4.2 sample setup procedure for normal pulse output........................................... 708 15.4.3 example of normal pulse output (exa mple of 5-phase pulse output)............ 710 15.4.4 non-overlapping pu lse output......................................................................... 711 15.4.5 sample setup procedure for non- overlapping pulse output........................... 713 15.4.6 example of non-overlapping pulse output (example of 4-phase complementary non-overlapping pulse output)........... 715 15.4.7 inverted pulse output ....................................................................................... 717 15.4.8 pulse output triggered by input capture ......................................................... 718 15.5 usage notes .................................................................................................................... .. 719 15.5.1 module stop st ate settin g ................................................................................ 719 15.5.2 operation of pulse output pins......................................................................... 719 15.5.3 tpu setting when ppg1 is in use.................................................................... 719 section 16 8-bit timers (tmr) ........................................................................ 721 16.1 features....................................................................................................................... ...... 721 16.2 input/output pins.............................................................................................................. 726 rev. 2.00 oct. 20, 2009 page xxi of xxx 16.3 register desc riptions........................................................................................................ 72 7 16.3.1 timer counter (tcnt)..................................................................................... 729 16.3.2 time constant regist er a (tcora)................................................................ 729 16.3.3 time constant regi ster b (t corb) ................................................................ 730 16.3.4 timer control regi ster (t cr).......................................................................... 730 16.3.5 timer counter control register (tccr) ......................................................... 732 16.3.6 timer control/status register (t csr)............................................................. 737 16.4 operation ...................................................................................................................... .... 742 16.4.1 pulse outp ut...................................................................................................... 742 16.4.2 reset inpu t ........................................................................................................ 743 16.5 operation timing.............................................................................................................. 7 44 16.5.1 tcnt count timing ........................................................................................ 744 16.5.2 timing of cmfa and cmfb se tting at compar e match................................. 745 16.5.3 timing of timer output at compare match ..................................................... 745 16.5.4 timing of counter clear by compare match ................................................... 746 16.5.5 timing of tcnt ex ternal reset....................................................................... 746 16.5.6 timing of overflow fl ag (ovf) setting .......................................................... 747 16.6 operation with cascad ed connection............................................................................... 748 16.6.1 16-bit counter mode ........................................................................................ 748 16.6.2 compare match co unt mode............................................................................ 748 16.7 interrupt sources.............................................................................................................. .749 16.7.1 interrupt sources and dtc activa tion ............................................................. 749 16.7.2 a/d converter ac tivation ................................................................................. 750 16.8 usage notes .................................................................................................................... .. 751 16.8.1 notes on settin g cycle...................................................................................... 751 16.8.2 conflict between tcnt writ e and counte r clear............................................ 751 16.8.3 conflict between tcnt wr ite and increment.................................................. 752 16.8.4 conflict between tcor writ e and compare match ........................................ 752 16.8.5 conflict between compare matches a and b................................................... 753 16.8.6 switching of internal clocks and tcnt op eration.......................................... 753 16.8.7 mode setting with casc aded connect ion ......................................................... 755 16.8.8 module stop st ate settin g ................................................................................ 755 16.8.9 interrupts in module stop state ........................................................................ 755 section 17 watchdog timer (wdt)..................................................................757 17.1 features....................................................................................................................... ...... 757 17.2 input/output pin ............................................................................................................... 758 17.3 register desc riptions........................................................................................................ 75 9 17.3.1 timer counter (tcnt)..................................................................................... 759 17.3.2 timer control/status register (t csr)............................................................. 759 rev. 2.00 oct. 20, 2009 page xxii of xxx 17.3.3 reset control/status re gister (rst csr)......................................................... 761 17.4 operation ...................................................................................................................... .... 762 17.4.1 watchdog time r mode..................................................................................... 762 17.4.2 interval timer mode......................................................................................... 764 17.5 interrupt source ............................................................................................................... .764 17.6 usage notes .................................................................................................................... .. 765 17.6.1 notes on regist er access ................................................................................. 765 17.6.2 conflict between timer counter (t cnt) write and increment....................... 766 17.6.3 changing values of bi ts cks2 to cks0.......................................................... 766 17.6.4 switching between watchdog timer m ode and interval timer mode............. 766 17.6.5 internal reset in watc hdog timer mode.......................................................... 767 17.6.6 system reset by wdtovf signal................................................................... 767 17.6.7 transition to watchdog timer mode or software st andby mode.................... 767 section 18 serial communication interface (sci, irda, crc) ....................... 769 18.1 features....................................................................................................................... ...... 769 18.2 input/output pins.............................................................................................................. 774 18.3 register desc riptions........................................................................................................ 77 5 18.3.1 receive shift regi ster (rsr) ........................................................................... 777 18.3.2 receive data regi ster (rdr)........................................................................... 777 18.3.3 transmit data regi ster (tdr).......................................................................... 778 18.3.4 transmit shift regi ster (tsr) .......................................................................... 778 18.3.5 serial mode regi ster (smr) ............................................................................ 778 18.3.6 serial control re gister (s cr) .......................................................................... 782 18.3.7 serial status regi ster (ssr) ............................................................................. 787 18.3.8 smart card mode re gister (s cmr)................................................................. 796 18.3.9 bit rate regist er (brr) ................................................................................... 797 18.3.10 serial extended mode re gister (semr_2) ...................................................... 804 18.3.11 serial extended mode register 5 and 6 (semr_5 and semr_6)................... 806 18.3.12 irda control regi ster (ircr)........................................................................... 813 18.4 operation in asynch ronous mode .................................................................................... 814 18.4.1 data transfer format........................................................................................ 815 18.4.2 receive data sampling timing and r eception margin in asynchronous mode ................................................................................................................. 816 18.4.3 clock................................................................................................................. 817 18.4.4 sci initialization (async hronous mo de).......................................................... 818 18.4.5 serial data transmission (asynchronous mode) ............................................. 819 18.4.6 serial data reception (a synchronous mode) .................................................. 821 18.5 multiprocessor communi cation func tion ........................................................................ 825 18.5.1 multiprocessor serial da ta transmission ......................................................... 827 rev. 2.00 oct. 20, 2009 page xxiii of xxx 18.5.2 multiprocessor serial data recep tion .............................................................. 828 18.6 operation in clocked synchronous mode (sci_0, 1, 2, and 4 only)................................ 831 18.6.1 clock................................................................................................................. 831 18.6.2 sci initialization (clocked synchronous m ode) (sci_0, 1, 2, and 4 only)...... 832 18.6.3 serial data transmission (clocked synchronous mode) (sci_0, 1, 2, an d 4 only ) ................................................................................... 833 18.6.4 serial data reception (clocked synchronous mode) (sci_0, 1, 2, an d 4 only ) ................................................................................... 835 18.6.5 simultaneous serial data tr ansmission and reception (clocked synchronous mode) (sci _0, 1, 2, and 4 only) .................................. 836 18.7 operation in smart ca rd interface mode.......................................................................... 838 18.7.1 sample connection ........................................................................................... 838 18.7.2 data format (except in bl ock transfer mode) ................................................ 839 18.7.3 block transfer mode ........................................................................................ 840 18.7.4 receive data sampling timing and receptio n margin .................................... 841 18.7.5 initializatio n ...................................................................................................... 842 18.7.6 data transmission (except in block transfer mode) ...................................... 843 18.7.7 serial data reception (except in block transfer mode).................................. 846 18.7.8 clock output control (only sci_0, 1, 2, and 4) .............................................. 847 18.8 irda oper ation ................................................................................................................. 849 18.9 interrupt sources.............................................................................................................. .852 18.9.1 interrupts in normal serial co mmunication interface mode ........................... 852 18.9.2 interrupts in smart ca rd interface mode .......................................................... 853 18.10 usage notes .................................................................................................................... .. 855 18.10.1 module stop func tion settin g .......................................................................... 855 18.10.2 break detection an d processing ....................................................................... 855 18.10.3 mark state and break detection ....................................................................... 855 18.10.4 receive error flags and transmit operations (clocked synchronous mode only).................................................................. 855 18.10.5 relation between writing to tdr and tdre flag .......................................... 856 18.10.6 restrictions on usin g dtc or dmac.............................................................. 856 18.10.7 sci operations during power-down state ....................................................... 857 18.11 crc operation ci rcuit ..................................................................................................... 860 18.11.1 features............................................................................................................. 860 18.11.2 register desc riptions ........................................................................................ 861 18.11.3 crc operation circu it operatio n..................................................................... 863 18.11.4 note on crc opera tion circui t........................................................................ 866 rev. 2.00 oct. 20, 2009 page xxiv of xxx section 19 usb function module (usb) ......................................................... 867 19.1 features....................................................................................................................... ...... 867 19.2 input/output pins.............................................................................................................. 868 19.3 register desc riptions........................................................................................................ 86 9 19.3.1 interrupt flag regi ster 0 (ifr0) ....................................................................... 870 19.3.2 interrupt flag regi ster 1 (ifr1) ....................................................................... 872 19.3.3 interrupt flag regi ster 2 (ifr2) ....................................................................... 873 19.3.4 interrupt select regi ster 0 (isr0)..................................................................... 875 19.3.5 interrupt select regi ster 1 (isr1)..................................................................... 876 19.3.6 interrupt select regi ster 2 (isr2)..................................................................... 877 19.3.7 interrupt enable regi ster 0 (ier0) ................................................................... 878 19.3.8 interrupt enable regi ster 1 (ier1) ................................................................... 879 19.3.9 interrupt enable regi ster 2 (ier2) ................................................................... 879 19.3.10 ep0i data regist er (epdr0i)........................................................................... 880 19.3.11 ep0o data regist er (epdr0o) ......................................................................... 881 19.3.12 ep0s data regist er (epdr0s) .......................................................................... 881 19.3.13 ep1 data register (epdr1) ............................................................................. 882 19.3.14 ep2 data register (epdr2) ............................................................................. 882 19.3.15 ep3 data register (epdr3) ............................................................................. 883 19.3.16 ep0o receive data size register (epsz0o) .................................................... 883 19.3.17 ep1 receive data size register (e psz1) ........................................................ 884 19.3.18 trigger register (trg) .................................................................................... 884 19.3.19 data status regist er (dasts).......................................................................... 886 19.3.20 fifo clear regist er (fclr) ............................................................................ 887 19.3.21 dma transfer setting register (dma) ........................................................... 888 19.3.22 endpoint stall regi ster (epstl)...................................................................... 891 19.3.23 configuration value re gister (cvr) ............................................................... 892 19.3.24 control register (ctlr) .................................................................................. 892 19.3.25 endpoint information register (epir) ............................................................. 894 19.3.26 transceiver test regist er 0 (trntreg0) ...................................................... 898 19.3.27 transceiver test regist er 1 (trntreg1) ...................................................... 900 19.4 interrupt sources.............................................................................................................. .902 19.5 operation ...................................................................................................................... .... 904 19.5.1 cable connect ion.............................................................................................. 904 19.5.2 cable disconn ection ......................................................................................... 905 19.5.3 suspend and resume operatio ns...................................................................... 905 19.5.4 control tran sfer................................................................................................ 914 19.5.5 ep1 bulk-out transfer (dual fifos)............................................................... 920 19.5.6 ep2 bulk-in transfer (dual fifos) ................................................................. 921 rev. 2.00 oct. 20, 2009 page xxv of xxx 19.5.7 ep3 interrupt-in transfer.................................................................................. 923 19.6 processing of usb standard command s and class/vendor commands ......................... 924 19.6.1 processing of commands transm itted by control transfer ............................. 924 19.7 stall oper ations............................................................................................................... .. 925 19.7.1 overview........................................................................................................... 925 19.7.2 forcible stall by applicatio n ............................................................................ 925 19.7.3 automatic stall by us b function module ....................................................... 927 19.8 dma tran sfer................................................................................................................... 928 19.8.1 overview........................................................................................................... 928 19.8.2 dma transfer for endpoint 1 .......................................................................... 928 19.8.3 dma transfer for endpoint 2 .......................................................................... 929 19.9 example of usb extern al circui try ................................................................................. 930 19.10 usage notes .................................................................................................................... .. 932 19.10.1 receiving setu p data........................................................................................ 932 19.10.2 clearing the fifo ............................................................................................. 932 19.10.3 overreading and overwriting the data regi sters ............................................. 932 19.10.4 assigning interrupt s ources to ep0 .................................................................. 933 19.10.5 clearing the fifo when dma transfer is enabled ........................................ 933 19.10.6 notes on tr interrupt ....................................................................................... 933 19.10.7 restrictions on peripheral module clock (p ) operating frequency............... 934 19.10.8 notes on deep software standb y mode when usb is used ............................ 934 section 20 i 2 c bus interface 2 (iic2) ................................................................935 20.1 features....................................................................................................................... ...... 935 20.2 input/output pins.............................................................................................................. 937 20.3 register desc riptions........................................................................................................ 93 8 20.3.1 i 2 c bus control regist er a (iccra ) ............................................................... 939 20.3.2 i 2 c bus control regi ster b (i ccrb)................................................................ 941 20.3.3 i 2 c bus mode regist er (icmr)........................................................................ 943 20.3.4 i 2 c bus interrupt enable register (i cier) ....................................................... 944 20.3.5 i 2 c bus status regi ster (icsr)......................................................................... 947 20.3.6 slave address regi ster (sar).......................................................................... 950 20.3.7 i 2 c bus transmit data re gister (icdrt)......................................................... 951 20.3.8 i 2 c bus receive data re gister (icd rr).......................................................... 951 20.3.9 i 2 c bus shift regist er (icdrs)........................................................................ 951 20.4 operation ...................................................................................................................... .... 952 20.4.1 i 2 c bus format.................................................................................................. 952 20.4.2 master transmit operation ............................................................................... 953 20.4.3 master receive operatio n................................................................................. 955 20.4.4 slave transmit op eration ................................................................................. 957 rev. 2.00 oct. 20, 2009 page xxvi of xxx 20.4.5 slave receive op eration................................................................................... 960 20.4.6 noise canceler.................................................................................................. 961 20.4.7 example of use................................................................................................. 962 20.5 interrupt request .............................................................................................................. 966 20.6 bit synchronous circuit.................................................................................................... 967 20.7 usage notes .................................................................................................................... .. 968 section 21 a/d converter ................................................................................. 971 21.1 features....................................................................................................................... ...... 971 21.2 input/output pins.............................................................................................................. 974 21.3 register desc riptions........................................................................................................ 97 5 21.3.1 a/d data registers a to h (addra to addrh) .......................................... 976 21.3.2 a/d control/status register_0 (adcsr_0) fo r unit 0.................................... 977 21.3.3 a/d control/status register 1 (adcsr_1) for unit 1..................................... 980 21.3.4 a/d control register_0 (a dcr_0) for unit 0................................................. 982 21.3.5 a/d control register_1 (a dcr_1) for unit 1................................................. 984 21.3.6 a/d mode selection register_0 (admosel_0) for unit 0............................ 986 21.3.7 a/d mode selection register_1 (admosel_1) for unit 1............................ 987 21.3.8 a/d sampling state register_0 (adsstr_0) for unit 0................................. 988 21.3.9 a/d sampling state register_1 (adsstr_1) for unit 1................................. 989 21.4 operation ...................................................................................................................... .... 990 21.4.1 single mode...................................................................................................... 990 21.4.2 scan mode ........................................................................................................ 991 21.4.3 input sampling and a/d conversion time ...................................................... 996 21.4.4 timing of external trigger input ................................................................... 1001 21.4.5 setting the system clock mo de...................................................................... 1002 21.5 interrupt source .............................................................................................................. 1 003 21.6 a/d conversion accura cy definitions ........................................................................... 1004 21.7 usage notes .................................................................................................................... 1006 21.7.1 module stop func tion settin g ........................................................................ 1006 21.7.2 a/d input hold function in software standby mode .................................... 1006 21.7.3 notes on stopping the a/d converter ............................................................ 1006 21.7.4 notes in system clock mode ......................................................................... 1008 21.7.5 permissible signal s ource impedance ............................................................ 1009 21.7.6 influences on abso lute accu racy ................................................................... 1010 21.7.7 setting range of analog power supply and other pins................................. 1010 21.7.8 notes on boar d design ................................................................................... 1011 21.7.9 notes on noise co untermeasur es ................................................................... 1011 rev. 2.00 oct. 20, 2009 page xxvii of xxx section 22 d/a converter................................................................................1013 22.1 features....................................................................................................................... .... 1013 22.2 input/output pins............................................................................................................ 10 14 22.3 register desc riptions...................................................................................................... 1014 22.3.1 d/a data registers 0 an d 1 (dadr0, dadr1) ............................................ 1015 22.3.2 d/a data registers 0h and 1h (dadr0h an d dadr1h) ........................... 1015 22.3.3 d/a data registers 0l and 1l (dadr0l an d dadr1l) ............................. 1016 22.3.4 d/a data register 01t (dadr01t) .............................................................. 1016 22.3.5 d/a control register 01 (da cr01) .............................................................. 1017 22.3.6 usage as an 8-bit d/a conver ter ................................................................... 1018 22.4 operation ...................................................................................................................... .. 1019 22.5 usage notes .................................................................................................................... 1021 22.5.1 module stop st ate settin g .............................................................................. 1021 22.5.2 d/a output hold function in software standby mode.................................. 1021 22.5.3 notes on deep softwa re standby mode ......................................................... 1021 22.5.4 limitations on emulator s................................................................................ 1021 section 23 ram ..............................................................................................1023 section 24 flash memory ................................................................................1025 24.1 features....................................................................................................................... .... 1025 24.2 mode transition diagram............................................................................................... 1028 24.3 memory mat conf iguratio n ......................................................................................... 1030 24.4 block structure ............................................................................................................... 1 031 24.4.1 block diagram of h8sx/1 652........................................................................ 1031 24.4.2 block diagram of h8sx/1 655........................................................................ 1032 24.5 programming/erasin g interface ...................................................................................... 1033 24.6 input/output pins............................................................................................................ 10 35 24.7 register desc riptions...................................................................................................... 1036 24.7.1 programming/erasing inte rface regist ers ...................................................... 1037 24.7.2 programming/erasing inte rface parame ters ................................................... 1044 24.7.3 ram emulation regist er (ramer).............................................................. 1056 24.8 on-board progra mming m ode ....................................................................................... 1057 24.8.1 sci boot mode ............................................................................................... 1057 24.8.2 usb boot mode.............................................................................................. 1061 24.8.3 user programm ing mode ................................................................................ 1065 24.8.4 user boot mode.............................................................................................. 1075 24.8.5 on-chip program and storable area for program data ................................. 1079 24.9 protection..................................................................................................................... ... 1085 rev. 2.00 oct. 20, 2009 page xxviii of xxx 24.9.1 hardware protection ....................................................................................... 1085 24.9.2 software prot ection......................................................................................... 1086 24.9.3 error protect ion .............................................................................................. 1086 24.10 flash memory emula tion using ram........................................................................... 1088 24.11 switching between user mat and user boot mat...................................................... 1091 24.12 programmer mode .......................................................................................................... 1092 24.13 standard serial communications inte rface specifications fo r boot mo de .................... 1092 24.14 usage notes .................................................................................................................... 1121 section 25 boundary scan............................................................................... 1123 25.1 features....................................................................................................................... .... 1123 25.2 block diagram of bounda ry scan fu nction ................................................................... 1124 25.3 input/output pins............................................................................................................ 11 24 25.4 register desc riptions...................................................................................................... 1125 25.4.1 instruction regist er (jtir) ............................................................................. 1126 25.4.2 bypass register (jtbpr) ............................................................................... 1127 25.4.3 boundary scan regist er (jtbsr) .................................................................. 1127 25.4.4 idcode register (jtid) ............................................................................... 1132 25.5 operations..................................................................................................................... .. 1133 25.5.1 tap contro ller ............................................................................................... 1133 25.5.2 commands ...................................................................................................... 1134 25.6 usage notes .................................................................................................................... 1136 section 26 clock pulse generator................................................................... 1137 26.1 register desc ription ....................................................................................................... 1139 26.1.1 system clock control register (s ckcr) ...................................................... 1139 26.2 oscilla tor ..................................................................................................................... ... 1142 26.2.1 connecting crystal resonato r ........................................................................ 1142 26.2.2 external cloc k input ....................................................................................... 1143 26.3 pll circuit .................................................................................................................... . 1144 26.4 frequency divider .......................................................................................................... 1144 26.5 usage notes .................................................................................................................... 1145 26.5.1 notes on clock puls e generator ..................................................................... 1145 26.5.2 notes on reso nator......................................................................................... 1146 26.5.3 notes on boar d design ................................................................................... 1146 section 27 power-down modes...................................................................... 1149 27.1 features....................................................................................................................... .... 1149 27.2 register desc riptions...................................................................................................... 1153 27.2.1 standby control regi ster (sby cr) ............................................................... 1153 rev. 2.00 oct. 20, 2009 page xxix of xxx 27.2.2 module stop control registers a and b (mstpcra and mstpcrb) ........ 1156 27.2.3 module stop control re gister c (m stpcrc) ............................................... 1159 27.2.4 deep standby control re gister (dps bycr)................................................. 1160 27.2.5 deep standby wait contro l register (dpswcr) .......................................... 1163 27.2.6 deep standby interrupt enab le register (dpsier) ....................................... 1165 27.2.7 deep standby interrupt flag register (d psifr)............................................ 1167 27.2.8 deep standby interrupt edge register (d psiegr) ....................................... 1169 27.2.9 reset status regist er (rstsr)....................................................................... 1170 27.2.10 deep standby backup re gister (dpsbkrn) ................................................. 1171 27.3 multi-clock f unction ..................................................................................................... 1172 27.4 module stop state........................................................................................................... 117 2 27.5 sleep mode ..................................................................................................................... 1173 27.5.1 entry to sleep mode ....................................................................................... 1173 27.5.2 exit from slee p mode..................................................................................... 1173 27.6 all-module-clock- stop m ode........................................................................................ 1174 27.7 software sta ndby mode .................................................................................................. 1175 27.7.1 entry to software standby mode.................................................................... 1175 27.7.2 exit from software standby m ode ................................................................. 1175 27.7.3 setting oscillation settling time after ex it from software standby mode.... 1176 27.7.4 software standby mode a pplication example............................................... 1178 27.8 deep software standby mode ........................................................................................ 1179 27.8.1 entry to deep softwa re standby mode .......................................................... 1179 27.8.2 exit from deep softwa re standby mode ........................................................ 1180 27.8.3 pin state on exit from deep software sta ndby mode .................................... 1181 27.8.4 b operation after exit from deep software standby mode ......................... 1182 27.8.5 setting oscillation settling time after exit from deep software standby mode ............................................................................................................... 1183 27.8.6 deep software standby mode application example ..................................... 1185 27.8.7 flowchart of deep software standby mode op eration .................................. 1189 27.9 hardware standby mode ................................................................................................ 1191 27.9.1 transition to hardware standby mode ........................................................... 1191 27.9.2 clearing hardware standby m ode.................................................................. 1191 27.9.3 hardware standby mode timing.................................................................... 1191 27.9.4 timing sequence at power- on ....................................................................... 1192 27.10 sleep instruction ex ception hand ling ............................................................................ 1193 27.11 | clock output control................................................................................................ 1196 27.12 usage notes .................................................................................................................... 1197 27.12.1 i/o port st atus................................................................................................. 1197 27.12.2 current consumption du ring oscillation settli ng standby pe riod ................. 1197 27.12.3 module stop state of ex dmac, dmac, or dtc ........................................ 1197 rev. 2.00 oct. 20, 2009 page xxx of xxx 27.12.4 on-chip peripheral mo dule interr upts ........................................................... 1197 27.12.5 writing to mstpcra, mstp crb, and ms tpcrc..................................... 1197 27.12.6 control of input buffers by dirqne (n = 3 to 0) ........................................... 1198 27.12.7 conflict between a transition to deep software standby mode and interrupt s ......................................................................................................... 1198 27.12.8 b output st ate .............................................................................................. 1198 section 28 list of registers............................................................................. 1199 28.1 register addresses (a ddress order)............................................................................... 1200 28.2 register bits .................................................................................................................. . 1219 28.3 register states in ea ch operating mode ........................................................................ 1250 section 29 electrical characteristics ............................................................... 1271 29.1 absolute maximu m ratings ........................................................................................... 1271 29.2 dc characteristics (h 8sx/1655 gr oup) ........................................................................ 1272 29.3 dc characteristics (h8s x/1655m gr oup)..................................................................... 1275 29.4 ac character istics .......................................................................................................... 127 8 29.4.1 clock timing .................................................................................................. 1279 29.4.2 control signal timing .................................................................................... 1281 29.4.3 bus timi ng ..................................................................................................... 1282 29.4.4 dmac/exdmac timing ............................................................................. 1298 29.4.5 timing of on-chip peri pheral modu les ......................................................... 1302 29.5 usb character istics ........................................................................................................ 1309 29.6 a/d conversion char acteristic s ..................................................................................... 1310 29.7 d/a conversion char acteristic s ..................................................................................... 1312 29.8 flash memory char acteristi cs ........................................................................................ 1313 29.9 power-on reset circuit and voltage-d etection circuit characteristics (h8sx/1655m group).................................................................................................... 1314 appendix ........................................................................................................... 1317 a. port states in e ach pin st ate........................................................................................... 1317 b. product lineup................................................................................................................ 1 322 c. package dime nsions ....................................................................................................... 1323 d. treatment of un used pins............................................................................................... 1325 main revisions and additions in this edition................................................... 1327 index ................................................................................................................. 1333 section 1 overview rev. 2.00 oct. 20, 2009 page 1 of 1340 rej09b0499-0200 section 1 overview 1.1 features the core of each product in the h8sx/1655 group and the h8sx/1655m group of cisc (complex instruction set computer) microcontrollers is an h8sx cpu, which has an internal 32- bit architecture. the h8sx cpu provides upward-compatibility with the cpus of other renesas technology-original microcontrollers; h8/300, h8/300h, and h8s. as peripheral functions, each lsi of the grou p includes a dma controller and an exdma controller, which enable high-speed data transfer, and a bus-state controller, which enables direct connection to different kinds of memory. the lsi of the group also includes serial communication interfaces, a/d and d/a converters , and a multi-function timer that makes motor control easy. together, the module s realize low-cost configuratio ns for end systems. the power consumption of these modules is kept down dynamically by an on-chip power-management function. the on-chip rom is a flash memory (f-ztat tm *) with a capacity of 512 kbytes (h8sx/1655 and h8sx/1655m) or 384 kbytes (h8sx/1652 and h8sx/1652m). note: * f-ztat tm is a trademark of renesas technology corp. 1.1.1 applications examples of the applicati ons of this lsi include pc peripheral equipment, optical storage devices, office automation equipment, and industrial equipment. section 1 overview rev. 2.00 oct. 20, 2009 page 2 of 1340 rej09b0499-0200 1.1.2 overview of functions table 1.1 lists the functions of this lsi in ou tline. table 1.2 shows the comparison of support functions in each group. table 1.1 overview of functions classification module/ function description rom ? rom capacity: 512 kbytes or 384 kbytes memory ram ? ram capacity: 40 kbytes cpu ? 32-bit high-speed h8sx cpu (cisc type) upwardly compatible for h8/300, h8/300h, and h8s cpus at object level ? general-register architecture (six teen 16-bit general registers) ? 11 addressing modes ? 4-gbyte address space program: 4 gbytes available data: 4 gbytes available ? 87 basic instructions, classifiable as bit arithmetic and logic instructions, multiply and divide instructions, bit manipulation instructions, multiply-and-accumulate instructions, and others ? minimum instruction execution time: 20.0 ns (for an add instruction while system clock i = 50 mhz and v cc = 3.0 to 3.6 v) ? on-chip multiplier (16 16 32 bits) ? supports multiply-and-accumulate instructions (16 16 + 42 42 bits) cpu operating mode ? advanced mode normal, middle, or maximum mode is not supported. section 1 overview rev. 2.00 oct. 20, 2009 page 3 of 1340 rej09b0499-0200 classification module/ function description cpu mcu operating mode mode 1: user boot mode (selected by driving the md2 and md1 pins low and driving the md0 pin high) mode 2: boot mode (selected by driving the md2 and md0 pins low and driving the md1 pin high) mode 3: boundary scan enabled single-chip mode (selected by driving the md2 pin low and driving the md1 and md0 pins high) mode 4: on-chip rom disabled external extended mode, 16-bit bus (selected by driving the md1 and md0 pins low and driving the md2 pin high) mode 5: on-chip rom disabled external extended mode, 8-bit bus (selected by driving the md1 pin low and driving the md2 and md0 pins high) mode 6: on-chip rom enabled external extended mode (selected by driving the md0 pin low and driving the md2 and md1 pins high) mode 7: single-chip mode (can be externally extended) (selected by driving the md2, md1, and md0 pins high) ? low power consumption state (t ransition driven by the sleep instruction) power on reset (por) * ? at power-on or low power supply voltage, an internal reset signal is generated voltage detection circuit (lvd) * ? at low power supply voltage, an internal reset signal and an interrupt are generated interrupt (source) interrupt controller (intc) ? 13 external interrupt pins (nmi, and irq11 to irq0 ) ? internal interrupt sources h8sx/1655 group: 119 pins h8sx/1655m group: 120 pins ? 2 interrupt control modes (specif ied by the interrupt control register) ? 8 priority orders specifiable (by setting the interrupt priority register) ? independent vector addresses section 1 overview rev. 2.00 oct. 20, 2009 page 4 of 1340 rej09b0499-0200 classification module/ function description interrupt (source) break interrupt (ubc) ? break point can be set for four channels ? address break can be set for cpu instruction fetch cycles exdma controller (exdmac) ? 4-channel dma transfer available ? 2 activation methods (auto-request, external request) ? 4 transfer modes (normal transfer, repeat transfer, block transfer, cluster transfer) ? dual or single address mode selectable ? extended repeat-area function dma controller (dmac) ? 4-channel dma transfer available ? 3 activation methods (auto-request, on-chip module interrupt, external request) ? 3 transfer modes (normal transfer, repeat transfer, block transfer) ? dual or single address mode selectable ? extended repeat-area function dma data transfer controller (dtc) ? allows dma transfer over 78 channels (number of dtc activation sources) ? activated by interrupt sources (chain transfer enabled) ? 3 transfer modes (normal transfer, repeat transfer, block transfer mode) ? short-address mode or full-address mode selectable ? 16-mbyte external address space external bus extension bus controller (bsc) ? the external address space can be divided into 8 areas, each of which is independently controllable ? chip-select signals ( cs0 to cs7 ) can be output ? access in 2 or 3 states can be selected for each area ? program wait cycles can be inserted ? the period of cs assertion can be extended ? idle cycles can be inserted ? bus arbitration function (arbitrates bus mastership among the internal cpu, dmac, exdmac, and dtc, and external bus masters) section 1 overview rev. 2.00 oct. 20, 2009 page 5 of 1340 rej09b0499-0200 classification module/ function description bus formats ? external memory interfaces (for the connection of rom, burst rom, sram, and byte control sram) ? address/data bus format: support for both separate and multiplexed buses (8-bit access or 16-bit access) external bus extension bus controller (bsc) ? endian conversion function for connecting devices in little- endian format clock clock pulse generator (cpg) ? 1 clock generation circuit available ? separate clock signals are provided for each of functional modules (detailed below) and eac h is independently specifiable (multi-clock function) ? system-intended data transfer modules, i.e. the cpu, runs in synchronization with the system clock (i ): 8 to 50 mhz ? internal peripheral functions run in synchronization with the peripheral module clock (p ): 8 to 35 mhz ? modules in the external space are supplied with the external bus clock (b ): 8 to 50 mhz ? includes a pll frequency multiplication circuit and frequency divider, so the operating frequency is selectable ? 5 low-power-consumption modes: sleep mode, all-module- clock-stop mode, software standby mode, deep software standby mode, and hardware standby mode section 1 overview rev. 2.00 oct. 20, 2009 page 6 of 1340 rej09b0499-0200 classification module/ function description a/d converter a/d converter (adc) ? 10-bit resolution 2 units ? selectable input channel and unit configuration 4 channels 2 units (units 0 and 1) 8 channels one unit (unit 0) ? sample and hold function included ? conversion time: 1.0 s per channel (with peripheral module clock (p ) at 25-mhz operation) ? 2 operating modes: single mode and scan mode ? 3 ways to start a/d conversion: unit 0: software, timer (tpu (unit 0) /tmr (units 0 and 1)) trigger, and external trigger unit 1: software, tmr (units 2 and 3) trigger, and external trigger ? activation of dtc and dmac by adi interrupt: unit 0: dtc and dmac can be activated by an adi interrupt. unit 1: dmac can be activated by an adi1 interrupt. d/a converter d/a converter (dac) ? 10-bit resolution 2 output channels ? output voltage: 0 v to vref, maximum conversion time: 10 s (with 20-pf load) 8-bit timer (tmr) ? 8 bits 8 channels (can be used as 16 bits four channels) ? select from among 7 clock sources (6 internal clocks and 1 external clock) ? allows the output of pulse tr ains with a desired duty cycle or pwm signals timer 16-bit timer pulse unit (tpu) ? 16 bits 12 channels (unit 0, unit 1 * ) ? select from among 8 counter-input clocks for each channel ? up to 24 pulse inputs and outputs ? counter clear operation, simultaneous writing to multiple timer counters (tcnt), simultaneous clearing by compare match and input capture possible, simultaneous input/output for registers possible by counter synchronous operation, and up to 15-phase pwm output possible by combination with synchronous operation ? buffered operation, cascaded operation (32 bits two channels), and phase counting mode (two-phase encoder input) settable for each channel ? input capture function supported ? output compare function (by the output of compare match waveform) supported note: * pin function of unit 1 cannot be used in the external bus extended mode. section 1 overview rev. 2.00 oct. 20, 2009 page 7 of 1340 rej09b0499-0200 classification module/ function description timer program- mable pulse generator (ppg) ? 24-bit * 1 * 2 pulse output ? 4 output groups, non-overlappi ng mode, and inverted output can be set ? selectable output trigger sign als; the ppg can operate in conjunction with the data transf er controller (dtc) and the dma controller (dmac) notes: 1. pulse output pins po31 to po16 cannot be activated by input capture. 2. pulse of unit 1 cannot be output in the external bus extended mode. watchdog timer watchdog timer (wdt) ? 8 bits one channel (selectable from eight counter input clocks) ? switchable between watchdog timer mode and interval timer mode serial interface ? 6 channels (select asynchronous or clock synchronous serial communications mode) ? full-duplex communications capability ? select the desired bit rate and lsb-first or msb-first transfer ? average transfer rate clock input from tmr (sci_5, sci_6) ? irda transmission and recepti on conformant with the irda specifications version 1.0 ? on-chip cyclic redundancy check (crc) calculator for improved reliability in data transfer smart card/sim serial communi- cations interface (sci) ? the sci module supports a smart card (sim) interface. i 2 c bus interface i 2 c bus interface 2 (iic2) ? 2 channels ? bus can be directly driven (the scl and sda pins are nmos open drains). universal serial bus interface universal serial bus interface (usb) ? on-chip udc (usb device controller) supporting usb 2.0 and transceiver ? transfer speed: full-speed (12 mbps) ? bulk transfer by dma ? self-power mode and bus power mode selectable i/o ports ? 9 cmos input-only pins ? 75 cmos input/output pins ? 8 large-current drive pins (port 3) ? 40 pull-up resistors ? 16 open drains package ? lqfp-120 package ? lga-145 package section 1 overview rev. 2.00 oct. 20, 2009 page 8 of 1340 rej09b0499-0200 classification module/ function description emulator ? full-spec emulator (e6000h) * ? on-chip emulator (e10a-usb) note: * e6000h of the h8sx/1668 group can be used excluding a part of function of a/ d and d/a though the h8sx/1655 group is not supporting e6000h. for details on functions for which e6000h cannot be used, see section 21, a/d converter and section 22, d/a converter. operating frequency/ power supply voltage ? operating frequency: 8 to 50 mhz ? power supply voltage: v cc = pllv cc = drv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v ? flash programming/erasure voltage: 3.0 to 3.6 v ? supply current: ? 50 ma (typ.) (v cc = pllv cc = drv cc = 3.0 v, av cc = 3.0 v, i = p = b = 35 mhz ) operating peripheral temperature ( c) ? ? 20 to +75 c (regular specifications) ? ? 40 to +85 c (wide-range specifications) note: * supported only by the h8sx/1655m group. table 1.2 comparison of support functions in the h8sx/1655 and h8sx/1655m groups function h8sx/1655 group h8sx/1655m group dmac o o dtc o o ppg o o ubc o o sci o o iic2 o o tmr o o wdt o o 10-bit adc o o 10-bit dac o o exdmac o o por/lvd ? o lqfp-120 o o package lga-145 o o section 1 overview rev. 2.00 oct. 20, 2009 page 9 of 1340 rej09b0499-0200 1.2 list of products table 1.3 is the list of products, and figure 1.1 shows how to read the product name code. table 1.3 list of products group part no. rom capacity ram capacity p ackage remarks r5f61655n50fpv 512 kbytes 40 kbytes lqfp-120 r5f61652n50fpv 384 kbytes 40 kbytes lqfp-120 r5f61655n50lgv 512 kbytes 40 kbytes lga-145 r5f61652n50lgv 384 kbytes 40 kbytes lga-145 regular specifications r5f61655d50fpv 512 kbytes 40 kbytes lqfp-120 r5f61652d50fpv 384 kbytes 40 kbytes lqfp-120 R5F61655D50LGV 512 kbytes 40 kbytes lga-145 h8sx/1655 r5f61652d50lgv 384 kbytes 40 kbytes lga-145 wide range specifications r5f61655mn50fpv 512 kbytes 40 kbytes lqfp-120 r5f61652mn50fpv 384 kbytes 40 kbytes lqfp-120 r5f61655mn50lgv 512 kbytes 40 kbytes lga-145 r5f61652mn50lgv 384 kbytes 40 kbytes lga-145 regular specifications r5f61655md50fpv 512 kbytes 40 kbytes lqfp-120 r5f61652md50fpv 384 kbytes 40 kbytes lqfp-120 r5f61655md50lgv 512 kbytes 40 kbytes lga-145 h8sx/1655m r5f61652md50lgv 384 kbytes 40 kbytes lga-145 wide range specifications section 1 overview rev. 2.00 oct. 20, 2009 page 10 of 1340 rej09b0499-0200 part no. indicates the pb-free version. indicates a renesas semiconductor product. indicates the package. fp: lqfp lg: lga indicates the product-specific number. n : regular specifications d : wide range specifications indicates the type of rom device. f: on-chip flash memory product classification microcontroller r 5 f 61655n50 lg v figure 1.1 how to read the product name code section 1 overview rev. 2.00 oct. 20, 2009 page 11 of 1340 rej09b0499-0200 ? small package package package code body size pin pitch lqfp-120 plqp0120la-a (fp-120bv) * 14.0 14.0 mm 0.40 mm lga-145 ptlg0145jb-a (tlp-145v) * 9.0 9.0 mm 0.65 mm note: * pb-free version section 1 overview rev. 2.00 oct. 20, 2009 page 12 of 1340 rej09b0499-0200 1.3 block diagram internal system bus internal peripheral bus external bus [legend] notes: 1. in single-chip mode, the port d and port e functions can be used in the initial state. pin functions are selectable by setting the pcjke bit in pfcrd. ports d and e are enabled when pcjke = 0 (initial value) and ports j and k are enabled when pcjke = 1. in external extended mode, only ports d and e can be used. 2. supported only by the h8sx/1655m group. cpu: dtc: bsc: dmac: exdmac: wdt: central processing unit data transfer controller bus controller dma controller exdma controller watchdog timer 8-bit timer 16-bit timer pulse unit programmable pulse generator serial communications interface universal serial bus interface iic bus interface 2 power-on reset / low voltage detection circuit tmr: tpu: ppg: sci: usb: iic2: por/lvd * 2 : internal system bus interrupt controller h8sx cpu ram rom dtc clock pulse generator bsc dmac 4 channels exdmac 4 channels iic2 2 channels sci 6 channels tpu 6 channels (unit 0) tmr 2 channels (unit 1) tmr 2 channels (unit 0) tmr 2 channels (unit 3) tmr 2 channels (unit 2) wdt tpu 6 channels (unit 1) ppg 8 channels (unit 0) ppg 16 channels (unit 1) 10-bit ad 4 channels (unit 0) 10-bit ad 4 channels (unit 1) port 1 port 2 port m port 6 port a port b port d/ port j ? 1 port e/ port k ? 1 port f port h port i 10-bit da 2 channels port 5 usb por/lvd * 2 figure 1.2 block diagram section 1 overview rev. 2.00 oct. 20, 2009 page 13 of 1340 rej09b0499-0200 1.4 pin assignments 1.4.1 pin assignments pk7/po31/tioca11/tiocb11 pk6/po30/tioca11 pk5/po29/tioca10/tiocb10 pj5/po21/tioca7/tiocb7/tclkg pj4/po20/tioca7 pj3/po19/tiocc6/tiocd6/tclkf pj2/po18/tiocc6/tclke pk4/po28/tioca10 pk3/po27/tiocc9/tiocd9 pk2/po26/tiocc9 pk1/po25/tioca9/tiocb9 pk0/po24/tioca9 pj7/po23/tioca8/tiocb8/tclkh pj6/po22/tioca8 pj0/po16/tioca6 pj1/po17/tioca6/tiocb6 * 1 * 1 pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b pb2/ cs2 -a/ cs6 -a pb3/ cs3 / cs7 -a md2 pm0/txd6 pm1/rxd6 pm2 pf4/a20 pf3/a19 vss pf2/a18 pf1/a17 pf0/a16 pe7/a15 pe6/a14 pe5/a13 vss pe4/a12 vcc pe3/a11 pe2/a10 pe1/a9 pe0/a8 pd7/a7 pd6/a6 vss pd5/a5 pd4/a4 pd3/a3 pd2/a2 p61/tmci2/rxd4/ tend2 / irq9 -b/ etend0 -b p60/tmri2/txd4/ dreq2 / irq8 -b/ edreq0 -b stby p17/tclkd/scl0/ adtrg1 / irq7 -a/ edrak1 p16/tclkc/sda0/ dack1 / irq6 -a/ edack1 -a vcc extal xtal vss wdtovf /tdo p15/tclkb/rxd5/irrxd/scl1/ tend1 / irq5 -a/ etend1 -a p14/tclka/tixd5/irtxd/sda1/ dreq1 / irq4 -a/ edreq1 -a v cl res vss p13/ adtrg0 / irq3 -a/ edrak0 p12/sck2/ dack0 / irq2 -a/ edack0 -a p11/rxd2/ tend0 / irq1 -a/ etend0 -a p10/txd2/ dreq0 / irq0 -a/ edreq0 -a pi7/d15 pi6/d14 pi5/d13 pi4/d12 vss pi3/d11 pi2/d10 pi1/d9 pi0/d8 vcc ph7/d7 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p62/tmo2/sck4/ dack2 / irq10 -b/ trst / edack0 -b pllvcc p63/tmri3/ dreq3 / irq11 -b/tms/ edreq1 -b pllvss p64/tmci3/ tend3 /tdi/ etend1 -b p65/tmo3/ dack3 /tck/ edack1 -b md0 p50/an0/ irq0 -b p51/an1/ irq1 -b p52/an2/ irq2 -b avcc p53/an3/ irq3 -b avss p54/an4/ irq4 -b vref p55/an5/ irq5 -b p56/an6/da0/ irq6 -b p57/an7/da1/ irq7 -b md1 pa0/ breqo / bs -a pa1/ back /(rd/ wr ) pa2/ breq / wait pa3/ llwr / llb pa4/ lhwr / lub pa5/ rd pa6/ as / ah / bs -b vss pa7/b vcc pb0/ cs0 / cs4 / cs5 -b 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 ph6/d6 ph5/d5 ph4/d4 vss ph3/d3 ph2/d2 ph1/d1 ph0/d0 nmi p27/po7/tioca5/tiocb5 p26/po6/tioca5/tmo1/txd1 p25/po5/tioca4/tmci1/rxd1 p24/po4/tioca4/tiocb4/tmri1/sck1 p23/po3/tiocc3/tiocd3/ irq11 -a p22/po2/tiocc3/tmo0/txd0/ irq10 -a p21/po1/tioca3/tmci0/rxd0/ irq9 -a vcc p20/po0/tioca3/tiocb3/tmri0/sck0/ irq8 -a vss md_clk vbus drvss usd- usd+ drvcc pm4 pm3 emle * 2 pd0/a0 pd1/a1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lqfp-120 (top view) notes: 1. in single-chip mode ports d and e can be used (initial state). pin functions are selectable by setting the pcjke bit in pfcrd. ports d and e are enabled when pcjke = 0 (initial value) and ports j and k are enabled when pcjke = 1. in external extended mode, only ports d and e can be used. 2. this pin is an on-chip emulator enable pin. drive this pin low for the connection in normal operating mode. the on-chip emulator function is enabled by driving this pin high. when the on-chip emulator is in use, the p62, p63, p64, p65, and wdtovf pins are dedicated pins for the on-chip emulator. for details on a connection example with the e10a, see e10a emulator user's manual. figure 1.3 pin assignments (lqfp-120: h8sx/1655 group and h8sx/1655m group) section 1 overview rev. 2.00 oct. 20, 2009 page 14 of 1340 rej09b0499-0200 1 a b c d e f g h j k l m n a b c d e f g h j k l m n 2345678910111213 123456789101112 13 pb1 pa7 vcc pa4 pa 1 n c * 3 p57 vref p50 p65 pllvss pllvcc p61 pb2 vss pa2 nc * 3 md1 p54 avcc p52 nc * 3 p64 p62 p60 pa 6 pa 5 n c * 3 nc * 3 avss p51 nc * 3 p63 nc * 3 nc * 3 pm1 md2 pm0 vcc pa 3 pa 0 p56 p55 p53 md0 nc * 3 vss stby nc * 3 nc * 3 p17 p16 xtal extal pb0 nc * 3 pb3 vss nc * 3 pm2 nc * 3 pf2 pf4 vss pf3 vcc p15 vss wdtovf pe6 /pk6 * 1 pf1 pe7 /pk7 * 1 vss p14 p13 vss res pe4 /pk4 * 1 pe5 /pk5 * 1 pe3 /pk3 * 1 pf0 v cl p11 nc * 3 nc * 3 pe1 /pk1 * 1 vcc pd7 /pj7 * 1 pe2 /pk2 * 1 pi7 p10 p12 pi6 pd5 /pj5 * 1 pe0 /pk0 * 1 pd4 /pj4 * 1 pd6 /pj6 * 1 vcc p21 p25 p26 nc * 3 ph2 pi4 pi5 vss vss pd3 /pj3 * 1 emle * 2 vbus md_clk p24 nc * 3 nc * 3 nmi ph1 pi2 pi3 pi1 pd1 /pj1 * 1 pd2 /pj2 * 1 drvcc usd- vss p20 p23 nc * 3 ph0 vss ph4 ph7 pi0 pm3 pd0 /pj0 * 1 pm4 usd+ drvss p22 nc * 3 p27 vcc ph3 ph5 ph6 vcc lga-145 (perspective top view) notes: 1. in single-chip mode ports d and e can be used (initial state). pin functions are selectable by setting the pcjke bit in pfcrd. ports d and e are enabled when pcjke = 0 (initial value) and ports j and k are enabled when pcjke = 1. in external extended mode, only ports d and e can be used. 2. this pin is an on-chip emulator enable pin. drive this pin low for the connection in normal operating mode. the on-chip emulator function is enabled by driving this pin high. when the on-chip emulator is in use, the p62, p63, p64, p65, and wdtovf pins are dedicated pins for the on-chip emulator. for details on a connection example with the e10a, see e10a emulator user's manual. 3. leave nc pin open. figure 1.4 pin assignments (lga-145: h8sx/1655 group and h8sx/1655m group) section 1 overview rev. 2.00 oct. 20, 2009 page 15 of 1340 rej09b0499-0200 1.4.2 correspondence between pin configuration and operating modes table 1.4 pin configuration in each operating mode (h8sx/1655 group and h8sx/1655m group) pin no. pin name lqfp-120 lga-145 modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 1 a1 pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b 2 b1 pb2/ cs2 -a/ cs6 -a pb2/ cs2 -a/ cs6 -a pb2/ cs2 -a/ cs6 -a 3 c1 pb3/ cs3 / cs7 -a pb3/ cs3 / cs7 -a pb3/ cs3 / cs7 -a 4 d1 md2 md2 md2 5 d3 pm0/txd6 pm0/txd6 pm0/txd6 6 d2 pm1/rxd6 pm1/rxd6 pm1/rxd6 7 e1 pm2 pm2 pm2 8 f1 pf4/a20 pf4/a20 pf4/a20 9 f4 pf3/a19 pf3/a19 pf3/a19 10 f3 vss vss vss 11 f2 pf2/a18 pf2/a18 pf2/a18 12 g1 pf1/a17 pf1/a17 pf1/a17 13 h4 pf0/a16 pf0/a16 pf0/a16 14 g3 pe7/a15 ? pe7/a15 ? pk7/po31/tioca11/tiocb11 * 1 a15 15 g2 pe6/a14 ? pe6/a14 ? pk6/po30/tioca11 * 1 a14 16 h1 pe5/a13 ? pe5/a13 ? pk5/po29/tioca10/tiocb10 * 1 a13 17 g4 vss vss vss 18 h2 pe4/a12 ? pe4/a12 ? pk4/po28/tioca10 * 1 a12 19 j1 vcc vcc vcc 20 h3 pe3/a11 ? pe3/a11 ? pk3/po27/tiocc9/tiocd9 * 1 a11 21 j4 pe2/a10 ? pe2/a10 ? pk2/po26/tiocc9 * 1 a10 section 1 overview rev. 2.00 oct. 20, 2009 page 16 of 1340 rej09b0499-0200 pin no. pin name lqfp-120 lga-145 modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 22 j2 pe1/a9 ? pe1/a9 ? pk1/po25/tioca9/tiocb9 * 1 a9 23 k1 pe0/a8 ? pe0/a8 ? pk0/po24/tioca9 * 1 a8 24 j3 pd7/a7 ? pd7/a7 ? pj7/po23/tioca8/tiocb8/ tclkh * 1 a7 25 k4 pd6/a6 ? pd6/a6 ? pj6/po22/tioca8 * 1 a6 26 l2 vss vss vss 27 k2 pd5/a5 ? pd5/a5 ? pj5/po21/tioca7/tiocb7/ tclkg * 1 a5 28 k3 pd4/a4 ? pd4/a4 ? pj4/po20/tioca7 * 1 a4 29 l1 pd3/a3 ? pd3/a3 ? pj3/po19/tiocc6/tiocd6/ tclkf * 1 a3 30 m1 pd2/a2 ? pd2/a2 ? pj2/po18/tiocc6/tclke * 1 a2 31 m2 pd1/a1 ? pd1/a1 ? pj1/po17/tioca6/tiocb6 * 1 a1 32 n1 pd0/a0 ? pd0/a0 ? pj0/po16/tioca6 * 1 a0 33 l3 emle emle emle 34 n2 pm3 pm3 pm3 35 n3 pm4 pm4 pm4 36 m3 drvcc drvcc drvcc 37 n4 usd + usd + usd + 38 m4 usd ? usd ? usd ? 39 n5 drvss drvss drvss 40 l4 vbus vbus vbus section 1 overview rev. 2.00 oct. 20, 2009 page 17 of 1340 rej09b0499-0200 pin no. pin name lqfp-120 lga-145 modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 41 l5 md_clk md_clk md_clk 42 m5 vss vss vss 43 m6 p20/po0/tioca3/tiocb3/ tmri0/sck0/ irq8 -a p20/po0/tioca3/tiocb3/ tmri0/sck0/ irq8 -a p20/po0/tioca3/tiocb3/ tmri0/sck0/ irq8 -a 44 k5 vcc vcc vcc 45 k6 p21/po1/tioca3/tmci0/ rxd0/ irq9 -a p21/po1/tioca3/tmci0/rxd0/ irq9 -a p21/po1/tioca3/tmci0/ rxd0/ irq9 -a 46 n6 p22/po2/tiocc3/tmo0/ txd0/ irq10 -a p22/po2/tiocc3/tmo0/txd0/ irq10 -a p22/po2/tiocc3/tmo0/txd0/ irq10 -a 47 m7 p23/po3/tiocc3/tiocd3/ irq11 -a p23/po3/tiocc3/tiocd3/ irq11 -a p23/po3/tiocc3/tiocd3/ irq11 -a 48 l6 p24/po4/tioca4/tiocb4/ tmri1/sck1 p24/po4/tioca4/tiocb4/ tmri1/sck1 p24/po4/tioca4/tiocb4/ tmri1/sck1 49 k7 p25/po5/tioca4/tmci1/ rxd1 p25/po5/tioca4/tmci1/ rxd1 p25/po5/tioca4/tmci1/ rxd1 50 k8 p26/po6/tioca5/tmo1/ txd1 p26/po6/tioca5/tmo1/ txd1 p26/po6/tioca5/tmo1/ txd1 51 n8 p27/po7/tioca5/tiocb5 p27/po7/ tioca5/tiocb5 p27/po7/tioca5/tiocb5 52 l9 nmi nmi nmi 53 m9 ph0/d0 ph0/d0 d0 54 l10 ph1/d1 ph1/d1 d1 55 k10 ph2/d2 ph2/d2 d2 56 n10 ph3/d3 ph3/d3 d3 57 m10 vss vss vss 58 m11 ph4/d4 ph4/d4 d4 59 n11 ph5/d5 ph5/d5 d5 60 n12 ph6/d6 ph6/d6 d6 61 m12 ph7/d7 ph7/d7 d7 62 n9 vcc vcc vcc 63 m13 pi0/d8 pi 0/d8 pi0/d8 64 l13 pi1/d9 pi 1/d9 pi1/d9 65 l11 pi2/d10 pi 2/d10 pi2/d10 66 l12 pi3/d11 pi 3/d11 pi3/d11 section 1 overview rev. 2.00 oct. 20, 2009 page 18 of 1340 rej09b0499-0200 pin no. pin name lqfp-120 lga-145 modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 67 k13 vss vss vss 68 k11 pi4/d12 pi 4/d12 pi4/d12 69 k12 pi5/d13 pi 5/d13 pi5/d13 70 j13 pi6/d14 pi 6/d14 pi6/d14 71 j10 pi7/d15 pi 7/d15 pi7/d15 72 j11 p10/txd2/ dreq0 / irq0 -a/ edreq0 -a p10/txd2/ dreq0 / irq0 -a/ edreq0 -a p10/txd2/ dreq0 / irq0 -a/ edreq0 -a 73 h11 p11/rxd2/ tend0 / irq1 - a/ etend0 -a p11/rxd2/ tend0 / irq1 -a/ etend0 -a p11/rxd2/ tend0 / irq1 -a/ etend0 -a 74 j12 p12/sck2/ dack0 / irq2 -a/ edack0 -a p12/sck2/ dack0 / irq2 -a/ edack0 -a p12/sck2/ dack0 / irq2 -a/ edack0 -a 75 g11 p13/ adtrg0 / irq3 -a/ edrak0 p13/ adtrg0 / irq3 -a/ edrak0 p13/ adtrg0 / irq3 -a/ edrak0 76 g12 vss vss vss 77 g13 res res res 78 h10 v cl v cl v cl 79 g10 p14/tclka/txd5/irtxd/ sda1/ dreq1 / irq4 -a/ edreq1 -a p14/tclka/txd5/irtxd/ sda1/ dreq1 / irq4 -a/ edreq1 -a p14/tclka/txd5/irtxd/ sda1/ dreq1 / irq4 -a/ edreq1 -a 80 f11 p15/tclkb/rxd5/irrxd/ scl1/ tend 1/ irq5 -a/ etend1 -a p15/tclkb/rxd5/irrxd/ scl1/ tend 1/ irq5 -a/ etend1 -a p15/tclkb/rxd5/irrxd/ scl1/ tend 1/ irq5 -a/ etend1 -a 81 f13 wdtovf wdtovf /tdo * 2 wdtovf 82 f12 vss vss vss 83 e12 xtal xtal xtal 84 e13 extal extal extal 85 f10 vcc vcc vcc 86 e11 p16/tclkc/sda0/ dack1 / irq6 -a/ edack1 -a p16/tclkc/sda0/ dack1 / irq6 -a/ edack1 -a p16/tclkc/sda0/ dack1 / irq6 -a/ edack1 -a 87 e10 p17/tclkd/scl0/ adtrg1 / irq7 -a/ edrak1 p17/tclkd/scl0/ adtrg1 / irq7 -a/ edrak1 p17/tclkd/scl0/ adtrg1 / irq7 -a/ edrak1 88 d13 stby stby stby 89 b13 p60/tmri2/txd4/ dreq2 / irq8 -b/ edreq0 -b p60/tmri2/txd4/ dreq2 / irq8 -b/ edreq0 -b p60/tmri2/txd4/ dreq2 / irq8 -b/ edreq0 -b section 1 overview rev. 2.00 oct. 20, 2009 page 19 of 1340 rej09b0499-0200 pin no. pin name lqfp-120 lga-145 modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 90 a13 p61/tmci2/rxd4/ tend2 / irq9 -b/ etend0 -b p61/tmci2/rxd4/ tend2 / irq9 -b/ etend0 -b p61/tmci2/rxd4/ tend2 / irq9 -b/ etend0 -b 91 b12 p62/tmo2/sck4/ dack2 / irq10 -b/ edack0 -b p62/tmo2/sck4/ dack2 / irq10 -b/ trst * 2 / edack0 -b p62/tmo2/sck4/ dack2 / irq10 -b/ edack0 -b 92 a12 pllvcc pllvcc pllvcc 93 c11 p63/tmri3/ dreq3 / irq11 -b/ edreq1 -b p63/tmri3/ dreq3 / irq11 -b/ tms * 2 / edreq1 -b p63/tmri3/ dreq3 / irq11 -b/ edreq1 -b 94 a11 pllvss pllvss pllvss 95 b11 p64/tmci3/ tend3 / etend1 -b p64/tmci3/ tend3 /tdi * 2 / etend1 -b p64/tmci3/ tend3 / etend1 -b 96 a10 p65/tmo3/ dack3 / edack1 -b p65/tmo3/ dack3 /tck * 2 / edack1 -b p65/tmo3/ dack3 / edack1 -b 97 d10 md0 md0 md0 98 a9 p50/an0/ irq0 -b p50/an0/ irq0 -b p50/an0/ irq0 -b 99 c9 p51/an1/ irq1 -b p51/an1/ irq1 -b p51/an1/ irq1 -b 100 b9 p52/an2/ irq2 -b p52/an2/ irq2 -b p52/an2/ irq2 -b 101 b8 avcc avcc avcc 102 d9 p53/an3/ irq3 -b p53/an3/ irq3 -b p53/an3/ irq3 -b 103 c8 avss avss avss 104 b7 p54/an4/ irq4 -b p54/an4/ irq4 -b p54/an4/ irq4 -b 105 a8 vref vref vref 106 d8 p55/an5/ irq5 -b p55/an5/ irq5 -b p55/an5/ irq5 -b 107 d7 p56/an6/da0/ irq6 -b p56/an6/da0/ irq6 -b p56/an6/da0/ irq6 -b 108 a7 p57/an7/da1/ irq7 -b p57/an7/da1/ irq7 -b p57/an7/da1/ irq7 -b 109 b6 md1 md1 md1 110 d6 pa0/ breqo / bs -a pa0/ breqo / bs -a pa0/ breqo / bs -a 111 a5 pa1/ back /(rd/ wr ) pa1/ back /(rd/ wr ) pa1/ back /(rd/ wr ) 112 b4 pa2/ breq / wait pa2/ breq / wait pa2/ breq / wait 113 d5 pa3/ llwr / llb pa3/ llwr / llb llwr / llb 114 a4 pa4/ lhwr / lub pa4/ lhwr / lub pa4/ lhwr / lub 115 c5 pa5/ rd pa5/ rd rd 116 c4 pa6/ as / ah / bs -b pa6/ as / ah / bs -b pa6/ as / ah / bs -b 117 c3 vss vss vss section 1 overview rev. 2.00 oct. 20, 2009 page 20 of 1340 rej09b0499-0200 pin no. pin name lqfp-120 lga-145 modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 118 a2 pa7/b pa7/b pa7/b 119 a3 vcc vcc vcc 120 b2 pb0/ cs0 / cs4 / cs5 -b pb0/ cs0 / cs4 / cs5 -b pb0/ cs0 / cs4 / cs5 -b pin no. lga-145: c2, e2, e3, e4, e5, b5, c6, a6, c7, b10, c10, c12, c13, d11, h12, h13, k9, l7, l8, m8, n7 nc nc nc pin no. lga-145: b3, d12 vss vss vss pin no. lga-145: d4, n13 vcc vcc vcc notes: 1. these pins can be used when the pcjke bit in pfcrd is set to 1 in single-chip mode. 2. pins tdo, trst , tms, tdi, and tck are enabled in mode 3. section 1 overview rev. 2.00 oct. 20, 2009 page 21 of 1340 rej09b0499-0200 1.4.3 pin functions table 1.5 pin functions classification pin name i/o description power supply v cc input power supply pins. connect them to the system power supply. v cl input connect this pin to v ss via a 0.1- f capacitor (the capacitor should be placed close to the pin). v ss input ground pins. connect them to the system power supply (0 v). pllv cc input power supply pin for the pll ci rcuit. connect it to the system power supply. pllv ss input ground pin for the pll circuit. drv cc input power supply pin for the transceiv er with on-chip usb. connect it to the system power supply. drv ss input ground pin for the transceiver with on-chip usb. clock xtal input extal input pins for a crystal resonator. an external clock signal can be input through the extal pin. for an example of this connection, see section 26, clock pulse generator. b output outputs the system clock for external devices. md2 to md0 input pins for setting the operat ing mode. the signal levels on these pins must not be changed during operation. operating mode control md_clk input pins for switching the multiplication ratio of the clock pulse generator. the signal levels on these pins must not be changed during operation. system control res input reset signal input pin. this lsi enters the reset state when this signal goes low. stby input this lsi enters hardware standby mode when this signal goes low. emle input input pin for the on-chip emulator enable si gnal. if the on-chip emulator is used, the signal level should be fixed high. if the on-chip emulator is not used, the signal level should be fixed low. trst input tms input tdi input tck input on-chip emulator tdo output on-chip emulator pins or boundar y scan pins. when the emle pin is driven high, these pins are d edicated for the on-chip emulator. when the emle pin is driven low and to mode 3, these pins are dedicated for the boundary scan. address bus a20 to a0 output output pins for the address bits. section 1 overview rev. 2.00 oct. 20, 2009 page 22 of 1340 rej09b0499-0200 classification pin name i/o description data bus d15 to d0 input/ output input and output for the bidirectional data bus. these pins also output addresses when accessing an address?data multiplexed i/o interface space. bus control breq input external bus-master modules assert this signal to request the bus. breqo output internal bus-master modul es assert this signal to request access to the external space vi a the bus in the external bus released state. back output bus acknowledge signal, wh ich indicates that the bus has been released. bs -a/ bs -b output indicates the start of a bus cycle. as output strobe signal which indicates that the output address on the address bus is valid in access to the basic bus interface or byte control sram interface space. ah output this signal is used to hold the address when accessing the address-data multiplexed i/o interface space. rd output strobe signal which indica tes that reading from the basic bus interface space is in progress. rd/ wr output indicates the direction (input or output) of the data bus. lhwr output strobe signal which indica tes that the higher-order byte (d15 to d8) is valid in access to the basic bus interface space. llwr output strobe signal which indicates that the lower-order byte (d7 to d0) is valid in access to the basic bus interface space. lub output strobe signal which indica tes that the higher-order byte (d15 to d8) is valid in access to the byte control sram interface space. llb output strobe signal which indicates that the lower-order byte (d7 to d0) is valid in access to the byte control sram interface space. cs0 cs1 cs2 -a/ cs2 -b cs3 cs4 cs5 -a/ cs5 -b cs6 -a/ cs6 -b cs7 -a/ cs7 -b output select signals for areas 0 to 7. wait input requests wait cycles in access to the external space. section 1 overview rev. 2.00 oct. 20, 2009 page 23 of 1340 rej09b0499-0200 classification pin name i/o description interrupt nmi input non-maskable interrupt request signal. when this pin is not in use, this signal must be fixed high. irq11 -a/ irq11 -b irq10 -a/ irq10 -b irq9 -a/ irq9 -b irq8 -a/ irq8 -b irq7 -a/ irq7 -b irq6 -a/ irq6 -b irq5 -a/ irq5 -b irq4 -a/ irq4 -b irq3 -a/ irq3 -b irq2 -a/ irq2 -b irq1 -a/ irq1 -b irq0 -a/ irq0 -b input maskable interrupt request signal. dreq0 -a/ dreq0 -b dreq1 -a/ dreq1 -b dreq2 dreq3 input requests dmac activation. dack0 -a/ dack0 -b dack1 -a/ dack1 -b dack2 dack3 output dmac single address- transfer acknowledge signal. dma controller (dmac) tend0 -a/ tend0 -b tend1 -a/ tend1 -b tend2 tend3 output indicates end of data transfer by the dmac. edreq0 - a/ edreq0 -b edreq1 - a/ edreq1 -b input requests exdmac activation. edack0 - a/ edack0 -b edack1 - a/ edack1 -b output exdmac single address-tr ansfer acknowledge signal. etend0 - a/ etend0 -b etend1 - a/ etend1 -b output indicates end of data transfer by the exdmac. exdma controller (exdmac) edrak0 edrak1 output notification to external device of exdmac request acceptance and start of execution section 1 overview rev. 2.00 oct. 20, 2009 page 24 of 1340 rej09b0499-0200 classification pin name i/o description tclka tclkb tclkc tclkd input input pins for the external cl ock signals. tioca3 tiocb3 tiocc3 tiocd3 input/ output signals for tgra_3 to tgrd_3. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca4 tiocb4 input/ output signals for tgra_4 and tgrb_4. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca5 tiocb5 input/ output signals for tgra_5 and tgrb_5. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tclke tclkf tclkg tclkh input input pins for ex ternal clock signals. tioca6 tiocb6 tiocc6 tiocd6 input/ output signals for tgra_6 to tgrd_6. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca7 tiocb7 input/ output signals for tgra_7 and tgrb_7. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca8 tiocb8 input/ output signals for tgra_8 and tgrb_8. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca9 tiocb9 tiocc9 tiocd9 input/ output signals for tgra_9 to tgrd_9. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca10 tiocb10 input/ output signals for tgra_10 and tgrb_10. these pins are used as input capture inputs, output compare outputs, or pwm outputs. 16-bit timer pulse unit (tpu) tioca11 tiocb11 input/ output signals for tgra_11 and tgrb_11. these pins are used as input capture inputs, output compare outputs, or pwm outputs. programmable pulse generator (ppg) po31 to po16, po7 to po0 output output pins for the pulse signals. section 1 overview rev. 2.00 oct. 20, 2009 page 25 of 1340 rej09b0499-0200 classification pin name i/o description tmo0 to tmo7 output output pins for the compare match signals. tmci0 to tmci3 input input pins for the external cloc k signals that drive for the counters. 8-bit timer (tmr) tmri0 to tmri3 input input pins for the counter-reset signals. watchdog timer (wdt) wdtovf output output pin for the counter-overflow signal in watchdog-timer mode. serial communications interface (sci) txd0 txd1 txd2 txd4 txd5 txd6 output output pins for data transmission. rxd0 rxd1 rxd2 rxd4 rxd5 rxd6 input input pins for data reception. sck0 sck1 sck2 sck4 input/ output input/output pins for clock signals. irtxd output output pin that outputs encoded data for irda. sci with irda (sci) irrxd input input pin that inputs encoded data for irda. scl0, scl1 input/ output input/output pin for iic clock. bus can be directly driven by the nmos open drain output. i 2 c bus interface 2 (iic2) sda0, sda1 input/ output input/output pin for iic data. bus can be directly driven by the nmos open drain output. usd + usd ? input/ output input/output pin for usb data. universal serial bus interface (usb) vbus input input/output pin to connect/disconnect usb cable. an7 to an0 input input pins for the analog signals to be processed by the a/d converter. a/d converter adtrg0 , adtrg1 input input pins for the external trigger signal that starts a/d conversion. d/a converter da1, da0 output output pins for the analog signals from the d/a converter. section 1 overview rev. 2.00 oct. 20, 2009 page 26 of 1340 rej09b0499-0200 classification pin name i/o description av cc input analog power supply pin for the a/d and d/a converters. when the a/d and d/a converters are not in use, connect this pin to the system power supply. av ss input ground pin for the a/d and d/a converters. connect this pin to the system power supply (0 v). a/d converter, d/a converter vref input reference power supply pin for the a/d and d/a converters. when the a/d and d/a converters are not in use, connect this pin to the system power supply. i/o ports p17 to p10 input/ output 8-bit input/output pins. p27 to p20 input/ output 8-bit input/output pins. p57 to p50 input 8-bit input/output pins. p65 to p60 input/ output 6-bit input/output pins. pa7 input input-only pin pa6 to pa0 input/ output 7-bit input/output pins. pb3 to pb0 input/ output 4-bit input/output pins. pd7 to pd0 input/ output 8-bit input/output pins. pe7 to pe0 input/ output 8-bit input/output pins. pf4 to pf0 input/ output 5-bit input/output pins. ph7 to ph0 input/ output 8-bit input/output pins. pi7 to pi0 input/ output 8-bit input/output pins. pm4 to pm0 input/ output 5-bit input/output pins. pj7 to pj0 * input/ output 8-bit input/output pins. pk7 to pk0 * input/ output 8-bit input/output pins. note: * these pins can be used when the pcjke bit in pfcrd is set to 1 in single-chip mode. section 2 cpu rev. 2.00 oct. 20, 2009 page 27 of 1340 rej09b0499-0200 section 2 cpu the h8sx cpu is a high-speed cpu with an in ternal 32-bit architect ure that is upward compatible with the h8/300, h8/300h, and h8s cpus. the h8sx cpu has sixteen 16-bit general register s, can handle a 4-gbyte linear address space, and is ideal for a r ealtime control system. 2.1 features ? upward-compatible with h8/300, h8/300h, and h8s cpus ? can execute object programs of these cpus ? sixteen 16-bit general registers ? also usable as sixteen 8-bit registers or eight 32-bit registers ? 87 basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? bit field transfer instructions ? powerful bit-manipulation instructions ? bit condition branch instructions ? multiply-and-accumulate instruction ? eleven addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:2,ern), @(d:16,ern), or @(d:32,ern)] ? index register indirect with displ acement [@(d:16,rnl.b), @(d:32,rnl.b), @(d:16,rn.w), @(d:32,rn.w), @(d: 16,ern.l), or @(d:32,ern.l)] ? register indirect with pre-/post- increment or pre-/post-decrement [@ + ern, @ ? ern, @ern + , or @ern ? ] ? absolute address [@aa:8, @a a:16, @aa:24, or @aa:32] ? immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? program-counter relative with index re gister [@(rnl.b,pc), @(rn.w,pc), or @(ern.l,pc)] ? memory indirect [@@aa:8] ? extended memory i ndirect [@@vec:7] section 2 cpu rev. 2.00 oct. 20, 2009 page 28 of 1340 rej09b0499-0200 ? two base registers ? vector base register ? short address base register ? 4-gbyte address space ? program: 4 gbytes ? data: 4 gbytes ? high-speed operation ? all frequently-used instructions executed in one or two states ? 8/16/32-bit register-regist er add/subtract: 1 state ? 8 8-bit register-register multiply: 1 state (when the multiplier is available.) ? 16 8-bit register-register divide: 10 st ates (when the divider is available.) ? 16 16-bit register-register multiply: 1 stat e (when the multiplier is available.) ? 32 16-bit register-register divide: 18 states (when th e divider is available.) ? 32 32-bit register-register multiply: 5 stat es (when the multiplier is available.) ? 32 32-bit register-register divide: 18 states (when th e divider is available.) ? four cpu operating modes ? normal mode ? middle mode ? advanced mode ? maximum mode ? power-down modes ? transition is made by exec ution of sleep instruction ? choice of cpu operating clocks notes: 1. advanced mode is only supported as the cpu operating mode of the h8sx/1655 group and h8sx/1655m group. normal, middle, and maximum modes are not supported. 2. the multiplier and divider are supported by the h8sx/1655 group and h8sx/1655m group. section 2 cpu rev. 2.00 oct. 20, 2009 page 29 of 1340 rej09b0499-0200 2.2 cpu operating modes the h8sx cpu has four operating modes: normal, middle, advanced and maximum modes. these modes can be selected by the mode pins of this lsi. cpu operating modes normal mode maximum mode maximum 64 kbytes for program and data areas combined maximum 4 gbytes for program and data areas combined maximum 16-mbyte program area and 64-kbyte data area, maximum 16 mbytes for program and data areas combined maximum 16-mbyte program area and 4-gbyte data area, maximum 4 gbytes for program and data areas combined advanced mode middle mode figure 2.1 cpu operating modes 2.2.1 normal mode the exception vector table and stack have th e same structure as in the h8/300 cpu. ? address space the maximum address space of 64 kbytes can be accessed. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when the extended register en is used as a 16-bit register it can contain any value, even when the corresponding general register rn is used as an address register. (if the general register rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post- decrement and a carry or borrow occurs, however, the value in the corresponding extended register en will be affected.) ? instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. section 2 cpu rev. 2.00 oct. 20, 2009 page 30 of 1340 rej09b0499-0200 ? exception vector table and memo ry indirect branch addresses in normal mode, the top area starting at h'0000 is allocated to the exce ption vector table. one branch address is stored per 16 bits. the struct ure of the exception vect or table is shown in figure 2.2. h'0000 h'0001 h'0002 h'0003 reset exception vector reset exception vector exception vector table figure 2.2 exception vector table (normal mode) the memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the jmp and jsr instructions. an 8- bit absolute address included in the instruction code specifies a memory location. execution branches to the cont ents of the memory location. ? stack structure the stack structure of pc at a subroutine branch and that of pc and ccr at an exception handling are shown in figure 2.3. the pc contents are saved or restored in 16-bit units. (a) subroutine branch (b) exception handling pc (16 bits) exr * 1 reserved * 1, * 3 ccr ccr * 3 pc (16 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored on return. (sp * 2 ) figure 2.3 stack structure (normal mode) section 2 cpu rev. 2.00 oct. 20, 2009 page 31 of 1340 rej09b0499-0200 2.2.2 middle mode the program area in middle mode is extended to 16 mbytes as compared with that in normal mode. ? address space the maximum address space of 16 mbytes can be accessed as a total of the program and data areas. for individual areas, up to 16 mbytes of the program area or up to 64 kbytes of the data area can be allocated. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when the extended register en is used as a 16-bit register (in other than the jmp and jsr instructions), it can contain any value even when the corresponding general register rn is used as an address register. (if the general register rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post- decrement and a carry or borrow occurs, howev er, the value in the corresponding extended register en will be affected.) ? instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid and the up per eight bits are sign-extended. ? exception vector table and memo ry indirect branch addresses in middle mode, the top area starting at h'000000 is allocated to the exception vector table. one branch address is stored per 32 bits. the upper eight bits are ignored and the lower 24 bits are stored. the structure of the exception vector table is shown in figure 2.4. the memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the jmp and jsr instructions. an 8- bit absolute addr ess included in the instruction code specifies a memory location. execution branches to the cont ents of the memory location. in middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. the upper eight bits are reserved and assumed to be h'00. ? stack structure the stack structure of pc at a subroutine branch and that of pc and ccr at an exception handling are shown in figure 2.5. the pc contents are saved or restored in 24-bit units. section 2 cpu rev. 2.00 oct. 20, 2009 page 32 of 1340 rej09b0499-0200 2.2.3 advanced mode the data area is extended to 4 gbytes as compared with that in middle mode. ? address space the maximum address space of 4 gbytes can be linearly accessed. for individual areas, up to 16 mbytes of the program area and up to 4 gbytes of the data area can be allocated. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. ? instruction set all instructions and addressing modes can be used. ? exception vector table and memo ry indirect branch addresses in advanced mode, the top area starting at h'00000000 is allocat ed to the excep tion vector table. one branch address is stored per 32 bits. the upper eight bits are ignored and the lower 24 bits are stored. the structure of the exception vector table is shown in figure 2.4. h'00000000 h'00000003 h'00000004 exception vector table reserved reset exception vector reserved h'00000007 h'00000001 h'00000002 h'00000005 h'00000006 figure 2.4 exception vector table (middle and advanced modes) the memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the jmp and jsr instructions. an 8- bit absolute address included in the instruction code specifies a memory location. execution branches to the cont ents of the memory location. in advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. the upper eight bits are reserved and assumed to be h'00. section 2 cpu rev. 2.00 oct. 20, 2009 page 33 of 1340 rej09b0499-0200 ? stack structure the stack structure of pc at a subroutine branch and that of pc and ccr at an exception handling are shown in figure 2.5. the pc contents are saved or restored in 24-bit units. (a) subroutine branch (b) exception handling pc (24 bits) exr * 1 reserved * 1 , * 3 ccr pc (24 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored on return. (sp ) * 2 reserved figure 2.5 stack structure (middle and advanced modes) 2.2.4 maximum mode the program area is extended to 4 gbytes as compared with that in advanced mode. ? address space the maximum address space of 4 gbytes can be linearly accessed. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers. ? instruction set all instructions and addressing modes can be used. ? exception vector table and memo ry indirect branch addresses in maximum mode, the top area starting at h'000 00000 is allocated to the exception vector table. one branch address is stor ed per 32 bits. the structure of the exception vector table is shown in figure 2.6. section 2 cpu rev. 2.00 oct. 20, 2009 page 34 of 1340 rej09b0499-0200 h'00000000 h'00000003 h'00000004 exception vector table reset exception vector h'00000007 h'00000001 h'00000002 h'00000005 h'00000006 figure 2.6 exception vector table (maximum modes) the memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the jmp and jsr instructions. an 8- bit absolute address included in the instruction code specifies a memory location. execution branches to the cont ents of the memory location. in maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. ? stack structure the stack structure of pc at a subroutine branch and that of pc and ccr at an exception handling are shown in figure 2.7. the pc contents are saved or restored in 32-bit units. the exr contents are saved or restored regardless of whether or not exr is in use. (a) subroutine branch (b) exception handling pc (32 bits) exr ccr pc (32 bits) sp sp figure 2.7 stack structure (maximum mode) section 2 cpu rev. 2.00 oct. 20, 2009 page 35 of 1340 rej09b0499-0200 2.3 instruction fetch the h8sx cpu has two modes for instruction fetch: 16-bit and 32-bit modes. it is recommended that the mode be set according to the bus width of the memory in which a program is stored. the instruction-fetch mode setting does not affect opera tion other than instruction fetch such as data accesses. whether an instruction is fetched in 16- or 32-bit mode is selected by the fetchmd bit in syscr. for details, see section 3.2.2, system control register (syscr). 2.4 address space figure 2.8 shows a memory map of the h8sx cpu. the address space differs depending on the cpu operating mode. h'0000 h'000000 h'007fff h'ff8000 h'ffffff h'00000000 h'00ffffff h'ffffffff h'00000000 h'ffffffff h'ffff normal mode program area data area (64 kbytes) program area data area (4 gbytes) program area (16 mbytes) program area (16 mbytes) data area (64 kbytes) data area (4 gbytes) middle mode advanced mode maximum mode figure 2.8 memory map section 2 cpu rev. 2.00 oct. 20, 2009 page 36 of 1340 rej09b0499-0200 2.5 registers the h8sx cpu has the internal registers shown in figure 2.9. there are two types of registers: general registers and control registers. the control registers are the 32-bit program counter (pc), 8-bit extended control register (exr), 8-bit co ndition-code register ( ccr), 32-bit vector base register (vbr), 32-bit short address base register (sbr), and 64-bit multiply-accumulate register (mac). t ???? i2 i1 i0 exr 76543210 31 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers and extended registers control registers [legend] stack pointer program counter condition-code register interrupt mask bit user bit or interrupt mask bit half-carry flag sp: pc: ccr: i: ui: h: user bit negative flag zero flag overflow flag carry flag extended control register u: n: z: v: c: exr: er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 7654321 0 sign extension 63 32 41 0 31 mac pc (reserved) 31 0 12 vbr (reserved) 31 0 8 sbr macl trace bit interrupt mask bits vector base register short address base register multiply-accumulate register t: i2 to i0: vbr: sbr: mac: mach figure 2.9 cpu registers section 2 cpu rev. 2.00 oct. 20, 2009 page 37 of 1340 rej09b0499-0200 2.5.1 general registers the h8sx cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. figu re 2.10 illustrates the usage of the general registers. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). when the general registers are used as 16-bit registers, the er registers are divided into 16-bit general registers designated by the letters e (e 0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. when the general registers are used as 8-bit registers, the r registers are divided into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. the general registers er (er0 to er7), r (r0 to r7 ), and rl (r0l to r7l) are also used as index registers. the size in the operand field determines which register is selected. the usage of each register can be selected independently. address registers 32-bit registers 32-bit index registers 16-bit registers general registers e (e0 to e7) 8-bit registers general registers rh (r0h to r7h) 16-bit registers 16-bit index registers general registers r (r0 to r7) 8-bit registers 8-bit index registers general registers rl (r0l to r7l) general registers er (er0 to er7) ? ? ? ? ? ? ? ? ? figure 2.10 usage of general registers section 2 cpu rev. 2.00 oct. 20, 2009 page 38 of 1340 rej09b0499-0200 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. figure 2.11 shows the stack. free area stack area sp (er7) figure 2.11 stack 2.5.2 program counter (pc) pc is a 32-bit counter that indicat es the address of the next instru ction the cpu will execute. the length of all cpu instructions is 16 bits (one word ) or a multiple of 16 bits, so the least significant bit is ignored. (when the instruction code is fetched, the least significant bit is regarded as 0. section 2 cpu rev. 2.00 oct. 20, 2009 page 39 of 1340 rej09b0499-0200 2.5.3 condition-code register (ccr) ccr is an 8-bit register that contains internal cp u status information, including an interrupt mask (i) and user (ui, u) bits and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branch conditio ns for conditional branch (bcc) instructions. bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts when set to 1. this bit is set to 1 at the start of an exception handling. 6 ui undefined r/w user bit/interrupt mask bit can be written to and read from by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is execut ed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written to and read from by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit (regarded as sign bit) of data. section 2 cpu rev. 2.00 oct. 20, 2009 page 40 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. a carry has the following types: ? carry from the result of addition ? borrow from the result of subtraction ? carry from the result of shift or rotation the carry flag is also used as a bit accumulator by bit manipulation instructions. 2.5.4 extended control register (exr) exr is an 8-bit register that contains the trace bit (t) and three interrupt mask bits (i2 to i0). operations can be performed on the exr bits by the ldc, stc, andc, orc, and xorc instructions. for details, see the corresponding section. bit bit name initial value r/w description 7 t 0 r/w trace bit when this bit is set to 1, a trace exception is generated each time an instruction is executed. when this bit is cleared to 0, instructions are executed in sequence. 6 to 3 ? all 1 r/w reserved these bits are always read as 1. 2 1 0 i2 i1 i0 1 1 1 r/w r/w r/w interrupt mask bits these bits designate the interrupt mask level (0 to 7). section 2 cpu rev. 2.00 oct. 20, 2009 page 41 of 1340 rej09b0499-0200 2.5.5 vector base register (vbr) vbr is a 32-bit register in which the upper 20 bits are valid. the lower 12 bi ts of this register are read as 0s. this register is a base address of the vector area for exceptio n handlings other than a reset and a cpu address error (extended memory indi rect is also out of th e target). the initial value is h'00000000. the vbr contents are changed with the ldc and stc instructions. 2.5.6 short address base register (sbr) sbr is a 32-bit register in which the upper 24 bits are valid. the lower eight bits are read as 0s. in 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. the initial value is h'ffffff00. the sbr contents are changed with the ldc and stc instructions. 2.5.7 multiply-accumulate register (mac) mac is a 64-bit register that stores the results of multiply-and-accumulate operations. it consists of two 32-bit registers denoted mach and macl. the lower 10 bits of mach are valid; the upper bits are sign extended. the mac contents are changed with the mac, clrmac, ldmac, and stmac instructions. 2.5.8 initial values of cpu registers reset exception handling loads the start address from the vector table into the pc, clears the t bit in exr to 0, and sets the i bits in ccr and exr to 1. the general registers, mac, and the other bits in ccr are not initialized. in particular, the initial value of the stack pointer (er7) is undefined. the sp should therefore be initialized using an mov.l instruction executed immediately after a reset. section 2 cpu rev. 2.00 oct. 20, 2009 page 42 of 1340 rej09b0499-0200 2.6 data formats the h8sx cpu can process 1-bit, 4-bit bcd, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions oper ate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.6.1 general register data formats figure 2.12 shows the data formats in general registers. section 2 cpu rev. 2.00 oct. 20, 2009 page 43 of 1340 rej09b0499-0200 7 6 5 4 3 2 1 0 don't care 7 0 don't care 7 6 5 4 3 2 1 0 43 70 70 don?t care upper lower lsb msb lsb 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data word data word data longword data rnh rnl rnh rnl rnh rnl rn en ern msb don't care upper lower 43 7 0 don't care 7 0 don't care 70 general register er general register e general register r general register rh [legend] ern: en: rn: rnh: 0 15 msb lsb 0 lsb 15 16 msb 31 en rn 0 msb lsb 15 rnl: msb: lsb: general register rl most significant bit least significant bit figure 2.12 general register data formats section 2 cpu rev. 2.00 oct. 20, 2009 page 44 of 1340 rej09b0499-0200 2.6.2 memory data formats figure 2.13 shows the data formats in memory. the h8sx cpu can access word data and longword data which are stored at any addresses in memory. when word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesse s. for example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. in this case, these accesses are assumed to be individual bus cycles. however, instructions to be fetc hed, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and mac instruction should be locat ed to even addresses. when sp (er7) is used as an address register to access the stack, the operand size should be word size or longword size. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2.13 memory data formats section 2 cpu rev. 2.00 oct. 20, 2009 page 45 of 1340 rej09b0499-0200 2.7 instruction set the h8sx cpu has 87 types of instructions. the instructions are classified by function as shown in table 2.1. the arithmetic operation, logic opera tion, shift, and bit manipulation instructions are called operation instruction in this manual. table 2.1 instruction classification function instructions size types mov b/w/l movfpe, movtpe b pop, push * 1 w/l ldm, stm l data transfer mova b/w * 2 6 eepmov b movmd b/w/l block transfer movsd b 3 add, addx, sub, subx, cmp, neg, inc, dec b/w/l daa, das b adds, subs l mulxu, divxu, mulxs, divxs b/w mulu, divu, muls, divs w/l mulu/u * 6 , muls/u * 6 l extu, exts w/l tas b mac * 6 ? ldmac * 6 , stmac * 6 ? arithmetic operations clrmac * 6 ? 27 logic operations and, or, xor, not b/w/l 4 shift shll, shlr, shal, shar, ro tl, rotr, rotxl, rotxr b/w/l 8 bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist b bset/eq, bset/ne, bclr/eq, bclr/ne, bstz, bistz b bit manipulation bfld, bfst b 20 section 2 cpu rev. 2.00 oct. 20, 2009 page 46 of 1340 rej09b0499-0200 function instructions size types bra/bs, bra/bc, bsr/bs, bsr/bc b * 3 bcc * 4 , jmp, bsr, jsr, rts ? rts/l l * 5 branch bra/s ? 9 trapa, rte, sleep, nop ? rte/l l * 5 system control ldc, stc, andc, orc, xorc b/w/l 10 total 87 [legend] b: byte size w: word size l: longword size notes: 1. pop.w rn and push.w rn are identical to mov.w @sp + , rn and mov.w rn, @ ? sp. pop.l ern and push.l ern are identical to mov.l @sp + , ern and mov.l ern, @ ? sp. 2. size of data to be added with a displacement 3. size of data to specify a branch condition 4. bcc is the generic designation of a conditional branch instruction. 5. size of general register to be restored 6. only when the multiplier is available. section 2 cpu rev. 2.00 oct. 20, 2009 page 47 of 1340 rej09b0499-0200 2.7.1 instructions and addressing modes table 2.2 indicates the combinations of instructions and addressing modes that the h8sx cpu can use. table 2.2 combinations of instru ctions and addressing modes (1) addressing mode classifi- cation instruction size #xx rn @ern @(d,ern) @(d, rnl.b/ rn.w/ ern.l) @ ? ern/ @ern ? / @ern ? / @ ? ern @aa:8 @aa:16/ @aa:32 ? b/w/l s sd sd sd sd sd sd mov b s/d s/d movfpe, movtpe b s/d s/d * 1 pop, push w/l s/d s/d * 2 ldm, stm l s/d s/d * 2 data transfer mova * 4 b/w s s s s s s eepmov b sd * 3 movmd b/w/l sd * 3 block transfer movsd b sd * 3 b s d d d d d d d b s d d d d d d b d s s s s s s b sd sd sd sd sd add, cmp w/l s sd sd sd sd sd sd b s d d d d d d b s d d d d d d b d s s s s s s b sd sd sd sd sd sub w/l s sd sd sd sd sd sd b/w/l s sd b/w/l s sd addx, subx b/w/l s sd * 5 inc, dec b/w/l d adds, subs l d arithmetic operations daa, das b d section 2 cpu rev. 2.00 oct. 20, 2009 page 48 of 1340 rej09b0499-0200 addressing mode classifi- cation instruction size #xx rn @ern @(d,ern) @(d, rnl.b/ rn.w/ ern.l) @ ? ern/ @ern ? / @ern ? / @ ? ern @aa:8 @aa:16/ @aa:32 ? mulxu, divxu b/w s:4 sd mulu, divu w/l s:4 sd mulxs, divxs b/w s:4 sd muls, divs w/l s:4 sd b d d d d d d d neg w/l d d d d d d extu, exts w/l d d d d d d tas b d mac * 12 ? clrmac * 12 ? o ldmac * 12 ? s arithmetic operations stmac * 12 ? d b s d d d d d d b d s s s s s s b sd sd sd sd sd and, or, xor w/l s sd sd sd sd sd sd b d d d d d d d logic operations not w/l d d d d d d b d d d d d d d w/l * 6 d d d d d d shll, shlr b/w/l * 7 d b d d d d d d d shift shal, shar rotl, rotr rotxl, rotxr w/l d d d d d d bset, bclr, bnot, btst, bset/cc, bclr/cc b d d d d bit manipu- lation band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist, bstz, bistz b d d d d section 2 cpu rev. 2.00 oct. 20, 2009 page 49 of 1340 rej09b0499-0200 addressing mode classifi- cation instruction size #xx rn @ern @(d,ern) @(d, rnl.b/ rn.w/ ern.l) @ ? ern/ @ern ? / @ern ? / @ ? ern @aa:8 @aa:16/ @aa:32 ? bfld b d s s s bit manipu- lation bfst b s d d d bra/bs, bra/bc * 8 b s s s branch bsr/bs, bsr/bc * 8 b s s s ldc (ccr, exr) b/w * 9 s s s s s * 10 s ldc (vbr, sbr) l s stc (ccr, exr) b/w * 9 d d d d * 11 d stc (vbr, sbr) l d andc, orc, xorc b s sleep ? o system control nop ? o [legend] d: d:16 or d:32 s: can be specified as a source operand. d: can be specified as a destination operand. sd: can be specified as either a s ource or destination operand or both. s/d: can be specified as either a source or destination operand. s:4: 4-bit immediate data can be specified as a source operand. notes: 1. only @aa:16 is available. 2. @ern + as a source operand and @ ? ern as a destination operand 3. specified by er5 as a source addre ss and er6 as a destination address for data transfer. 4. size of data to be added with a displacement 5. only @ern ? is available 6. when the number of bits to be shifted is 1, 2, 4, 8, or 16 7. when the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. size of data to specify a branch condition 9. byte when immediate or r egister direct, otherwise, word 10. only @ern + is available 11. only @ ? ern is available 12. only when the multiplier is available. section 2 cpu rev. 2.00 oct. 20, 2009 page 50 of 1340 rej09b0499-0200 table 2.2 combinations of instru ctions and addressing modes (2) addressing mode classifi- cation instruction size @ern @(d,pc) @(rnl.b /rn.w/ ern.l, pc) @aa:24 @aa:32 @@aa:8 @@vec:7 ? bra/bs, bra/bc ? o bsr/bs, bsr/bc ? o bcc ? o bra ? o o bra/s ? o * jmp ? o o o o o bsr ? o jsr ? o o o o o branch rts, rts/l ? o trapa ? o system control rte, rte/l ? o [legend] d: d:8 or d:16 note: * only @(d:8, pc) is available. section 2 cpu rev. 2.00 oct. 20, 2009 page 51 of 1340 rej09b0499-0200 2.7.2 table of instructions classified by function tables 2.4 to 2.11 summarize the instructions in each functional category. the notation used in these tables is defined in table 2.3. table 2.3 operation notation operation notation description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register vbr vector base register sbr short address base register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical exclusive or move logical not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). section 2 cpu rev. 2.00 oct. 20, 2009 page 52 of 1340 rej09b0499-0200 table 2.4 data transfer instructions instruction size function mov b/w/l #imm (ead), (eas) (ead) transfers data between immediate data , general registers, and memory. movfpe b (eas) rd movtpe b rs (eas) pop w/l @sp + rn restores the data from the stack to a general register. push w/l rn @ ? sp saves general register contents on the stack. ldm l @sp + rn (register list) restores the data from the stack to mu ltiple general registers. two, three, or four general registers which have serial register numbers can be specified. stm l rn (register list) @ ? sp saves the contents of multiple general registers on the stack. two, three, or four general registers which have serial register numbers can be specified. mova b/w ea rd zero-extends and shifts the contents of a specified general register or memory data and adds them with a disp lacement. the result is stored in a general register. section 2 cpu rev. 2.00 oct. 20, 2009 page 53 of 1340 rej09b0499-0200 table 2.5 block transfer instructions instruction size function eepmov.b eepmov.w b transfers a data block. transfers byte data which begins at a memory location specified by er5 to a memory location specified by er6. the number of byte data to be transferred is specified by r4 or r4l. movmd.b b transfers a data block. transfers byte data which begins at a memory location specified by er5 to a memory location specified by er6. the number of byte data to be transferred is specified by r4. movmd.w w transfers a data block. transfers word data which begins at a memory location specified by er5 to a memory location specified by er6. the number of word data to be transferred is specified by r4. movmd.l l transfers a data block. transfers longword data which begins at a memory location specified by er5 to a memory location specified by er6. the number of longword data to be transferred is specified by r4. movsd.b b transfers a data block with zero data detection. transfers byte data which begins at a memory location specified by er5 to a memory location specified by er6. the number of byte data to be transferred is specified by r4. when ze ro data is detected during transfer, the transfer stops and execution bran ches to a specified address. section 2 cpu rev. 2.00 oct. 20, 2009 page 54 of 1340 rej09b0499-0200 table 2.6 arithmetic operation instructions instruction size function add sub b/w/l (ead) #imm (ead), (ead) (eas) (ead) performs addition or subtracti on on data between immediate data, general registers, and memory. immediate byte data cannot be subtracted from byte data in a general register. addx subx b/w/l (ead) #imm c (ead), (ead) (eas) c (ead) performs addition or subtraction wit h carry on data between immediate data, general registers, and me mory. the addressing mode which specifies a memory location can be sp ecified as register indirect with post-decrement or register indirect. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general re gister by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a general register. daa das b rd (decimal adjust) rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 2-digit 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits, or 16 bits 16 bits 32 bits. mulu w/l rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits, or 16 bits 16 bits 32 bits. mulu/u ? l rd rs rd performs unsigned multiplication on data in two general registers (32 bits 32 bits upper 32 bits). mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits, or 16 bits 16 bits 32 bits. muls w/l rd rs rd performs signed multiplication on data in two general registers: either 16 bits 16 bits 16 bits, or 32 bits 32 bits 32 bits. muls/u ? l rd rs rd performs signed multiplication on data in two general registers (32 bits 32 bits upper 32 bits). divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder, or 32 bits 16 bits 16-bit quotient and 16-bit remainder. section 2 cpu rev. 2.00 oct. 20, 2009 page 55 of 1340 rej09b0499-0200 instruction size function divu w/l rd rs rd performs unsigned division on data in two general registers: either 16 bits 16 bits 16-bit quotient, or 32 bits 32 bits 32-bit quotient. divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder, or 32 bits 16 bits 16-bit quotient and 16-bit remainder. divs w/l rd rs rd performs signed division on data in two general registers: either 16 bits 16 bits 16-bit quotient, or 32 bits 32 bits 32-bit quotient. cmp b/w/l (ead) ? #imm, (ead) ? (eas) compares data between immediate data, general registers, and memory and stores the result in ccr. neg b/w/l 0 ? (ead) (ead) takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. extu w/l (ead) (zero extension) (ead) performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. the lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. exts w/l (ead) (sign extension) (ead) performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. the lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. tas b @erd ? 0, 1 ( section 2 cpu rev. 2.00 oct. 20, 2009 page 56 of 1340 rej09b0499-0200 table 2.7 logic operation instructions instruction size function and b/w/l (ead) #imm (ead), (ead) (eas) (ead) performs a logical and operati on on data between immediate data, general registers, and memory. or b/w/l (ead) #imm (ead), (ead) (eas) (ead) performs a logical or operation on data between immediate data, general registers, and memory. xor b/w/l (ead) #imm (ead), (ead) (eas) (ead) performs a logical exclusive or operation on data between immediate data, general registers, and memory. not b/w/l (ead) (ead) takes the one's complement of the c ontents of a general register or a memory location. table 2.8 shift operation instructions instruction size function shll shlr b/w/l (ead) (shift) (ead) performs a logical shift on the contents of a general register or a memory location. the contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. the contents of a general register can be shifted by any bits. in this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register. shal shar b/w/l (ead) (shift) (ead) performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible. rotl rotr b/w/l (ead) (rotate) (ead) rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible. rotxl rotxr b/w/l (ead) (rotate) (ead) rotates the contents of a general regi ster or a memory location with the carry bit. 1-bit or 2-bit rotation is possible. section 2 cpu rev. 2.00 oct. 20, 2009 page 57 of 1340 rej09b0499-0200 table 2.9 bit manipulation instructions instruction size function bset b 1 ( section 2 cpu rev. 2.00 oct. 20, 2009 page 58 of 1340 rej09b0499-0200 instruction size function bior b c [~ ( section 2 cpu rev. 2.00 oct. 20, 2009 page 59 of 1340 rej09b0499-0200 instruction size function bistz b z ( section 2 cpu rev. 2.00 oct. 20, 2009 page 60 of 1340 rej09b0499-0200 table 2.11 system control instructions instruction size function trapa ? starts trap-instruct ion excepti on handling. rte ? returns from an exception-handling routine. rte/l ? returns from an exception-handli ng routine, restoring data from the stack to multiple general registers. sleep ? causes a transition to a power-down state. b/w #imm ccr, (eas) ccr, #imm exr, (eas) exr loads immediate data or the contents of a general register or a memory location to ccr or exr. although ccr and exr are 8-bit regi sters, word-size transfers are performed between them and memory. the upper 8 bits are valid. ldc l rs vbr, rs sbr transfers the general register contents to vbr or sbr. b/w ccr (ead), exr (ead) transfers the contents of ccr or exr to a general register or memory. although ccr and exr are 8-bit regi sters, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc l vbr rd, sbr rd transfers the contents of vbr or sbr to a general register. andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data. xorc b ccr #imm ccr, exr #imm exr logically exclusive-ors the ccr or exr contents with immediate data. nop ? pc + 2 pc only increments the program counter. section 2 cpu rev. 2.00 oct. 20, 2009 page 61 of 1340 rej09b0499-0200 2.7.3 basic instruction formats the h8sx cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effect ive address extension (ea field), and a condition field (cc). figure 2.14 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc figure 2.14 instruction formats ? operation field indicates the function of the instruction, and speci fies the addressing mode and operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. ? register field specifies a general register. address registers are sp ecified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. ? effective address extension 8, 16, or 32 bits specifying immediate data , an absolute address, or a displacement. ? condition field specifies the branch condition of bcc instructions. section 2 cpu rev. 2.00 oct. 20, 2009 page 62 of 1340 rej09b0499-0200 2.8 addressing modes and effective address calculation the h8sx cpu supports the 11 addressing modes listed in table 2.12. each instruction uses a subset of these addressing modes. bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.12 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:2,ern)/@(d:16,ern)/@(d:32,ern) 4 index register indirect with displacement @(d:16, rnl.b)/@(d: 16,rn.w)/@(d:16,ern.l) @(d:32, rnl.b)/@(d:32, rn.w)/@(d:32,ern.l) 5 register indirect with post-increment @ern+ register indirect with pre-decrement @?ern register indirect with pre-increment @+ern register indirect with post-decrement @ern? 6 absolute address @aa:8/@aa:16/@aa:24/@aa:32 7 immediate #xx:3/#xx: 4/#xx:8/#xx:16/#xx:32 8 program-counter relati ve @(d:8,pc)/@(d:16,pc) 9 program-counter relative with index regi ster @(rnl.b,pc)/@(rn.w,pc)/@(ern.l,pc) 10 memory indirect @@aa:8 11 extended memory indirect @@vec:7 2.8.1 register direct?rn the operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in th e instruction code. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. section 2 cpu rev. 2.00 oct. 20, 2009 page 63 of 1340 rej09b0499-0200 2.8.2 register indirect?@ern the operand value is the co ntents of the memory location which is pointed to by the contents of an address register (ern). ern is specified by the register field of the instruction code. in advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). 2.8.3 register indirect with displacemen t ?@(d:2, ern), @(d:16, ern), or @(d:32, ern) the operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ern) and a 16- or 32-bit displacement. ern is specified by the register field of the instruction code. the displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ern. this addressing mode has a short format (@(d:2, ern)). the short format can be used when the displacement is 1, 2, or 3 and the operand is byte da ta, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data. 2.8.4 index register indirect with displacem ent?@(d:16,rnl.b), @(d:32,rnl.b), @(d:16,rn.w), @(d:32,rn.w), @(d:16,ern.l), or @(d:32,ern.l) the operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (rnl, rn, ern) specified by the register field in the in struction code are zero- extended to 32-bit data an d multiplied by 1, 2, or 4. the displacement is in cluded in the instruction code and the 16-bit displacement is sign-extended wh en added to ern. if the operand is byte data, ern is multiplied by 1. if the operand is word or longword data, ern is multiplied by 2 or 4, respectively. section 2 cpu rev. 2.00 oct. 20, 2009 page 64 of 1340 rej09b0499-0200 2.8.5 register indirect with post-increm ent, pre-decrement, pre-increment, or post-decrement?@ern + , @ ? ern, @ + ern, or @ern ? ? register indirect with post-increment?@ern + the operand value is the contents of a memory location which is pointed to by the contents of an address register (ern). ern is specified by the register field of th e instruction code. after the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address regi ster. the value added is 1 for by te access, 2 for word access, or 4 for longword access. ? register indirect with pre-decrement?@ ? ern the operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ern). ern is specified by the register field of the instructio n code. after that, the operand value is stored in the address register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. ? register indirect with pre-increment?@ + ern the operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ern). ern is specified by the register fiel d of the instruction code. after that, the operand value is stored in the address register. the value added is 1 for byte access, 2 for wo rd access, or 4 for longword access. ? register indirect with post-decrement?@ern ? the operand value is the contents of a memory location which is pointed to by the contents of an address register (ern). ern is specified by the register field of th e instruction code. after the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register . the value subtracted is 1 for byte access, 2 for word access, or 4 fo r longword access. using this addressing mode, data to be written is the contents of the general register after calculating an effective address. if the same general register is specified in an instruction and two effective addresses are calculated, the contents of the general register after the first calculation of an effective address is used in the seco nd calculation of an effective address. example 1: mov.w r0, @er0 + when er0 before execution is h'12345678, h'567a is written at h'12345678. section 2 cpu rev. 2.00 oct. 20, 2009 page 65 of 1340 rej09b0499-0200 example 2: mov.b @er0 + , @er0 + when er0 before execution is h'00001000, h'000010 00 is read and the contents is written at h'00001001. after execution, er0 is h'00001002. 2.8.6 absolute address?@aa:8, @aa:16, @aa:24, or @aa:32 the operand value is the co ntents of a memory location which is pointed to by an absolute address included in the instruction code. there are 8-bit (@aa:8), 16-bit (@aa:16), 24-b it (@aa:24), and 32-bit (@aa:32) absolute addresses. to access the data area, the absolu te address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. for an 8-bit absolute address, the upper 24 bits are specified by sbr. for a 16- bit absolute address, the upper 16 bits are sign -extended. a 32-bit abso lute address can access the entire address space. to access the program area, the abso lute address of 24 bits (@aa:24 ) or 32 bits (@aa:32) is used. for a 24-bit absolute addres s, the upper 8 bits are a ll assumed to be 0 (h'00). table 2.13 shows the accessibl e absolute address ranges. table 2.13 absolute address access ranges absolute address normal mode middle mode advanced mode maximum mode 8 bits (@aa:8) a consecutive 256-byte area (the upper address is set in sbr) 16 bits (@aa:16) h'00000000 to h'00007fff, h'ffff8000 to h'ffffffff data area 32 bits (@aa:32) h'000000 to h'007fff, h'ff8000 to h'ffffff h'00000000 to h'ffffffff 24 bits (@aa:24) h'00000000 to h'00ffffff program area 32 bits (@aa:32) h'0000 to h'ffff h'000000 to h'ffffff h'00000000 to h'00ffffff h'00000000 to h'ffffffff section 2 cpu rev. 2.00 oct. 20, 2009 page 66 of 1340 rej09b0499-0200 2.8.7 immediate?#xx the operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. this addressing mode has short formats in which 3- or 4-bit immediate data can be used. when the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. the bfld and bfst instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. the tr apa instruction contains 2-bit i mmediate data in the instruction code, for specifying a vector address. 2.8.8 program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bcc and bsr instructi ons. the operand value is a 32-bit branch address, which is the sum of an 8- or 16 -bit displacement in the instruction code and th e 32-bit address of the pc contents. the 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the pc contents. the pc contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ? 126 to + 128 bytes ( ? 63 to + 64 words) or ? 32766 to + 32768 bytes ( ? 16383 to + 16384 words) from the branch instruction. the resulting value should be an even number. in advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). 2.8.9 program-counter relative with index register?@(rnl.b, pc), @(rn.w, pc), or @(ern.l, pc) this mode is used in the bcc and bsr instructi ons. the operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the pc contents: the contents of an address register specified by the register field in the instruction code (rnl, rn, or ern) is zero-extended and multiplie d by 2. the pc contents to wh ich the displacement is added is the address of the first byte of the next instruction. in advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). section 2 cpu rev. 2.00 oct. 20, 2009 page 67 of 1340 rej09b0499-0200 2.8.10 memory indirect?@@aa:8 this mode can be used by the jmp and jsr instru ctions. the operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code. the upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h'0000ff in other modes). in normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. in other modes, the memory location is pointed to by longword-size data. in middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (h'00). note that the top part of the address range is al so used as the exceptio n handling vector area. a vector address of an exception handling other than a reset or a cpu address error can be changed by vbr. figure 2.15 shows an example of specification of a branch address using this addressing mode. (a) normal mode (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address figure 2.15 branch address speci fication in memory indirect mode section 2 cpu rev. 2.00 oct. 20, 2009 page 68 of 1340 rej09b0499-0200 2.8.11 extended memory indirect?@@vec:7 this mode can be used by the jmp and jsr instru ctions. the operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of h'80 is multiplied by 2 or 4. the address range to store a branch address is h'0100 to h'01ff in normal mode and h'000200 to h'0003ff in other modes. in assembler notation, an address to store a branch address is specified. in normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. in other modes, the memory location is pointed to by longword-size data. in middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (h'00). 2.8.12 effective address calculation tables 2.14 and 2.15 show how effective addres ses are calculated in each addressing mode. the lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign extended) according to the cpu operating mode. the valid bits in middle mode are as follows: ? the lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions. ? the lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions. section 2 cpu rev. 2.00 oct. 20, 2009 page 69 of 1340 rej09b0499-0200 table 2.14 effective address calculation for transfer and operation instructions 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 15 31 15 0 31 0 31 0 0 31 15 0 31 0 1, 2, or 4 31 31 0 0 31 0 31 1, 2, or 4 1, 2, or 4 31 0 7 no. op op rm rn imm 1 2 3 4 5 6 7 op r op disp disp disp disp aa aa aa disp r op disp r op aa op disp r op disp r op aa op r op r op aa 31 0 0 1, 2, or 4 addressing mode and instruction format effective address calculation effective address (ea) immediate register direct register indirect register indirect with 16-bit displacement register indirect with 32-bit displacement index register indirect with 16-bit displacement index register indirect with 32-bit displacement register indirect with post-increment or post-decrement register indirect with pre-increment or pre-decrement 8-bit absolute address 16-bit absolute address 32-bit absolute address sign extension sbr general register contents general register contents zero extension contents of general register (rl, r, or er) zero extension contents of general register (rl, r, or er) sign extension general register contents general register contents general register contents sign extension + + + + section 2 cpu rev. 2.00 oct. 20, 2009 page 70 of 1340 rej09b0499-0200 table 2.15 effective address calc ulation for branch instructions 31 0 31 0 31 0 31 0 31 31 23 0 0 31 31 0 0 31 0 2 or 4 7 1 7 vec op disp 1 2 3 4 5 6 op disp op r op aa op r op aa aa aa op aa aa 31 0 31 0 op vec 31 0 31 0 31 0 31 0 31 7 0 disp 31 0 31 0 31 15 0 disp 31 0 31 31 0 2 0 no. register indirect program-counter relative with 8-bit displacement 24-bit absolute address 32-bit absolute address zero extension contents of general register (rl, r, or er) general register contents sign extension addressing mode and instruction format effective address calculation effective address (ea) pc contents sign extension pc contents zero extension zero extension memory contents memory contents zero extension pc contents program-counter relative with 16-bit displacement program-counter relative with index register memory indirect extended memory indirect + + + 2.8.13 mova instruction the mova instruction stores the eff ective address in a general register. 1. firstly, data is obtained by the addressing mode shown in item 2 of table 2.14. 2. next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. the obtained data is used instead of the general register. the result is stored in a general register. for details, see h8sx family software manual. section 2 cpu rev. 2.00 oct. 20, 2009 page 71 of 1340 rej09b0499-0200 2.9 processing states the h8sx cpu has five main processing states: the reset state, exception- handling state, program execution state, bus-released stat e, and program stop state. fi gure 2.16 indicates the state transitions. ? reset state in this state the cpu and internal peripheral mo dules are all initialized and stopped. when the res input goes low, all current processing stops and the cpu enters the reset state. all interrupts are masked in the reset state. reset exception handlin g starts when the res signal changes from low to high. for details, see section 6, exception handling. the reset state can also be entered by a watchdog timer overfl ow when available. ? exception-handling state the exception-handling state is a transient state that occurs wh en the cpu alters the normal processing flow due to activati on of an exception sour ce, such as, a reset, trace, interrupt, or trap instruction. the cpu fetches a start addre ss (vector) from the exception handling vector table and branches to that address. for further details, see section 6, exception handling. ? program execution state in this state the cpu executes pr ogram instructions in sequence. ? bus-released state the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. ? program stop state this is a power-down state in which the cpu stops operating. the program stop state occurs when a sleep instruction is executed or the cpu enters hardware standby mode. for details, see section 27, power-down modes. section 2 cpu rev. 2.00 oct. 20, 2009 page 72 of 1340 rej09b0499-0200 note: a transition to hardware standby mode occurs whenever the stby signal goes low. * a transition to the reset state occurs when the res signal goes low in all states except hardware standby mode. a transition can also be made to the reset state when the watchdog timer overflows. reset state * exception-handling state request for exception handling end of exception handling program execution state bus-released state bus request end of bus request program stop state sleep instruction interrupt request bus request end of bus request res = high res = low stby = high, figure 2.16 state transitions section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 73 of 1340 rej09b0499-0200 section 3 mcu operating modes 3.1 operating mode selection this lsi has seven operating modes (modes 1, 2, 3, 4, 5, 6, and 7). the operating mode is selected by the setting of mode pins md2 to md0. table 3.1 lists mcu operating mode settings. table 3.1 mcu operating mode settings external data bus width mcu operating mode md2 md1 md0 cpu operating mode address space lsi initiation mode on-chip rom default max. 1 0 0 1 advanced mode 16 mbytes user boot mode enabled ? 16 bits 2 0 1 0 boot mode enabled ? 16 bits 3 0 1 1 boundary scan enabled single-chip mode enabled ? 16 bits 4 1 0 0 disabled 16 bits 16 bits 5 1 0 1 on-chip rom disabled extended mode disabled 8 bits 16 bits 6 1 1 0 on-chip rom enabled extended mode enabled 8 bits 16 bits 7 1 1 1 single-chip mode enabled ? 16 bits in this lsi, an advanced mode as the cpu op erating mode and a 16-mbyte address space are available. the initial external bus widths are 8 bits or 16 bits. as the lsi initiation mode, the external extended mode, on-chip rom initiation mode, or single-chip initiation mode can be selected. modes 1 and 2 are the user boot mode and the boot mode, respectively, in which the flash memory can be programmed and erased. for details on the user boot mode and boot mode, see section 24, flash memory. section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 74 of 1340 rej09b0499-0200 mode 3 is the boundary scan function enabled single-chip mode. for details on the boundary scan function, see section 25, boundary scan. mode 7 is a single-chip initiation mode. all i/o po rts can be used as general input/output ports. the external address space cannot be accessed in th e initial state, but setti ng the expe bit in the system control register (syscr) to 1 enables to use the external address space. after the external address space is enabled, ports h and i can be us ed as a data bus and po rts d, e, and f as an address output bus by specifying the data dir ection register (ddr) fo r each port. when the external address space is not in use, ports j and k can be used by setting the pcjke bit in the port function control register d (pfcrd) to 1. modes 4 to 6 are external extended modes, in which the external memory and devices can be accessed. in the external extended modes, the exte rnal address space can be designated as 8-bit or 16-bit address space for each ar ea by the bus controller after starting program execution. if 16-bit address space is designated for any one area, it is called the 16-bit bus widths mode. if 8- bit address space is designated for all areas, it is called the 8-bit bus width mode. section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 75 of 1340 rej09b0499-0200 3.2 register descriptions the following registers are related to the operating mode setting. ? mode control register (mdcr) ? system control register (syscr) 3.2.1 mode control register (mdcr) mdcr indicates the current opera ting mode. when mdcr is read from, the states of signals md3 to md0 are latched. latching is released by a reset. bit bit name initial value r/w note: * determined by pins md2 to md0. 15 ? 0 r 14 ? 1 r 13 ? 0 r 12 ? 1 r 11 mds3 undefined * r 10 mds2 undefined * r 9 mds1 undefined * r 8 mds0 undefined * r bit bit name initial value r/w 7 ? 0 r 6 ? 1 r 5 ? 0 r 4 ? 1 r 3 ? undefined * r 2 ? undefined * r 1 ? undefined * r 0 ? undefined * r bit bit name initial value r/w descriptions 15 14 13 12 ? ? ? ? 0 1 0 1 r r r r reserved these are read-only bits and cannot be modified. 11 10 9 8 mds3 mds2 mds1 mds0 undefined * undefined * undefined * undefined * r r r r mode select 3 to 0 these bits indicate the operating mode selected by the mode pins (md2 to md0) (see table 3.2). when mdcr is read, the signal levels input on pins md2 to md0 are latched into these bits. these latches are released by a reset. section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 76 of 1340 rej09b0499-0200 bit bit name initial value r/w descriptions 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? 0 1 0 1 undefined * undefined * undefined * undefined * r r r r r r r r reserved these are read-only bits and cannot be modified. note: * determined by pins md2 to md0. table 3.2 settings of bits mds3 to mds0 mode pins mdcr mcu operating mode md2 md1 md0 mds3 mds2 mds1 mds0 1 0 0 1 1 1 0 1 2 0 1 0 1 1 0 0 3 0 1 1 0 1 0 0 4 1 0 0 0 0 1 0 5 1 0 1 0 0 0 1 6 1 1 0 0 1 0 1 7 1 1 1 0 1 0 0 section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 77 of 1340 rej09b0499-0200 3.2.2 system control register (syscr) syscr controls mac saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-ch ip ram, and selects the dtc address mode. bit bit name initial value r/w note: * the initial value depends on the startup mode. 15 ? 1 r/w 14 ? 1 r/w 13 macs 0 r/w 12 ? 1 r/w 11 fetchmd 0 r/w 10 ? undefined * r 9 expe undefined * r/w 8 rame 1 r/w bit bit name initial value r/w 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 dtcmd 1 r/w 0 ? 1 r/w bit bit name initial value r/w descriptions 15 14 1 1 r/w r/w reserved these bits are always read as 1. the write value should always be 1. 13 macs 0 r/w mac saturation operation control selects either saturation operation or non-saturation operation for the mac instruction. 0: mac instruction is non-saturation operation 1: mac instruction is saturation operation 12 1 r/w reserved this bit is always read as 1. the write value should always be 1. 11 fetchmd 0 r/w instruction fetch mode select this lsi can prefetch an instruction in units of 16 bits or 32 bits. select the bus width for instruction fetch depending on the used memory for the storage of programs. 0: 32-bit mode 1: 16-bit mode section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 78 of 1340 rej09b0499-0200 bit bit name initial value r/w descriptions 10 ? undefined * 1 r reserved this bit is fixed at 1 in on-chip rom enabled mode, and 0 in on-chip rom disabled mode. this bit cannot be changed. 9 expe undefined * 1 r/w external bus mode enable selects external bus mode. in external extended mode, this bit is fixed 1 and cannot be changed. in single-chip mode, the initial value of th is bit is 0, and can be read from or written to when pckje = 0. do not write to this bit when pckje = 1 * 2 . when writing 0 to this bit after reading expe = 1, an external bus cycle should not be executed. the external bus cycle may be carried out in parallel with the internal bus cycle depending on the setting of the write data buffer f unction and the state the exdmac releases the bus mastership. 0: external bus disabled 1: external bus enabled 8 rame 1 r/w ram enable enables or disables the on-chip ram. this bit is initialized when the reset stat e is released. do not write 0 during access to the on-chip ram. 0: on-chip ram disabled 1: on-chip ram enabled 7 to 2 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 1 dtcmd 1 r/w dtc mode select selects dtc operating mode. 0: dtc is in full-address mode 1: dtc is in short address mode 0 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. notes: 1. the initial value dep ends on the lsi initiation mode. 2. for details on the settings of the expe and pcjke bits when the external address space is in use, see section 13.3.12, port function control register d (pfcrd). section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 79 of 1340 rej09b0499-0200 3.3 operating mode descriptions 3.3.1 mode 1 this is the user boot mode for the flash memory. the lsi operates in the same way as in mode 7 except for programming and erasing of the flas h memory. for details, see section 24, flash memory. 3.3.2 mode 2 this is the boot mode for the flash memory. th e lsi operates in the same way as in mode 7 except for programming and erasing of the flas h memory. for details, see section 24, flash memory. 3.3.3 mode 3 this is the boundary scan function enabled single-chip activation mode. the operation is the same as mode 7 except for the boundary scan function. for details on the boundary scan function, see section 25, boundary scan. 3.3.4 mode 4 the cpu operating mode is adva nced mode in which the addres s space is 16 mbytes, and the on- chip rom is disabled. the initial bus width mode immediately after a rese t is 16 bits, with 16-bit access to all areas. ports d, e, and f function as an address bus, ports h and i function as a data bus, and parts of ports a and b function as bus control signals. however, if all areas are designated as an 8-bit access space by the bus contro ller, the bus mode switches to 8 b its, and only port h functions as a data bus. section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 80 of 1340 rej09b0499-0200 3.3.5 mode 5 the cpu operating mode is adva nced mode in which the addres s space is 16 mbytes, and the on- chip rom is disabled. the initial bus width mode immediately after a rese t is eight bits, with 8-bit access to all areas. ports d, e, and f function as an address bus, port h functions as a data bus, and parts of ports a and b function as bus control signals. however, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports h and i function as a data bus. 3.3.6 mode 6 the cpu operating mode is adva nced mode in which the addres s space is 16 mbytes, and the on- chip rom is enabled. the initial bus width mode immediately after a rese t is eight bits, with 8-bit access to all areas. ports d, e, and f function as input ports, but they can be used as an address bus by specifying the data direction register (ddr) for each port. for de tails, see section 13, i/o ports. port h functions as a data bus, and parts of ports a and b function as bus control signals. however, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports h and i function as a data bus. 3.3.7 mode 7 the cpu operating mode is adva nced mode in which the addres s space is 16 mbytes, and the on- chip rom is enabled. all i/o ports can be used as general input/output ports. the external address space cannot be accessed in the initial state, but se tting the expe bit in the system control register (syscr) to 1 enables the external addr ess space. after the external address space is en abled, ports h and i can be used as a data bus and ports d, e, and f as an address output bus by specifying the data direction register (ddr) for each port. when the external address space is not in use, ports j and k can be used by setting the pcjke bit in the port function control register d (pfcrd) to 1. for details, see section 13, i/o ports. section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 81 of 1340 rej09b0499-0200 3.3.8 pin functions table 3.3 lists the pin functions in each operating mode. table 3.3 pin functions in each operating mode (advanced mode) port a port b port f mcu operating mode pa7 pa6 to pa3 pa2 to pa0 pb3 to pb1 pb0 port d port e pf4 to pf0 port h port i 1 p * /c p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /d p * /d 2 p * /c p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /d p * /d 3 p * /c p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /d p * /d 4 p/c * p/c * p * /c p * /c p/c * a a a d p/d * 5 p/c * p/c * p * /c p * /c p/c * a a a d p * /d 6 p/c * p/c * p * /c p * /c p * /c p * /a p * /a p * /a d p * /d 7 p * /c p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /d p * /d [legend] p: i/o port a: address bus output d: data bus input/output c: control signals, clock input/output * : immediately after a reset 3.4 address map 3.4.1 address map figures 3.1 and 3.2 sh ow the address map in each operating mode. section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 82 of 1340 rej09b0499-0200 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 reserved area * 3 on-chip rom on-chip ram * 2 on-chip i/o registers on-chip i/o registers h'000000 h'080000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff reserved area * 3 h'fec000 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 reserved area * 3 access prohibited area access prohibited area on-chip rom on-chip i/o registers on-chip i/o registers h'100000 h'000000 h'080000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff h'fec000 h'100000 external address space external address space external address space external address space reserved area * 3 reserved area c reserved area * 3 on-chip ram/ external address space * 4 on-chip ram/ external address space * 4 on-chip i/o registers on-chip i/o registers h'000000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'fec000 h'ffea00 h'ffff00 h'ffff20 h'ffffff this area is specified as the external address space when expe = 1 and the reserved area when expe = 0. the on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. do not access the reserved areas. this area is specified as the external address space by clearing the rame bit in syscr to 0. 1. 2. 3. 4. notes: modes 1 and 2 user boot mode, boot mode (advanced mode) modes 3 and 7 boundary scan enabled single-chip mode, single-chip mode (advanced mode) modes 4 and 5 on-chip rom disabled extended mode (advanced mode) figure 3.1 address map in each operating mode of h8sx/1655 and h8sx/1655m (1) section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 83 of 1340 rej09b0499-0200 mode 6 on-chip rom enabled extended mode (advanced mode) external address space external address space external address space external address space access prohibited area on-chip rom on-chip ram/ external address space * 2 on-chip i/o registers on-chip i/o registers h'000000 h'080000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff reserved area * 1 h'fec000 access prohibited area h'100000 1. do not access the reserved area. 2. this area is specified as the external address space by clearing the rame bit in syscr to 0. notes: figure 3.1 address map in each operating mode of h8sx/1655 and h8sx/1655m (2) section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 84 of 1340 rej09b0499-0200 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 access prohibited area on-chip rom on-chip ram * 2 on-chip i/o registers on-chip i/o registers h'000000 h'060000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff reserved area * 3 h'fec000 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 access prohibited area access prohibited area access prohibited area on-chip rom on-chip i/o registers on-chip i/o registers h'100000 h'000000 h'060000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff h'fec000 h'100000 external address space external address space external address space external address space access prohibited area reserved area * 3 reserved area * 3 on-chip ram/ external address space * 4 on-chip ram/ external address space * 4 on-chip i/o registers on-chip i/o registers h'000000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'fec000 h'ffea00 h'ffff00 h'ffff20 h'ffffff 3. do not access the reserved areas. 4. this area is specified as the external address space by clearing the rame bit in syscr to 0. 1. this area is specified as the external address space when expe = 1 and the reserved area when expe = 0. 2. the on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. notes: modes 1 and 2 user boot mode, boot mode (advanced mode) modes 3 and 7 boundary scan enabled single-chip mode, single-chip mode (advanced mode) modes 4 and 5 on-chip rom disabled extended mode (advanced mode) figure 3.2 address map in each operating mode of h8sx/1652 and h8sx/1652m (1) section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 85 of 1340 rej09b0499-0200 mode 6 on-chip rom enabled extended mode (advanced mode) external address space external address space reserved area * 1 external address space access prohibited area on-chip rom on-chip ram/ external address space * 2 on-chip i/o registers on-chip i/o registers h'000000 h'060000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff access prohibited area h'fec000 access prohibited area h'100000 1. do not access the reserved area. 2. this area is specified as the external address space by clearing the rame bit in syscr to 0. notes: figure 3.2 address map in each operating mode of h8sx/1652 and h8sx/1652m (2) section 3 mcu operating modes rev. 2.00 oct. 20, 2009 page 86 of 1340 rej09b0499-0200 section 4 reset rev. 2.00 oct. 20, 2009 page 87 of 1340 rej09b0499-0200 section 4 reset 4.1 types of reset there are three types of reset: a pin reset, power-on reset*, voltage-monitoring reset*, deep software standby reset, and watchdog timer reset. table 4.1 shows the reset names and sources. the internal state and pins are initialized by a reset. figure 4.1 shows the reset targets to be initialized. when using power-on reset* and voltage monitoring reset*, res pin must be fixed high. table 4.1 reset names and sources reset name source pin reset voltage input to the res pin is driven low. power-on reset * vcc rises or lowers voltage-monitoring reset * vcc falls (voltage-detection: vdet) deep software standby reset deep software standby mode is canceled by an interrupt. watchdog timer reset the watchdog timer overflows. note: * supported only by the h8sx/1655m group. section 4 reset rev. 2.00 oct. 20, 2009 page 88 of 1340 rej09b0499-0200 vcc res power-on rest circuit registers * (rstsr.porf) rstsr.lvdf lvdcr.lvde lv d r i rstsr.dpsrstf dpsbycr, dpswcr dpsier, dpsifr dpsiegr, dpsbkrn rstcsr for wdt pin reset power-on reset voltage-monitoring reset deep software standby reset watchdog timer reset registers for voltage-monitoring * registers related to power-down mode internal state other than above, and pin states. power-on reset circuit * deep software standby reset generation circuit watchdog timer voltage detection circuit * note: * supported only by the h8sx/1655m group. figure 4.1 block diagram of reset circuit section 4 reset rev. 2.00 oct. 20, 2009 page 89 of 1340 rej09b0499-0200 note that some registers are not initialized by an y of the reset. the following describes the cpu internal registers. the pc, one of the cpu internal re gisters, is initialized by loadin g the start address from vector addresses with the reset exception handling. at this time, the t bit in exr is cleared to 0 and the i bits in exr and ccr are set to 1. the general registers, mac, and other bits in ccr are not initialized. the initial value of the sp (er7) is undefined. the sp should be initialized using the mov.l instruction immediately after a reset. for details, see section 2, cpu. for other registers that are not initialized by a reset, see regist er descriptions in each section. when a reset is canceled, the reset exception handling is started. for the reset exception handling, see section 6.3, reset. 4.2 input/output pin table 4.2 shows the pin related to reset. table 4.2 pin configuration pin name symbol i/o function reset res input reset input section 4 reset rev. 2.00 oct. 20, 2009 page 90 of 1340 rej09b0499-0200 4.3 register descriptions this lsi has the following registers for reset. ? reset status register (rstsr) ? reset control/status register (rstcsr) 4.3.1 reset status register (rstsr) rstsr indicates a source for generating an internal reset and voltage monitoring interrupt. bit bit name initial value: r/w: 7 dpsrstf 0 r/(w) * 1 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 lvdf * 2 0 * 3 r/w * 4 1 ? 0 * 3 r/w 0 porf * 2 0 * 3 r/w * 5 notes: 1. only 0 can be written to clear the flag. 2. supported only by the h8sx/1655m group. 3. initial value is undefined in the h8sx/1655m group. 4. only 0 can be written to clear the flag in the h8sx/1655m group. 5. only read is possible in the h8sx/1655m group. bit bit name initial value r/w description 7 dpsrstf 0 r/(w) * 1 deep software standby reset flag indicates that deep software standby mode is canceled by an interrupt source specified with dpsier or dpsiegr and an internal reset is generated. [setting condition] when deep software standby mode is canceled by an interrupt source. [clearing conditions] ? when this bit is read as 1 and then written by 0. ? when a pin reset, power-on reset * 2 and voltage- monitoring reset * 2 is generated. 6 to 3 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 4 reset rev. 2.00 oct. 20, 2009 page 91 of 1340 rej09b0499-0200 ? h8sx/1655 group bit bit name initial value r/w description 2 to 0 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. ? h8sx/1655m group bit bit name initial value r/w description 2 lvdf undefined r/(w) * 1 lvd flag this bit indicates that the voltage detection circuit has detected a low voltage (vcc at or below vdet). [setting condition] vcc falling to or below vdet. [clearing condition] ? after vcc has exceeded vdet and the specified stabilization period has elapsed, writing 0 to the bit after reading it as 1. ? generation of a pin reset or power-on reset. 1 ? undefined r/w reserved the write value should always be 0. 0 porf undefined r power-on reset flag this bit indicates that a power-on reset has been generated. [setting condition] generation of a power-on reset [clearing condition] generation of a pin reset notes: 1. only 0 can be wr itten to clear the flag. 2. supported only by the h8sx/1655m group. section 4 reset rev. 2.00 oct. 20, 2009 page 92 of 1340 rej09b0499-0200 4.3.2 reset control/status register (rstcsr) rstcsr controls an internal reset signal generated by the watchdog timer and selects the internal reset signal type. rstcsr is initialized to h'1f by a pin reset or a deep software standby reset, but not by the internal reset signal generated by a wdt overflow. bit bit name initial value: r/w: 7 wovf 0 r/(w) * 6 rste 0 r/w 5 ? 0 r/w 4 ? 1 r 3 ? 1 r 2 ? 1 r 1 ? 1 r 0 ? 1 r note: * only 0 can be written to clear the flag. bit bit name initial value r/w description 7 wovf 0 r/(w) * watchdog timer overflow flag this bit is set when tcnt overflows in watchdog timer mode, but not set in interval timer mode. only 0 can be written to. [setting condition] when tcnt overflows (h'ff h'00) in watchdog timer mode. [clearing condition] when this bit is read as 1 and then written by 0. (the flag must be read after writing of 0, when this bit is cleared by the cpu using an interrupt.) 6 rste 0 r/w reset enable selects whether or not the lsi inte rnal state is reset by a tcnt overflow in watchdog timer mode. 0: internal state is not rese t when tcnt overflows. (although this lsi internal state is not reset, tcnt and tcsr of the wdt are reset.) 1: internal state is reset when tcnt overflows. 5 0 r/w reserved although this bit is readable/writ able, operation is not affected by this bit. 4 to 0 1 r reserved these are read-only bits but cannot be modified. note: * only 0 can be written to clear the flag. section 4 reset rev. 2.00 oct. 20, 2009 page 93 of 1340 rej09b0499-0200 4.4 pin reset this is a reset generated by the res pin. when the res pin is driven low, all the processing in progress is aborted and the lsi enters a reset state. in order to firmly reset the lsi, the stby pin should be set to high and the res pin should be held low at least for 20 ms at a power-on. during operation, the res pin should be held low at least for 20 states. 4.5 power-on reset (por) (h8sx/1655m group) this is an internal reset generated by the power-on reset circuit. if res is in the high-level state when power is supplied, a power-on reset is generated. after vcc has exceeded vpor and the specified period (power-on reset time) has elapsed, the chip is released from the power-on reset state. the power-on reset time is a period for stabilization of the external power supply and the lsi circuit. if res is at the high-level when the power-supply voltage (vcc) falls to or below vpor, a power- on reset is generated. the chip is released afte r vcc has risen above vpor and the power-on reset time has elapsed. after a power-on reset has been generated, the porf bit in rstsr is set to 1. the porf bit is in a read-only register and is only initialized by a pin reset. figure 4.2 shows the operation of a power-on reset. section 4 reset rev. 2.00 oct. 20, 2009 page 94 of 1340 rej09b0499-0200 v v v vpor * 1 external power supply vcc vcc vcc vcc vcc res pin por signal ("l" is valid) reset signal ("l" is valid) pin reset and or signal for por porf reset state reset state t por * 2 t por * 2 set set notes: for details of the electrical characteristics, see section 29, electrical characteristics. 1. v por shows a level of power-on reset detection level. 2. t por shows a time for power-on reset. figure 4.2 operation of a power on reset section 4 reset rev. 2.00 oct. 20, 2009 page 95 of 1340 rej09b0499-0200 4.6 power supply monitoring reset (h8sx/1655m group) this is an internal reset generated by the power-supply detection circuit. when vcc falls below vdet in the state where the lvde bit in lvdcr has been set to 1 and the lvdri bit has been cleared to 0, a voltage-monitoring reset is generated. when vcc subsequently rises above vdet, release from the voltage-monitori ng reset proceeds after a specified time has elapsed. for details of the voltage-monitoring reset, see section 5, voltage detection circuit (lvd), and section 29, electrical characteristics. 4.7 deep software standby reset this is an internal reset generated when deep software standby mode is canceled by an interrupt. when deep software standby mode is canceled, a deep software standby reset is generated, and simultaneously, clock oscillation starts. after the time specified with dpswcr has elapsed, the deep software standby reset is canceled. for details of the deep software standby reset, see section 27, power-down modes. 4.8 watchdog timer reset this is an internal reset generated by the watchdog timer. when the rste bit in rstcsr is set to 1, a watchdog timer reset is generated by a tcnt overflow. after a certain time, the watchdog timer reset is canceled. for details of the watchdog timer reset, see section 17, watchdog timer (wdt). section 4 reset rev. 2.00 oct. 20, 2009 page 96 of 1340 rej09b0499-0200 4.9 determination of reset generation source reading rstcsr, rstsr, and lvdcr* of the volta ge detection circuit determines which reset was used to execute the reset exception handling. figure 4.2 shows an example the flow to identify a reset generation source. note: * supported only by the h8sx/1655m group. no pin reset no no yes lvdcr.lvde=1 & lvdcr.lcdri=0 & rstsr.lvdf=1 yes rstsr. porf=1 power-on reset * reset exception handling rstcsr.rste=1 and rstcsr.wovf=1 no yes yes rstsr. dpsrstf=1 deep software standby reset watchdog timer reset voltage monitoring reset * note: * supported only by the h8sx/1655m group. figure 4.3 example of reset generation source determination flow section 5 voltage detection circuit (lvd) rev. 2.00 oct. 20, 2009 page 97 of 1340 rej09b0499-0200 section 5 voltage detection circuit (lvd) the voltage detection circuit (lvd) is only supported by the h8sx/1655m group. this circuit is used to monitor vcc. the lvd is capable of internally resetting the lsi when vcc falls and crosses the voltage detection level. an interrupt can also be generated. 5.1 features ? voltage-detection circuit capable of detecting the power-supply voltage (vcc) becoming less than or equal to vdet. capable of generating an internal reset or interrupt when a low voltage is detected. a block diagram of the voltage detection circuit is shown in figure 5.1. vcc lvdf lvde lvdri lvdmon on-chip reference voltage (for sensing vdet) [legend] lvde: lvd enable lvdri: lvd reset / interrupt select lvdmon: lvd monitor lvdf: lvd flag power-supply stabilization time generation circuit reset / interrupt control circuit voltage-monitoring reset voltage-monitoring interrupt + ? figure 5.1 block diagram of voltage-detection circuit section 5 voltage detection circuit (lvd) rev. 2.00 oct. 20, 2009 page 98 of 1340 rej09b0499-0200 5.2 register descriptions the registers of the voltage det ection circuit are listed below. ? voltage detection control register (lvdcr) ? reset status register (rstsr) 5.2.1 voltage detection cont rol register (lvdcr) the lvdcr controls the voltage-detection circuit. lvde, lvdri, and lvdmon are initialized by a pin reset or power-on reset bit bit name initial value: r/w: 7 lvde 0 r/w 6 lvdri 0 r/w 5 ? 0 r/w 4 lvdmon 0 r 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w bit bit name initial value r/w description 7 lvde 0 r/w lvd enable this bit enables or disables issuing of a reset or interrupt by the voltage-detection circuit. 0: disabled 1: enabled 6 lvdri 0 r/w lvd reset/interrupt select this bit selects whether an internal reset or interrupt is generated when the voltage detection circuit detects a low voltage. when modifying the lvdri bit, ensure that low-voltage detection is in the disabled state (the lvde bit is cleared to 0). 0: a reset is generated when a voltage is detected. 1: an interrupt is generated when a low voltage is detected. 5 ? 0 r/w reserved this bit is always read as 0 and the write value should always be 0. section 5 voltage detection circuit (lvd) rev. 2.00 oct. 20, 2009 page 99 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 lvdmon 0 r lvd monitor this bit monitors the voltage level. this bit is valid when the lvde bit is 1 and read as 0 when the lvde bit is 0. writing to this bit is ineffective. 0: vcc must fall below vdet. 1: vcc must rise above vdet. 3 to 0 ? 0 r/w reserved these bits are always read as 0 and the write value should always be 0. 5.2.2 reset status register (rstsr) rstsr indicates the source of an internal reset or voltage monitoring interrupt. note: * to clear the flag, only 0 should be written to. 7 dpsrstf 0 r/(w) * 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 lvdf undefined r/(w) * 1 ? undefined r/w 0 porf undefined r bit bit name initial value: r/w: bit bit name initial value r/w description 7 dpsrstf 0 r/w * deep software standby reset flag this bit indicates release from deep software standby mode due to the interrupt source selected by dpsier and dpsiegr, and generation of an internal reset. [setting condition] release from deep software standby mode due to an interrupt source. [clearing condition] ? writing 0 to the bit after reading it as1. ? generation of a pin reset, power on reset, or voltage monitoring reset. section 5 voltage detection circuit (lvd) rev. 2.00 oct. 20, 2009 page 100 of 1340 rej09b0499-0200 bit bit name initial value r/w description 6 to 3 ? all 0 r/w reserved these bits are always read as 0 and the write value should always be 0. 2 lvdf undefined r/(w) * lvd flag this bit indicates that the voltage detection circuit has detected a low voltage (vcc at or below vdet). [setting condition] vcc falling to or below vdet. [clearing condition] ? after vcc has exceeded vdet and the specified stabilization period has elapsed, writing 0 to the bit after reading it as 1. ? generation of a pin reset or power-on reset. 1 ? undefined r/w reserved the write value should always be 0. 0 porf undefined r power-on reset flag this bit indicates that a power-on reset has been generated. [setting condition] generation of a power-on reset [clearing condition] generation of a pin reset note: * to clear the flag, only 0 should be written to. section 5 voltage detection circuit (lvd) rev. 2.00 oct. 20, 2009 page 101 of 1340 rej09b0499-0200 5.3 voltage detection circuit 5.3.1 voltage monitoring reset figure 5.2 shows the timing of a voltage monitoring reset by the voltage-detection circuit. when vcc falls below vdet in the state where the lvde bit in lvdcr has been set to 1 and the lvdri bit has been cleared to 0, the lvdf bit is set to 1 and the voltage-detection circuit generates a voltage monitoring reset. next, after vcc has risen above vdet, release from the voltage-monitoring re set takes place after a period for stabilization (t por ) has elapsed. the period for stabilization (t por ) is a time that is generated by the voltage detection circuit in order to stabilize the vcc and the internal circuit of the lsi. when a voltage-monitoring reset is generated, the lvdf bit is set to 1. for details, see section 29, electrical characteristics. vdet vpor lvde lvdri internal reset signal (low) stabilization time (t por ) vcc write 1 write 0 figure 5.2 timing of the voltage-monitoring reset section 5 voltage detection circuit (lvd) rev. 2.00 oct. 20, 2009 page 102 of 1340 rej09b0499-0200 5.3.2 voltage monitoring interrupt figure 5.3 shows the timing of a voltage monitoring interrupt by the voltage-detection circuit. when vcc falls below the vdet in a state wher e the lvde and lvdri bits in lvdcr are both set to 1, the lvdf bit is set to 1 and a voltage monitoring interrupt is requested. the voltage monitoring interrupt signal is internally connected to irq14 -b, so the irq14f bit in the isr is set to 1 when the interrupt is generated. as for the irq14 setting, set both the its14 bit in pfcrb and the irq14e bit in the ier to 1, and the irq14sr and irq14sf bits in the iscr to 01 (interrupt request on falling edge). figure 5.4 shows the procedure for setting the voltage-monitoring interrupt. vdet vpor lvde lvdri stabilization time (t por ) vcc write 1 write 1 lvdf set set voltage-monitoring interrupt signal (irq14) irq14f voltage-monitoring signal write 0 after reading as 1 figure 5.3 timing of the voltage-monitoring interrupt section 5 voltage detection circuit (lvd) rev. 2.00 oct. 20, 2009 page 103 of 1340 rej09b0499-0200 ier.irq14e = write 0 lvdcr.lvdri = write 1 lvdcr.lvde = write 1 pfcrb.its14 = write 1 isr.irq14f = clear clear rstsr.lvdf * ier.irq14e = write 1 iscr setting (irq14sr = 0, irq14sf = 1) lvdcr. lvdmon = 1 (vcc low) (vcc high) no yes note: * when the lvdf cannot be cleared despite vcc being at a higher electrical potential than vdet (lvdmon = 1), the voltage-detection circuit is in the state of waiting for stabilization. clear the bit again after the stabilization time (t por ) has elapsed. start program processing for lowered vcc interrupt generation when a low voltage is detected voltage monitoring interrupt (irq14) disabled voltage detection and irq register settings if the flag has been set to 1 before the voltage-monitoring interrupt is enabled, clear it by writing 0 after having read it as 1. voltage-monitoring interrupt (irq14) enabled processing for lowered vcc figure 5.4 example of the procedure fo r setting the voltage-monitoring interrupt section 5 voltage detection circuit (lvd) rev. 2.00 oct. 20, 2009 page 104 of 1340 rej09b0499-0200 5.3.3 release from deep software standby mode by the voltage-detection circuit if the lvde and lvdri bits in lvdcr and the dlvdie bit in dpsier have all been set to 1 during a period in deep software standby mode, the voltage-detection circuit requests release from deep software standby mode when vcc falls to or below vdet. this sets the dlvdif bit in dpsifr to 1, thus producing release from the deep software standby mode. for the deep software standby mode, see section 27, power-down modes. 5.3.4 voltage monitor the result of voltage detection by the voltage-detection circuit can be monitored by checking the value of the lvdmon bit in lvdcr. when the lvdmon bit has been enabled by setting the lvde bit, 0 indicates that vcc is at or below vd et and 1 indicates that vcc is above vdet. this bit should be read while the voltage-monitoring reset has been disabled by setting the lvdri bit to 1. before clearing the lvdf bit in rstsr to 0, conf irm that the lvdmon bit is set to 1 (indicating that vcc is above vdet). when it is impossible to clear the lv df bit despite the lvdmon bit being 1, the voltage-detection circuit is in the state of waiting for stabilizati on. in such cases, clear the bit again after the stabilization time (t por ) has elapsed. section 6 exception handling rev. 2.00 oct. 20, 2009 page 105 of 1340 rej09b0499-0200 section 6 exception handling 6.1 exception handling types and priority as table 6.1 indicates, exception handling is cause d by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal instruction or slot illegal instruction). exception handling is prioritized as shown in table 6.1. if two or more exceptions occur simu ltaneously, they are accepted and processed in order of priority. exception sources, the stack structure, and operation of the cpu vary depending on the interrupt control mode. for details on the interrupt control mode, see section 7, interrupt controller. table 6.1 exception types and priority priority exception type e xception handling start timing reset exception handling starts at the timing of level change from low to high on the res pin, when deep software standby mode is canceled, or when the watchdog timer overflows. the cpu enters the reset state when the res pin is low. illegal instruction exception handlin g starts when an undefined code is executed. trace * 1 exception handling starts a fter execution of the current instruction or exception handling, if the trace (t) bit in exr is set to 1. address error after an address error has occurred, exception handling starts on completion of instruction execution. interrupt exception handling starts after execution of the current instruction or exception handli ng, if an interrupt request has occurred. * 2 high sleep instruction exception handling star ts by execution of a sleep instruction (sleep), if the ssby bit in sbycr is set to 0 and the slpie bit in sbycr is set to 1. low trap instruction * 3 exception handling starts by execution of a trap instruction (trapa). notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on comple tion of reset exception handling. 3. trap instruction exception handling reques ts and sleep instruction exception handling requests are accepted at all time s in program execution state. section 6 exception handling rev. 2.00 oct. 20, 2009 page 106 of 1340 rej09b0499-0200 6.2 exception sources and exception handling vector table different vector table address offsets are assigned to different exception sources. the vector table addresses are calculated from th e contents of the vector base register (vbr) and vector table address offset of the v ector number. the start address of the exception service routine is fetched from the exception handling vector table indi cated by this vector table address. table 6.2 shows the corresponden ce between the exception sour ces and vector table address offsets. table 6.3 shows the calculation method of exception handling vector table addresses. table 6.2 exception handling vector table vector table address offset * 1 exception source vector number normal mode * 2 advanced, middle * 2 , maximum * 2 modes reset 0 h'0000 to h'0001 h'0000 to h'0003 1 h'0002 to h'0003 h'0004 to h'0007 2 h'0004 to h'0005 h'0008 to h'000b reserved for system use 3 h'0006 to h'0007 h'000c to h'000f illegal instruction 4 h'0008 to h'0009 h'0010 to h'0013 trace 5 h'000a to h'000b h'0014 to h'0017 reserved for system use 6 h'000c to h'000d h'0018 to h'001b interrupt (nmi) 7 h'000e to h'000f h'001c to h'001f trap instruction (#0) 8 h'001 0 to h'0011 h'0020 to h'0023 (#1) 9 h'0012 to h'0013 h'0024 to h'0027 (#2) 10 h'0014 to h'0015 h'0028 to h'002b (#3) 11 h'0016 to h'0017 h'002c to h'002f cpu address error 12 h'0018 to h'0019 h'0030 to h'0033 dma address error * 3 13 h'001a to h'001b h'0034 to h'0037 ubc break interrupt 14 h'001c to h'001d h'0038 to h'003b reserved for system use 15 ? 17 h'001e to h'001f ? h'0022 to h'0023 h'003c to h'003f ? h'0044 to h'0047 sleep interrupt 18 h'0024 to h'0025 h'0048 to h'004b section 6 exception handling rev. 2.00 oct. 20, 2009 page 107 of 1340 rej09b0499-0200 vector table address offset * 1 exception source vector number normal mode * 2 advanced, middle * 2 , maximum * 2 modes reserved for system use 19 ? 23 h'0026 to h'0027 ? h'002e to h'002f h'004c to h'004f ? h'005c to h'005f user area (not used) 24 ? 63 h'0030 to h'0031 ? h'007e to h'007f h'0060 to h'0063 ? h'00fc to h'00ff irq0 64 h'0080 to h'0081 h'0100 to h'0103 irq1 65 h'0082 to h'0083 h'0104 to h'0107 irq2 66 h'0084 to h'0085 h'0108 to h'010b irq3 67 h'0086 to h'0087 h'010c to h'010f irq4 68 h'0088 to h'0089 h'0110 to h'0113 irq5 69 h'008a to h'008b h'0114 to h'0117 irq6 70 h'008c to h'008d h'0118 to h'011b irq7 71 h'008e to h'008f h'011c to h'011f irq8 72 h'0090 to h'0091 h'0120 to h'0123 irq9 73 h'0092 to h'0093 h'0124 to h'0127 irq10 74 h'0094 to h'0095 h'0128 to h'012b external interrupt irq11 75 h'0096 to h'0097 h'012c to h'012f reserved for system use 76 ? 79 h'0098 to h'0099 ? h'009e to h'009f h'0130 to h'0133 ? h'013c to h'013f internal interrupt * 4 80 ? 255 h'00a0 to h'00a1 ? h'01fe to h'01ff h'0140 to h'0143 ? h'03fc to h'03ff notes: 1. lower 16 bits of the address. 2. not available in this lsi. 3. a dma address error is generat ed by the dtc, dmac, and exdmac. 4. for details of internal interrupt vectors, see section 7.5, interrupt exception handling vector table. section 6 exception handling rev. 2.00 oct. 20, 2009 page 108 of 1340 rej09b0499-0200 table 6.3 calculation method of exception handling vector table address exception source calculation method of vector table address reset, cpu address error vector table address = (vector table address offset) other than above vector table address = vbr + (vector table address offset) [legend] vbr: vector base register vector table address offset: see table 6.2. 6.3 reset a reset has priority over any other exception. when the res pin goes low, all processing halts and this lsi enters the reset state. to ensu re that this lsi is reset, hold the res pin low for at least 20 ms with the stby pin driven high when the power is turned on. when operation is in progress, hold the res pin low for at least 20 cycles. the chip can be reset by the overflow that is generated in watchdog timer mode of the watchdog timer. for details, see section 17, watchdog timer (wdt). the chip can also be reset by the exit from deep software standby mode. for details, see section 27, power-down modes. a reset initializes the internal state of the cpu an d the registers of the on -chip peripheral modules. the interrupt control mode is 0 immediately after a reset. 6.3.1 reset exception handling when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized, vbr is cleared to h'00000000, the t bit is cleared to 0 in exr, and the i bits are set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the ad dress indicated by the pc. figures 6.1 and 6.2 show examples of the reset sequence. section 6 exception handling rev. 2.00 oct. 20, 2009 page 109 of 1340 rej09b0499-0200 6.3.2 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a re set. since the first instruction of a program is always executed immediatel y after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 6.3.3 on-chip peripheral functions after reset release after the reset state is released, mstpcra and mstpcrb are initialized to h'0fff and h'ffff, respectively, and all modules except the exdmac , dtc, and dmac enter module stop mode. consequently, on-chip peripheral module registers cannot be read or written to. register reading and writing is enabled when mo dule stop mode is canceled. res high vector fetch internal operation first instruction prefetch (1): reset exception handling vector address (when reset, (1) = h'000000) (2): start address (contents of reset exception handling vector address) (3) start address ((3) = (2)) (4) first instruction in the exception handling routine i internal address bus internal read signal internal write signal internal data bus (1) (2) (4) (3) figure 6.1 reset sequence (on-chip rom enabled advanced mode) section 6 exception handling rev. 2.00 oct. 20, 2009 page 110 of 1340 rej09b0499-0200 res rd hwr , lwr d15 to d0 high * * * b address bus vector fetch internal operation first instruction prefetch (1) (2) (4) (6) (3) (5) (1)(3) reset exception handling vector address (when reset, (1) = h'000000, (3) = h'000002) (2)(4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2)(4)) (6) first instruction in the exception handling routine note: * seven program wait cycles are inserted. figure 6.2 reset sequence (16-bit external access in on-chi p rom disabled advanced mode) section 6 exception handling rev. 2.00 oct. 20, 2009 page 111 of 1340 rej09b0499-0200 6.4 traces traces are enabled in interrupt control mode 2. tr ace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. before changing interrupt control modes, the t bit must be cleared. for details on interrupt control modes, see section 7, interrupt controller. if the t bit in exr is set to 1, trace mode is ac tivated. in trace mode, a tr ace exception occurs on completion of each instruction. trace mode is not affected by interrupt masking by ccr. table 6.4 shows the state of ccr and exr after execution of trace exception handling. trace mode is canceled by clearing the t bit in exr to 0 during the trace exception handling. however, the t bit saved on the stack retains its value of 1, and wh en control is returned from the trace exception handling routine by the rte in struction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. interrupts are accepted even within th e trace exception handling routine. table 6.4 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 trace exception handling cannot be used. 2 1 ? ? 0 [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. section 6 exception handling rev. 2.00 oct. 20, 2009 page 112 of 1340 rej09b0499-0200 6.5 address error 6.5.1 address error source instruction fetch, stack operation, or data read/write shown in table 6.5 may cause an address error. table 6.5 bus cycle and address error bus cycle type bus master description address error fetches instructions from even addresses no (normal) fetches instructions from odd addresses occurs fetches instructions from areas other than on- chip peripheral module space * 1 no (normal) fetches instructions from on-chip peripheral module space * 1 occurs fetches instructions from external memory space in single-chip mode occurs instruction fetch cpu fetches instructions from access prohibited area .* 2 occurs accesses stack when the stack pointer value is even address no (normal) stack operation cpu accesses stack when the stack pointer value is odd address. occurs accesses word data from even addresses no (normal) accesses word data from odd addresses no (normal) accesses external memory space in single-chip mode occurs data read/write cpu accesses to access prohibited area * 2 occurs section 6 exception handling rev. 2.00 oct. 20, 2009 page 113 of 1340 rej09b0499-0200 bus cycle type bus master description address error accesses word data from even addresses no (normal) accesses word data from odd addresses no (normal) accesses external memory space in single-chip mode occurs data read/write dtc or dmac accesses to access prohibited area * 2 occurs accesses word data from even addresses no (normal) accesses word data from odd addresses no (normal) accesses external memory space in single-chip mode occurs accesses access prohibited area * 2 occurs accesses external memory space no (normal) data read/write exdmac accesses areas other than external memory space occurs address access space is the external memory space for single address transfer no (normal) single address transfer dmac/ exdmac address access space is not the external memory space for single address transfer occurs notes: 1. for on-chip peripheral module spac e, see section 9, bus controller (bsc). 2. for the access prohibited area, refer to fi gures 3.1 and 3.2 in sect ion 3.4, address map. section 6 exception handling rev. 2.00 oct. 20, 2009 page 114 of 1340 rej09b0499-0200 6.5.2 address error exception handling when an address error occurs, address error excep tion handling starts after the bus cycle causing the address error ends and curren t instruction execution complete s. the address error exception handling is as follows: 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is update d and the t bit is cleared to 0. 3. an exception handling vector table address corresponding to the address error is generated, the start address of the exception se rvice routine is loaded from the vector table to pc, and program execution starts from that address. even though an address error occurs during a tran sition to an address error exception handling, the address error is not accepte d. this prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. if the sp contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (pc, ccr, and exr) are undefined. when an address error occurs, the following is performed to halt the dtc, dmac, and exdmac. ? the err bit of dtccr in the dtc is set to 1. ? the errf bit of dmdr_0 in the dmac is set to 1. ? the errf bit of edmdr_0 in the exdmac is set to 1. ? the dte bits of dmdrs for all channels in the dmac are cleared to 0 to forcibly terminate transfer. ? the dte bits of edmdr for all channels in the exdmac are cleared to 0 to forcibly terminate transfer. section 6 exception handling rev. 2.00 oct. 20, 2009 page 115 of 1340 rej09b0499-0200 table 6.6 shows the state of ccr and exr after execution of the address error exception handling. table 6.6 status of ccr and exr af ter address error exception handling ccr exr interrupt control mode i ui t i2 to i0 0 1 ? ? ? 2 1 ? 0 7 [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. section 6 exception handling rev. 2.00 oct. 20, 2009 page 116 of 1340 rej09b0499-0200 6.6 interrupts 6.6.1 interrupt sources interrupt sources are nmi, ubc break interrupt, irq0 to irq11, and on-chip peripheral modules, as shown in table 6.7. table 6.7 interrupt sources type source number of sources nmi nmi pin (external input) 1 ubc break interrupt user break controller (ubc) 1 irq0 to irq11 pins irq0 to irq11 (external input) 12 voltage-detection circuit voltage-detection circuit (lvd) * 1 dma controller (dmac) 8 exdma controller (exdmac) 8 watchdog timer (wdt) 1 a/d converter 2 16-bit timer pulse unit (tpu) 52 8-bit timer (tmr) 16 serial communications interface (sci) 24 i 2 c bus interface 2 (iic2) 2 on-chip peripheral module usb function module (usb) 5 note: * supported only by the h8sx/1655m group. different vector numbers and vector table offsets are assigned to different interrupt sources. for vector number and vector table offset, refer to table 7.2, interrupt sources, vect or address offsets, and interrupt priority in section 7, interrupt controller. section 6 exception handling rev. 2.00 oct. 20, 2009 page 117 of 1340 rej09b0499-0200 6.6.2 interrupt exception handling interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi or sleep interrupt to eight priority/mask levels to enable multiple-interrupt control. the so urce to start interrupt exception handling and the vector address differ depending on the product. for details, refer to section 7, interrupt controller. the interrupt exception handling is as follows: 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is updated and the t bit is cleared to 0. 3. an exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routin e is loaded from the vector table to pc, and program execution starts from that address. section 6 exception handling rev. 2.00 oct. 20, 2009 page 118 of 1340 rej09b0499-0200 6.7 instruction exception handling there are three instructions that cause exception handling: trap inst ruction, sleep instruction, and illegal instruction. 6.7.1 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. the trap instruction exception handling is as follows: 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is update d and the t bit is cleared to 0. 3. an exception handling vector table address co rresponding to the vect or number specified in the trapa instruction is generated, the start addr ess of the exception serv ice routine is loaded from the vector table to pc, and progra m execution starts from that address. a start address is read from the vector table corr esponding to a vector number from 0 to 3, as specified in the instruction code. table 6.8 shows the state of ccr and exr after execution of trap instruction exception handling. table 6.8 status of ccr and exr aft er trap instruction exception handling ccr exr interrupt control mode i ui t i2 to i0 0 1 ? ? ? 2 1 ? 0 ? [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. section 6 exception handling rev. 2.00 oct. 20, 2009 page 119 of 1340 rej09b0499-0200 6.7.2 sleep instruction exception handling the sleep instruction exception handling starts when a sleep instruction is executed with the ssby bit in sbycr set to 0 and the slpie bit in sbycr set to 1. the sleep instruction exception handling can always be executed in the program execution state. in the exception handling, the cpu operates as follows. 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is updated and the t bit is cleared to 0. 3. an exception handling vector table address co rresponding to the vect or number specified in the sleep instruction is generated, the start addr ess of the excepti on service routine is loaded from the vector table to pc, and progra m execution starts fr om that address. bus masters other than the cpu may gain the bus mastership after a sleep instruction has been executed. in such cases the sleep instruction will be started when the transactions of a bus master other than the cpu has been completed and the cpu has gained the bus mastership. table 6.9 shows the state of ccr and exr after execution of sleep instruction exception handling. for the detail, see section 27.10, sleep instruction exception handling. table 6.9 status of ccr and exr aft er sleep instruction exception handling ccr exr interrupt control mode i ui t i2 to i0 0 1 ? ? ? 2 1 ? 0 7 [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. section 6 exception handling rev. 2.00 oct. 20, 2009 page 120 of 1340 rej09b0499-0200 6.7.3 exception handling by illegal instruction the illegal instructions are general illegal instructions and slot illegal instructions. the exception handling by the general illegal instruction starts when an undefined code is executed. the exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code length is two words or more, or it changes the pc contents) at a delay slot (immediately after a delayed branch instruction) is executed. the exception handling by the general illegal instruction and slot illegal instruction is always ex ecutable in the program execution state. the exception handling is as follows: 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is update d and the t bit is cleared to 0. 3. an exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception servi ce routine is loaded from the vector table to pc, and program execution starts from that address. table 6.10 shows the state of ccr and exr after execution of illegal instruction exception handling. table 6.10 status of ccr and exr after illegal instruction exception handling ccr exr interrupt control mode i ui t i2 to i0 0 1 ? ? ? 2 1 ? 0 ? [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. section 6 exception handling rev. 2.00 oct. 20, 2009 page 121 of 1340 rej09b0499-0200 6.8 stack status after exception handling figure 6.3 shows the stack after completion of exception handling. ccr pc (24 bits) sp exr reserved * ccr pc (24 bits) sp advanced mode interrupt control mode 0 interrupt control mode 2 note: * ignored on return. figure 6.3 stack status after exception handling section 6 exception handling rev. 2.00 oct. 20, 2009 page 122 of 1340 rej09b0499-0200 6.9 usage note when performing stack-man ipulating access, this lsi assumes that the lowest address bit is 0. the stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (sp: er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) performing stack manipulation while sp is set to an odd value leads to an ad dress error. figure 6.4 shows an example of operatio n when the sp value is odd. sp ccr : pc : r1l : sp : condition code register program counter general register r1l stack pointer ccr sp sp r1l h'fffefa h'fffefb h'fffefc h'fffefd h'fffefe h'fffeff pc pc trapa instruction executed sp set to h'fffeff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost address [legend] note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. (address error occurred) figure 6.4 operation when sp value is odd section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 123 of 1340 rej09b0499-0200 section 7 interrupt controller 7.1 features ? two interrupt control modes any of two interrupt control modes can be set by means of bits intm1 and intm0 in the interrupt control register (intcr). ? priority can be assigned by the in terrupt priority register (ipr) ipr provides for setting interrupt priory. eight levels can be set for each module for all interrupts except for the interrupt requests listed below. the following seven interrupt requests are given priority of 8, therefor e they are accepted at all times. ? nmi ? illegal instructions ? trace ? trap instructions ? cpu address error ? dma address error (occurred in the dtc, dmac, and exdmac) ? sleep instruction ? independent vector addresses all interrupt sources are assigned independent v ector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? thirteen external interrupts nmi is the highest-priority interrupt, and is accep ted at all times. rising edge or falling edge detection can be selected for nm i. falling edge, rising edge, or both edges detection, or level sensing, can be selected for irq11 to irq0 . ? dtc and dmac control dtc and dmac can be activated by means of interrupts. ? cpu priority control function the priority levels can be assigned to the cpu, dtc, and dmac, exdmac. the priority level of the cpu can be automatically assigned on an exception generation. priority can be given to the cpu interrupt exception handling over that of the dtc, dmac, and exdmac transfer. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 124 of 1340 rej09b0499-0200 a block diagram of the interrupt controller is shown in figure 7.1. intcr ipr nmi input irq11 to irq0 input internal interrupt sources wovi to resume intm1, intm0 nmieg nmi input unit irq input unit cpu priority dtc priority interrupt controller priority determination source selector cpu interrupt request cpu vector dtc vector activation request clear signal dtc activation request i i2 to i0 ccr exr cpu dtc intcr: cpupcr: iscr: ier: isr: interrupt control register cpu priority control register irq sense control register irq enable register irq status register ssier: ipr: dtcer: dtccr: software standby release irq enable register interrupt priority register dtc enable register dtc control register [legend] iscr ssier ier dtcer dtc priority control dtccr isr dmac activation permission dmdr dmac dmac priority control cpupcr irq14 input lvd * note: * supported only by the h8sx/1655m group. figure 7.1 block diagra m of interrupt controller section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 125 of 1340 rej09b0499-0200 7.2 input/output pins table 7.1 shows the pin configuration of the interrupt controller. table 7.1 pin configuration name i/o function nmi input nonmaskable external interrupt rising or falling edge can be selected. irq11 to irq0 input maskable external interrupts rising, falling, or both edges , or level sensing, can be independently selected. 7.3 register descriptions the interrupt controller has the following registers. ? interrupt control register (intcr) ? cpu priority control register (cpupcr) ? interrupt priority registers a to c, e to o, q, and r (ipra to iprc, ipre to ipro, iprq, and iprr) ? irq enable register (ier) ? irq sense control registers h and l (iscrh, iscrl) ? irq status register (isr) ? software standby release ir q enable register (ssier) section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 126 of 1340 rej09b0499-0200 7.3.1 interrupt control register (intcr) intcr selects the interrupt control mode, and the edge to detect nmi. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 7 6 ? ? 0 0 r r reserved these are read-only bits and cannot be modified. 5 4 intm1 intm0 0 0 r/w r/w interrupt control select mode 1 and 0 these bits select either of two interrupt control modes for the interrupt controller. 00: interrupt control mode 0 interrupts are controlled by i bit in ccr. 01: setting prohibited. 10: interrupt control mode 2 interrupts are controlled by bits i2 to i0 in exr, and ipr. 11: setting prohibited. 3 nmieg 0 r/w nmi edge select selects the input edge for the nmi pin. 0: interrupt request generated at falling edge of nmi input 1: interrupt request generated at rising edge of nmi input 2 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 127 of 1340 rej09b0499-0200 7.3.2 cpu priority control register (cpupcr) cpupcr sets whether or not the cpu has priority over the dtc, dmac, and exdmac. the interrupt exception handling by the cpu can be given priority over that of the dtc, dmac, and exdmac transfer. the priority level of the dtc is set by bits dtcp2 to dtcp0 in cpupcr. the priority level of the dmac and exdmac are set by the dmac and exdmac control registers for each channel. bit bit name initial value r/w note: * when the ipsete bit is set to 1, the cpu priority is automatically updated, so these bits cannot be modified. 7 cpupce 0 r/w 6 dtcp2 0 r/w 5 dtcp1 0 r/w 4 dtcp0 0 r/w 3 ipsete 0 r/w 2 cpup2 0 r/(w) * 1 cpup1 0 r/(w) * 0 cpup0 0 r/(w) * bit bit name initial value r/w description 7 cpupce 0 r/w cpu priority control enable controls the cpu priority control function. setting this bit to 1 enables the cpu priority control over the dtc, dmac, and exdmac. 0: cpu always has the lowest priority 1: cpu priority control enabled 6 5 4 dtcp2 dtcp1 dtcp0 0 0 0 r/w r/w r/w dtc priority level 2 to 0 these bits set the dtc priority level. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 128 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 ipsete 0 r/w interrupt priority set enable controls the function which automatically assigns the interrupt priority level of t he cpu. setting this bit to 1 automatically sets bits cpup2 to cpup0 by the cpu interrupt mask bit (i bit in ccr or bits i2 to i0 in exr). 0: bits cpup2 to cpup0 ar e not updated automatically 1: the interrupt mask bit value is reflected in bits cpup2 to cpup0 2 1 0 cpup2 cpup1 cpup0 0 0 0 r/(w) * r/(w) * r/(w) * cpu priority level 2 to 0 these bits set the cpu priority level. when the cpupce is set to 1, the cpu priority control function over the dtc, dmac, and exdmac becomes valid and the priority of cpu processing is assigned in accordance with the settings of bits cpup2 to cpup0. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) note: * when the ipsete bit is set to 1, the cpu priori ty is automatically updated, so these bits cannot be modified. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 129 of 1340 rej09b0499-0200 7.3.3 interrupt priority registers a to c, e to o, q, and r (ipra to iprc, ipre to ipro, iprq, and iprr) ipr sets priory (levels 7 to 0) for interrupts other than nmi. setting a value in the range from b'000 to b'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. for the correspondence between the interrupt sources and the ipr settings, see table 7.2. bit bit name initial value r/w 15 ? 0 r 14 ipr14 1 r/w 13 ipr13 1 r/w 12 ipr12 1 r/w 11 ? 0 r 10 ipr10 1 r/w 9 ipr9 1 r/w 8 ipr8 1 r/w bit bit name initial value r/w 7 ? 0 r 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 ? 0 r 2 ipr2 1 r/w 1 ipr1 1 r/w 0 ipr0 1 r/w bit bit name initial value r/w description 15 ? 0 r reserved this is a read-only bit and cannot be modified. 14 13 12 ipr14 ipr13 ipr12 1 1 1 r/w r/w r/w sets the priority level of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 11 ? 0 r reserved this is a read-only bit and cannot be modified. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 130 of 1340 rej09b0499-0200 bit bit name initial value r/w description 10 9 8 ipr10 ipr9 ipr8 1 1 1 r/w r/w r/w sets the priority level of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 7 ? 0 r reserved this is a read-only bit and cannot be modified. 6 5 4 ipr6 ipr5 ipr4 1 1 1 r/w r/w r/w sets the priority level of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 3 ? 0 r reserved this is a read-only bit and cannot be modified. 2 1 0 ipr2 ipr1 ipr0 1 1 1 r/w r/w r/w sets the priority level of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 131 of 1340 rej09b0499-0200 7.3.4 irq enable register (ier) ier enables interrupt requests irq14, and irq11 to irq0. bit bit name initial value r/w 15 ? 0 r/w 14 irq14e * 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 irq11e 0 r/w 10 irq10e 0 r/w 9 irq9e 0 r/w 8 irq8e 0 r/w bit bit name initial value r/w 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e 0 r/w note: * supported only by the h8sx/1655m group. bit bit name initial value r/w description 15 all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 14 irq14e * 0 r/w irq14 enable the irq14 interrupt request is enabled when this bit is 1.the irq14 is internally connected to the voltage- detection interrupt. 13 to 12 all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 11 irq11e 0 r/w irq11 enable the irq10 interrupt request is enabled when this bit is 1. 10 irq10e 0 r/w irq10 enable the irq11 interrupt request is enabled when this bit is 1. 9 irq9e 0 r/w irq9 enable the irq9 interrupt request is enabled when this bit is 1. 8 irq8e 0 r/w irq8 enable the irq8 interrupt request is enabled when this bit is 1. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 132 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 irq7e 0 r/w irq7 enable the irq7 interrupt request is enabled when this bit is 1. 6 irq6e 0 r/w irq6 enable the irq6 interrupt request is enabled when this bit is 1. 5 irq5e 0 r/w irq5 enable the irq5 interrupt request is enabled when this bit is 1. 4 irq4e 0 r/w irq4 enable the irq4 interrupt request is enabled when this bit is 1. 3 irq3e 0 r/w irq3 enable the irq3 interrupt request is enabled when this bit is 1. 2 irq2e 0 r/w irq2 enable the irq2 interrupt request is enabled when this bit is 1. 1 irq1e 0 r/w irq1 enable the irq1 interrupt request is enabled when this bit is 1. 0 irq0e 0 r/w irq0 enable the irq0 interrupt request is enabled when this bit is 1. note: * supported only by the h8sx/1655m group. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 133 of 1340 rej09b0499-0200 7.3.5 irq sense control registers h and l (iscrh, iscrl) iscr selects the source that genera tes an interrupt request from irq14 and irq11 to irq0 input. upon changing the setting of iscr, irqnf (n = 0 to 11, 14) in isr is often set to 1 accidentally through an internal operation. in this case, an in terrupt exception handling is executed if an irqn interrupt request is enabled. in order to prevent such an accidental interrupt from occurring, the setting of iscr should be changed while the irqn interrupt is disabled, and then the irqnf in isr should be cleared to 0. ? iscrh bit bit name initial value r/w bit bit name initial value r/w 15 ? 0 r/w 14 ? 0 r/w 13 irq14sr * 0 r/w 12 irq14sf * 0 r/w 11 ? 0 r/w 10 ? 0 r/w 9 ? 0 r/w 8 ? 0 r/w 7 irq11sr 0 r/w 6 irq11sf 0 r/w 5 irq10sr 0 r/w 4 irq10sf 0 r/w 3 irq9sr 0 r/w 2 irq9sf 0 r/w 1 irq8sr 0 r/w 0 irq8sf 0 r/w ? iscrl bit bit name initial value r/w bit bit name initial value r/w 15 irq7sr 0 r/w 14 irq7sf 0 r/w 13 irq6sr 0 r/w 12 irq6sf 0 r/w 11 irq5sr 0 r/w 10 irq5sf 0 r/w 9 irq4sr 0 r/w 8 irq4sf 0 r/w 7 irq3sr 0 r/w 6 irq3sf 0 r/w 5 irq2sr 0 r/w 4 irq2sf 0 r/w 3 irq1sr 0 r/w 2 irq1sf 0 r/w 1 irq0sr 0 r/w 0 irq0sf 0 r/w note: * supported only by the h8sx/1655m group. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 134 of 1340 rej09b0499-0200 ? iscrh bit bit name initial value r/w description 15 to 14 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 13 12 irq14sr * irq14sf * 0 0 r/w r/w irq14 sense control rise irq14 sense control fall irq14 is used as the lvd voltage-monitoring interrupt * . when used as irq14, set the interrupt request at falling edge. 00: initial value 01: interrupt request generated at falling edge of irq14 10: setting prohibited 11: setting prohibited 11 to 8 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 7 6 irq11sr irq11sf 0 0 r/w r/w irq11 sense control rise irq11 sense control fall 00: interrupt request generated by low level of irq11 01: interrupt request generated at falling edge of irq11 10: interrupt request generated at rising edge of irq11 11: interrupt request generated at both falling and rising edges of irq11 5 4 irq10sr irq10sf 0 0 r/w r/w irq10 sense control rise irq10 sense control fall 00: interrupt request generated by low level of irq10 01: interrupt request generated at falling edge of irq10 10: interrupt request generated at rising edge of irq10 11: interrupt request generated at both falling and rising edges of irq10 section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 135 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 2 irq9sr irq9sf 0 0 r/w r/w irq9 sense control rise irq9 sense control fall 00: interrupt request generated by low level of irq9 01: interrupt request generated at falling edge of irq9 10: interrupt request generated at rising edge of irq9 11: interrupt request generated at both falling and rising edges of irq9 1 0 irq8sr irq8sf 0 0 r/w r/w irq8 sense control rise irq8 sense control fall 00: interrupt request generated by low level of irq8 01: interrupt request generated at falling edge of irq8 10: interrupt request generated at rising edge of irq8 11: interrupt request generated at both falling and rising edges of irq8 note: supported only by the h8sx/1655m group. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 136 of 1340 rej09b0499-0200 ? iscrl bit bit name initial value r/w description 15 14 irq7sr irq7sf 0 0 r/w r/w irq7 sense control rise irq7 sense control fall 00: interrupt request generated by low level of irq7 01: interrupt request generated at falling edge of irq7 10: interrupt request generated at rising edge of irq7 11: interrupt request generated at both falling and rising edges of irq7 13 12 irq6sr irq6sf 0 0 r/w r/w irq6 sense control rise irq6 sense control fall 00: interrupt request generated by low level of irq6 01: interrupt request generated at falling edge of irq6 10: interrupt request generated at rising edge of irq6 11: interrupt request generated at both falling and rising edges of irq6 11 10 irq5sr irq5sf 0 0 r/w r/w irq5 sense control rise irq5 sense control fall 00: interrupt request generated by low level of irq5 01: interrupt request generated at falling edge of irq5 10: interrupt request generated at rising edge of irq5 11: interrupt request generated at both falling and rising edges of irq5 9 8 irq4sr irq4sf 0 0 r/w r/w irq4 sense control rise irq4 sense control fall 00: interrupt request generated by low level of irq4 01: interrupt request generated at falling edge of irq4 10: interrupt request generated at rising edge of irq4 11: interrupt request generated at both falling and rising edges of irq4 7 6 irq3sr irq3sf 0 0 r/w r/w irq3 sense control rise irq3 sense control fall 00: interrupt request generated by low level of irq3 01: interrupt request generated at falling edge of irq3 10: interrupt request generated at rising edge of irq3 11: interrupt request generated at both falling and rising edges of irq3 section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 137 of 1340 rej09b0499-0200 bit bit name initial value r/w description 5 4 irq2sr irq2sf 0 0 r/w r/w irq2 sense control rise irq2 sense control fall 00: interrupt request generated by low level of irq2 01: interrupt request generated at falling edge of irq2 10: interrupt request generated at rising edge of irq2 11: interrupt request generated at both falling and rising edges of irq2 3 2 irq1sr irq1sf 0 0 r/w r/w irq1 sense control rise irq1 sense control fall 00: interrupt request generated by low level of irq1 01: interrupt request generated at falling edge of irq1 10: interrupt request generated at rising edge of irq1 11: interrupt request generated at both falling and rising edges of irq1 1 0 irq0sr irq0sf 0 0 r/w r/w irq0 sense control rise irq0 sense control fall 00: interrupt request generated by low level of irq0 01: interrupt request generated at falling edge of irq0 10: interrupt request generated at rising edge of irq0 11: interrupt request generated at both falling and rising edges of irq0 section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 138 of 1340 rej09b0499-0200 7.3.6 irq status register (isr) isr is an irq14 and irq11 to irq0 interrupt request register. bit bit name initial value r/w 15 ? 0 r/(w) * 1 14 irq14f * 2 0 r/(w) * 1 13 ? 0 r/(w) * 1 12 ? 0 r/(w) * 1 11 irq11f 0 r/(w) * 1 10 irq10f 0 r/(w) * 1 9 irq9f 0 r/(w) * 1 8 irq8f 0 r/(w) * 1 bit bit name initial value r/w notes: 1. only 0 can be written, to clear the flag. the bit manipulation instructions or memory operation instructions should be used to clear the flag. 2. supported only by the h8sx/1655m group. 7 irq7f 0 r/(w) * 1 6 irq6f 0 r/(w) * 1 5 irq5f 0 r/(w) * 1 4 irq4f 0 r/(w) * 1 3 irq3f 0 r/(w) * 1 2 irq2f 0 r/(w) * 1 1 irq1f 0 r/(w) * 1 0 irq0f 0 r/(w) * 1 bit bit name initial value r/w description 15 all 0 r/(w) * 1 reserved these bits are always read as 0. the write value should always be 0. 14 irq14f * 2 0 r/(w) * 1 [setting condition] ? when the interrupt selected by iscr occurs [clearing conditions] ? writing 0 after reading irq14f = 1 ? when irq14 interrupt exception handling is executed while falling edge sensing is selected. 13, 12 all 0 r/(w) * 1 reserved these bits are always read as 0. the write value should always be 0. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 139 of 1340 rej09b0499-0200 bit bit name initial value r/w description 11 10 9 8 7 6 5 4 3 2 1 0 irq11f irq10f irq9f irq8f irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 [setting condition] ? when the interrupt selected by iscr occurs [clearing conditions] ? writing 0 after reading irqnf = 1 ? when interrupt exception handling is executed while low-level sensing is selected and irqn input is high (n = 11 to 0). ? when irqn interrupt exception handling is executed while falling-, rising-, or both-edge sensing is selected. ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0. notes: 1. only 0 can be wr itten, to clear the flag. 2. supported only by the h8sx/1655m group. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 140 of 1340 rej09b0499-0200 7.3.7 software standby release ir q enable register (ssier) ssier selects the irq interrupt used to leave software standby mode. the irq interrupt used to leave software standby mode should not be set as the dtc activation source. bit bit name initial value r/w 15 ? 0 r/w 14 ? 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 ssi11 0 r/w 10 ssi10 0 r/w 9 ssi9 0 r/w 8 ssi8 0 r/w bit bit name initial value r/w 7 ssi7 0 r/w 6 ssi6 0 r/w 5 ssi5 0 r/w 4 ssi4 0 r/w 3 ssi3 0 r/w 2 ssi2 0 r/w 1 ssi1 0 r/w 0 ssi0 0 r/w bit bit name initial value r/w description 15 to 12 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 11 10 9 8 7 6 5 4 3 2 1 0 ssi11 ssi10 ssi9 ssi8 ssi7 ssi6 ssi5 ssi4 ssi3 ssi2 ssi1 ssi0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w software standby release irq setting these bits select the irqn interrupt used to leave software standby mode (n = 11 to 0). 0: an irqn request is not sampled in software standby mode 1: when an irqn request occurs in software standby mode, this lsi leaves software standby mode after the oscillation settling time has elapsed section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 141 of 1340 rej09b0499-0200 7.4 interrupt sources 7.4.1 external interrupts there are thirteen external inte rrupts: nmi and irq11 to irq0. these interrupts can be used to leave software standby mode. (1) nmi interrupts nonmaskable interrupt request (nm i) is the highest-priority interr upt, and is always accepted by the cpu regardless of the interrupt control mode or the settings of the cpu interrupt mask bits. the nmieg bit in intcr selects whether an interrupt is requested at the rising or falling edge on the nmi pin. when an nmi interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure. ? sets the err bit of dtccr in the dtc to 1. ? sets the errf bit of dmdr_0 in dmac to 1. ? sets the errf bit of edmdr_0 in the exdmac to 1 ? clears the dte bits of dmdrs for all channels in the dmac to 0 to forcibly terminate transfer ? clears the dte bits of edmdrs for all channels in the exdmac to 0 to forcibly terminate transfer (2) irqn interrupts an irqn interrupt is requested by a signal input on pins irq11 to irq0 . irqn (n = 11 to 0) have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins irqn . ? enabling or disabling of interrupt requests irqn can be selected by ier. ? the interrupt priority can be set by ipr. ? the status of interrupt requests irqn is indicat ed in isr. isr flags can be cleared to 0 by software. the bit manipulation instructions and memory operation instructions should be used to clear the flag. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 142 of 1340 rej09b0499-0200 detection of irqn interrupts is enabled throug h the p1icr, p2icr, p5icr, and p6icr register settings, and does not change regardless of the output setting. however, when a pin is used as an external interrupt input pin, the pin must not be used as an i/o pin for another function by clearing the corresponding ddr bit to 0. a block diagram of interrupts irqn is shown in figure 7.2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit input buffer corresponding bit in icr irqnsf, irqnsr irqn input [legend] n = 11 to 0 figure 7.2 block diagra m of interrupts irqn when the irq sensing control in iscr is set to a low level of signal irqn , the level of irqn should be held low until an interrupt handling starts. then set the corresponding input signal irqn to high in the interrupt handling routine and clear the irqnf to 0. interrupts may not be executed when the corresponding input signal irqn is set to high before the interrupt handling begins. 7.4.2 internal interrupts the sources for internal interrupts from on-chip peripheral modules have the following features: ? for each on-chip peripheral module there are fl ags that indicate the in terrupt request status, and enable bits that enable or disable these interrupts. they can be controlled independently. when the enable bit is set to 1, an interrupt request is issued to the interrupt controller. ? the interrupt priority can be set by means of ipr. ? the dtc and dmac can be activated by a tpu, sci, or other interrupt request. ? the priority levels of dtc and dmac activation can be controlled by the dtc and dmac priority control functions. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 143 of 1340 rej09b0499-0200 7.5 interrupt exception handling vector table table 7.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. in the default priority order, a lower vector number corresponds to a higher priority. when interrupt control mode 2 is set, priority levels can be changed by setting the ipr contents. the priority for interrupt sources allocated to the same level in ipr follows the default priority, that is, they are fixed. table 7.2 interrupt sources , vector address offsets, and interrupt priority vector address offset * 1 classification interrupt source vector number advanced mode, middle mode, maximum mode ipr priority dtc activation dmac activation external pin nmi 7 h'001c ? ? ? ubc ubc break interrupt 14 h'0038 ? ? ? irq0 64 h'0100 ipra14 to ipra12 o ? irq1 65 h'0104 ipra10 to ipra8 o ? irq2 66 h'0108 ipra6 to ipra4 o ? irq3 67 h'010c ipra2 to ipra0 o ? irq4 68 h'0110 iprb14 to iprb12 o ? irq5 69 h'0114 iprb10 to iprb8 o ? irq6 70 h'0118 iprb6 to iprb4 o ? irq7 71 h'011c iprb2 to iprb0 o ? irq8 72 h'0120 iprc14 to iprc12 o ? irq9 73 h'0124 iprc10 to iprc8 o ? irq10 74 h'0128 iprc6 to iprc4 o ? external pin irq11 75 h'012c iprc2 to iprc0 o ? 76 h'0130 ? ? ? reserved for system use 77 h'0134 ? ? ? lvd * 2 voltage- monitoring interrupt (irq14) 78 h'0138 iprd6 to iprd4 ? ? 79 h'013c ? ? ? reserved for system use 80 h'0140 ? high ? ? wdt wovi 81 h'0144 ipre10 to ipre8 low ? ? section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 144 of 1340 rej09b0499-0200 vector address offset * 1 classification interrupt source vector number advanced mode, middle mode, maximum mode ipr priority dtc activation dmac activation 82 h'0148 ? ? 84 h'0150 ? ? ? reserved for system use 85 h'0154 ? ? ? a/d_0 adi0 86 h'0158 iprf10 to iprf8 o o ? reserved for system use 87 h'015c ? ? ? tgi0a 88 h'0160 o o tgi0b 89 h'0164 o ? tgi0c 90 h'0168 o ? tgi0d 91 h'016c o ? tpu_0 tci0v 92 h'0170 iprf6 to iprf4 ? ? tgi1a 93 h'0174 o o tgi1b 94 h'0178 o ? tci1v 95 h'017c ? ? tpu_1 tci1u 96 h'0180 iprf2 to iprf0 ? ? tgi2a 97 h'0184 o o tgi2b 98 h'0188 o ? tci2v 99 h'018c ? ? tpu_2 tci2u 100 h'0190 iprg14 to iprg12 ? ? tgi3a 101 h'0194 o o tgi3b 102 h'0198 o ? tgi3c 103 h'019c o ? tgi3d 104 h'01a0 o ? tpu_3 tci3v 105 h'01a4 iprg10 to iprg8 ? ? tgi4a 106 h'01a8 o o tgi4b 107 h'01ac o ? tci4v 108 h'01b0 high ? ? tpu_4 tci4u 109 h'01b4 iprg6 to iprg4 low ? ? section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 145 of 1340 rej09b0499-0200 vector address offset * 1 classification interrupt source vector number advanced mode, middle mode, maximum mode ipr priority dtc activation dmac activation tgi5a 110 h'01b8 o o tgi5b 111 h'01bc o ? tci5v 112 h'01c0 ? ? tpu_5 tci5u 113 h'01c4 iprg2 to iprg0 ? ? 114 h'01c8 ? ? ? reserved for system use 115 h'01cc ? ? ? cmi0a 116 h'01d0 o ? cmi0b 117 h'01d4 o ? tmr_0 ov0i 118 h'01d8 iprh14 to iprh12 ? ? cmi1a 119 h'01dc o ? cmi1b 120 h'01e0 o ? tmr_1 ov1i 121 h'01e4 iprh10 to iprh8 ? ? cmi2a 122 h'01e8 o ? cmi2b 123 h'01ec o ? tmr_2 ov2i 124 h'01f0 iprh6 to iprh4 ? ? cmi3a 125 h'01f4 o ? cmi3b 126 h'01f8 o ? tmr_3 ov3i 127 h'01fc iprh2 to iprh0 ? ? dmtend0 128 h'0200 ipri14 to ipri12 o ? dmtend1 129 h'0204 ipri10 to ipri8 o ? dmtend2 130 h'0208 ipri6 to ipri4 o ? dmac dmtend3 131 h'020c ipri2 to ipri0 o ? exdmtend0 132 h'0210 iprj14 to iprj12 o ? exdmtend1 133 h'0214 iprj10 to iprj8 o ? exdmtend2 134 h'0218 iprj6 to iprj4 o ? exdmac exdmtend3 135 h'021c iprj2 to iprj0 o ? dmeend0 136 h'0220 o ? dmeend1 137 h'0224 o ? dmeend2 138 h'0228 high o ? dmac dmeend3 139 h'022c iprk14 to iprk12 low o ? section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 146 of 1340 rej09b0499-0200 vector address offset * 1 classification interrupt source vector number advance mode, middle mode, maximum mode ipr priority dtc activation dmac activation exdmeend0 140 h'0230 o ? exdmeend1 141 h'0234 o ? exdmeend2 142 h'0238 o ? exdmac exdmeend3 143 h'023c iprk10 to iprk8 o ? eri0 144 h'0240 ? ? rxi0 145 h'0244 o o txi0 146 h'0248 o o sci_0 tei0 147 h'024c iprk6 to iprk4 ? ? eri1 148 h'0250 ? ? rxi1 149 h'0254 o o txi1 150 h'0258 o o sci_1 tei1 151 h'025c iprk2 to iprk0 ? ? eri2 152 h'0260 ? ? rxi2 153 h'0264 o o txi2 154 h'0268 o o sci_2 tei2 155 h'026c iprl14 to iprl12 ? ? 156 h'0270 ? ? 157 h'0274 ? ? 158 h'0278 ? ? ? reserved for system use 159 h'027c ? ? ? eri4 160 h'0280 ? ? rxi4 161 h'0284 o o txi4 162 h'0288 o o sci_4 tei4 163 h'028c iprl6 to iprl4 ? ? tgi6a 164 h'0290 o o tgi6b 165 h'0294 o ? tgi6c 166 h'0298 o ? tgi6d 167 h'029c iprl2 to iprl0 high o ? tpu_6 tgi6v 168 h'02a0 iprm14 to iprm12 low ? ? section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 147 of 1340 rej09b0499-0200 vector address offset * 1 classification interrupt source vector number advance mode, middle mode, maximum mode ipr priority dtc activation dmac activation tgi7a 169 h'02a4 o o tgi7b 170 h'02a8 irpm10 to irpm8 o ? tgi7v 171 h'02ac ? ? tpu_7 tci7u 172 h'02b0 irpm6 to irpm4 ? ? tgi8a 173 h'02b4 o o tgi8b 174 h'02b8 irpm2 to irpm0 o ? tci8v 175 h'02bc ? ? tpu_8 tci8u 176 h'02c0 iprn14 to iprn12 ? ? tgi9a 177 h'02c4 o o tgi9b 178 h'02c8 o ? tgi9c 179 h'02cc o ? tgi9d 180 h'02d0 iprn10 to iprn8 o ? tpu_9 tci9v 181 h'02d4 iprn6 to iprn4 ? ? tgi10a 182 h'02d8 o o tgi10b 183 h'02dc iprn2 to iprn0 o ? reserved for system use 184 h'02e0 ? ? reserved for system use 185 h'02e4 ? ? ? tci10v 186 h'02e8 o ? tpu_10 tci10u 187 h'02ec ipro14 to ipro12 ? ? tgi11a 188 h'02f0 o o tgi11b 189 h'02f4 ipro10 to ipro8 o ? tci11v 190 h'02f8 ? ? tpu_11 tci11u 191 h'02fc ipro6 to ipro4 high ? ? ? reserved for system use 192 | 215 h'0300 | h'035c ? low ? | ? ? | ? section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 148 of 1340 rej09b0499-0200 vector address offset * 1 classification interrupt source vector number advanced mode, middle mode, maximum mode ipr priority dtc activation dmac activation iic2_0 iici0 216 h'0360 ? ? ? reserved for system use 217 h'0364 ? ? iic2_1 iici1 218 h'0368 ? ? ? reserved for system use 219 h'036c iprq6 to iprq4 ? ? rxi5 220 h'0370 ? o txi5 221 h'0374 ? o eri5 222 h'0378 ? ? sci_5 tei5 223 h'037c iprq2 to iprq0 ? ? rxi6 224 h'0380 ? o txi6 225 h'0384 ? o eri6 226 h'0388 ? ? sci_6 tei6 227 h'038c iprr14 to iprr12 ? ? tmr_4 cmia4 or cmib4 228 h'0390 ? ? tmr_5 cmia5 or cmib5 229 h'0394 ? ? tmr_6 cmia6 or cmib6 230 h'0398 ? ? tmr_7 cmia7 or cmib7 231 h'039c iprr10 to iprr8 ? ? usbintn0 232 h'03a0 ? o usbintn1 233 h'03a4 ? o usbintn2 234 h'03a8 ? ? usb usbintn3 235 h'03ac iprr6 to iprr4 ? ? ? reserved for system use 236 h'03b0 ? ? a/d_1 adi1 237 h'03b4 ? o usb resume 238 h'03b8 iprr2 to iprr0 high ? ? ? reserved for system use 239 | 255 h'03bc | h'03fc ? low ? | ? ? | ? notes: 1. lower 16 bits of the start addr ess in advanced, middle, and maximum modes. 2. supported only by the h8sx/1655m group. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 149 of 1340 rej09b0499-0200 7.6 interrupt control modes and interrupt operation the interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. interrupt operations differ depending on the interrupt control mode. the interrupt control mode is selected by intcr. table 7.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. table 7.3 interrupt control modes interrupt control mode priority setting register interrupt mask bit description 0 default i the priority levels of the interrupt sources are fixed default settings. the interrupts except for nmi is masked by the i bit. 2 ipr i2 to i0 eight priority leve ls can be set for interrupt sources except for nmi with ipr. 8-level interrupt mask control is performed by bits i2 to i0. 7.6.1 interrupt control mode 0 in interrupt control mode 0, interrupt requests except for nmi are masked by the i bit in ccr of the cpu. figure 7.3 shows a flowchart of th e interrupt acceptance oper ation in this case. 1. if an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. if the i bit in ccr is set to 1, nmi is accepted, and other interrupt requests are held pending. if the i bit is cleared to 0, an interrupt request is accepted. 3. for multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the cpu, and holds other interrupt requests pending. 4. when the cpu accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. the pc and ccr contents are saved to the st ack area during the inte rrupt exception handling. the pc contents saved on the stack is the addres s of the first instructio n to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this masks all interrupts except nmi. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 150 of 1340 rej09b0499-0200 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. program execution state interrupt generated? nmi irq0 irq1 tei4 i = 0 save pc and ccr i 1 read vector address branch to interrupt handling routine yes no yes yes yes no no no yes yes no pending figure 7.3 flowchart of proce dure up to interrupt acceptance in interrupt control mode 0 section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 151 of 1340 rej09b0499-0200 7.6.2 interrupt control mode 2 in interrupt control mode 2, interrupt requests except for nmi are ma sked by comparing the interrupt mask level (i2 to i0 bits) in exr of th e cpu and the ipr setting. there are eight levels in mask control. figure 7.4 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. for multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to the ipr setting, and holds other interrupt requests pending. if multiple interrupt requests have th e same priority, an interrupt re quest is selected according to the default setting shown in table 7.2. 3. next, the priority of the selected interrupt reque st is compared with the interrupt mask level set in exr. when the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt re quest with a priority over the interrupt mask level is accepted. 4. when the cpu accepts an interrupt request, it starts interrupt exce ption handling after execution of the current instru ction has been completed. 5. the pc, ccr, and exr contents are saved to the stack area during interrupt exception handling. the pc saved on the stack is the addres s of the first instruction to be executed after returning from the interrupt handling routine. 6. the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority of the accepted interrupt. if the accepted interrupt is nm i, the interrupt mask level is set to h'7. 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 152 of 1340 rej09b0499-0200 yes program execution state interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 7.4 flowchart of proce dure up to interrupt acceptance in interrupt control mode 2 section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 153 of 1340 rej09b0499-0200 7.6.3 interrupt exception handling sequence figure 7.5 shows the interrupt exception handlin g sequence. the example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on- chip memory. (12) (10) (6) (4) (2) (1) (5) (7) (9) (11) instruction prefetch interrupt acceptance interrupt level determination wait for end of instruction (3) (8) instruction prefetch in interrupt handling routine internal operation vector fetch stack internal operation interrupt request signal internal address bus internal read signal internal write signal internal data bus i (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp ? 2 sp ? 4 saved pc and saved ccr vector address start address of interrupt handling routine (vector address contents) start address of interrupt handling routine ((11) = (10)) first instruction of interrupt handling routine (6) (8) (9) (10) (11) (12) figure 7.5 interrupt exception handling section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 154 of 1340 rej09b0499-0200 7.6.4 interrupt response times table 7.4 shows interrupt response times ? the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the symbols for execution states used in table 7.4 ar e explained in table 7.5. this lsi is capable of fast word transfer to on -chip memory, so allocating the program area in on- chip rom and the stack ar ea in on-chip ram enable s high-speed processing. table 7.4 interrupt response times normal mode * 5 advanced mode maximum mode * 5 execution state interrupt control mode 0 interrupt control mode 2 interrupt control mode 0 interrupt control mode 2 interrupt control mode 0 interrupt control mode 2 interrupt priority determination * 1 3 number of states until executing instruction ends * 2 1 to 19 + 2s i pc, ccr, exr stacking s k to 2s k * 6 2s k s k to 2s k * 6 2s k 2s k 2s k vector fetch s h instruction fetch * 3 2s i internal processing * 4 2 total (using on-chip memory) 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31 notes: 1. two states for an internal interrupt. 2. in the case of the mulxs or divxs instruction 3. prefetch after interrupt acceptance or for an instruction in the inte rrupt handling routine. 4. internal operation after interru pt acceptance or after vector fetch 5. not available in this lsi. 6. when setting the sp value to 4n, the interrupt response time is s k ; when setting to 4n + 2, the interrupt response time is 2s k . section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 155 of 1340 rej09b0499-0200 table 7.5 number of execution stat es in interrupt handling routine object of access external device 8-bit bus 16-bit bus symbol on-chip memory 2-state access 3-state access 2-state access 3-state access vector fetch s h 1 8 12 + 4m 4 6 + 2m instruction fetch s i 1 4 6 + 2m 2 3 + m stack manipulation s k 1 8 12 + 4m 4 6 + 2m [legend] m: number of wait cycles in an external device access. 7.6.5 dtc and dmac activa tion by interrupt the dtc and dmac can be activated by an interr upt. in this case, th e following options are available: ? interrupt request to the cpu ? activation request to the dtc ? activation request to the dmac ? combination of the above for details on interrupt requests that can be us ed to activate the dtc an d dmac, see table 7.2, section 10, dma controller (dmac), and secti on 12, data transfer controller (dtc). figure 7.6 shows a block diagram of the dtc, dmac, and interrupt controller. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 156 of 1340 rej09b0499-0200 select signal dtcer dmrsr_0 to dmrsr_3 select signal irq interrupt on-chip peripheral module interrupt controller clear signal control signal dmac activation request signal clear signal dtc/cpu select circuit dmac select circuit dtc control circuit priority determination dtc dmac cpu interrupt request clear signal interrupt request interrupt request clear signal interrupt request clear signal interrupt request dtc activation request vector number cpu interrupt request vector number clear signal i, i2 to i0 figure 7.6 block diagram of dtc, dmac, and interrupt controller (1) selection of in terrupt sources the activation source for each dmac channel is selected by dmrsr. the selected activation source is input to the dmac through the select circuit. when transfer by an on-chip module interrupt is enabled (dtf1 = 1, dtf0 = 0, and dte = 1 in dmdr) and the dta bit in dmdr is set to 1, the interrupt source selected for the dm ac activation source is controlled by the dmac and cannot be used as a dtc activation source or cpu interrupt source. interrupt sources that are not controlled by the dmac are set for dtc activation sources or cpu interrupt sources by the dtce bit in dtcera to dtcerf of the dtc. specifying the disel bit in mrb of the dtc generates an interrupt request to the cpu by clearing the dtce bit to 0 after the individual dtc data transfer. note that when the dtc performs a predetermine d number of data transfers and the transfer counter indicates 0, an interrupt request is made to the cpu by clearing the dtce bit to 0 after the dtc data transfer. when the same interrupt source is set as both the dtc and dmac activation source and cpu interrupt source, the dtc and dmac must be given priority over the cpu. if the ipsete bit in cpupcr is set to 1, the priority is determined acc ording to the ipr settin g. therefore, the cpup setting or the ipr setting corresponding to the interrupt source must be set to lower than or equal to the dtcp and dmap setting. if the cpu is given priority over the dtc or dmac, the dtc or dmac may not be activated, and the data transfer may not be performed. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 157 of 1340 rej09b0499-0200 (2) priority determination the dtc activation source is select ed according to the default prio rity, and the selection is not affected by its mask level or priority level. for respective priority levels, see table 12.1, interrupt sources, dtc vector addresses, and corresponding dtces. (3) operation order if the same interrupt is selected as both the dtc activation sour ce and cpu interrupt source, the cpu interrupt exception handling is performed after th e dtc data transfer. if the same interrupt is selected as the dtc or dmac activation source or cpu interrupt source, respective operations are performed independently. table 7.6 lists the selection of interrupt sources and interrupt source clear control by setting the dta bit in dmdr of the dmac, the dtce bit in dtcera to dtcerf of the dtc, and the disel bit in mrb of the dtc. table 7.6 interrupt source se lection and clear control dmac setting dtc setting interrupt source selection/clear control dta dtce disel dmac dtc cpu 0 0 * o x 1 0 o x 1 o o 1 * * x x [legend] : the corresponding interrupt is used. the interrupt source is cleared. (the interrupt source flag must be cleared in the cpu interrupt handling routine.) o: the corresponding interrupt is used. the interrupt source is not cleared. x: the corresponding interrupt is not available. * : don't care. (4) usage note the interrupt sources of the sci, and a/d convert er are cleared according to the setting shown in table 7.6, when the dtc or dmac re ads/writes the prescribed register. to initiate multiple channels for the dtc with the same interrupt, the same priority (dtcp = dmap) should be assigned. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 158 of 1340 rej09b0499-0200 7.7 cpu priority control function over dtc, dmac, and exdmac the interrupt controller has a function to control the priority among the dtc, dmac, exdmac, and the cpu by assigning different priority le vels to the dtc, dmac, exdmac, and the cpu. since the priority level can automatically be assi gned to the cpu on an interrupt occurrence, it is possible to execute the cpu interrupt exception handling prior to the dtc, dmac, or exdmac transfer. the priority level of the cpu is assigned by b its cpup2 to cpup0 in cpupcr. the priority level of the dtc is assigned by bits dtcp2 to dtcp0 in cpupcr. the priority level of the dmac is assigned by bits dmap2 to dmap0 in dmdr for each channel. the priority level of the exdmac is assigned by bits edmap2 to edmap0 in the exdma mode control register (edmdr_0 to edmde_3) for each channel. the priority control function over the dtc and dmac is enabled by setting the cpupce bit in cpupcr to 1. when the cpupce bit is 1, the dtc, dmac, and exdmac activation sources are controlled according to the respective priority levels. the dtc activation source is controlled according to the priority level of the cpu indicated by bits cpup2 to cpup0 and the priority level of th e dtc indicated by bits dtcp2 to dtcp0. if the cpu has priority, the dtc activation source is he ld. the dtc is activated when the condition by which the activation source is held is cancelled (cpupce = 1 and value of bits cpup2 to cpup0 is greater than that of bits dtcp2 to dtcp0). th e priority level of the dtc is assigned by the dtcp2 to dtcp0 bits regardless of the activation source. for the dmac, the priority level can be specif ied for each channel. the dmac activation source is controlled according to the priority level of each dmac channel indicat ed by bits dmap2 to dmap0 and the priority level of the cpu. if the cpu has priority, the dmac activation source is held. the dmac is activated when the condition by which the activation source is held is cancelled (cpupce = 1 and value of bits cpup2 to cpup0 is greater than that of bits dmap2 to dmap0). if different priority levels are specified for channels, the channels of the higher priority levels continue transfer and the activation sources for the channels of lower priority levels than that of the cpu are held. for the exdmac, the priority level can be speci fied for each channel. the exdmac activation source is controlled according to the priority level of each exdmac channel indicated by bits edmap2 to edmap0 and the priority level of the cpu. if the cpu has priority, the exdmac activation source is held. the exdmac is activated when the condition by which the activation source is held is cancelled (cpupce = 1 and value of bits cpup2 to cpup0 is greater than that of bits dmap2 to edmap0). if different priority le vels are specified for channels, the channels of section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 159 of 1340 rej09b0499-0200 the higher priority levels continue transfer and the activation sources for the channels of lower priority levels than that of the cpu are held. there are two methods for assigning the priority level to the cpu by the ipsete bit in cpupcr. setting the ipsete bit to 1 enables a function to au tomatically assign the value of the interrupt mask bit of the cpu to the cpu pr iority level. clearing the ipsete bit to 0 disables the function to automatically assign the priority level. theref ore, the priority level is assigned directly by software rewriting bits cpup2 to cpup0. even if the ipsete bit is 1, the priority level of the cpu is software assignable by rewriting the interrup t mask bit of the cpu (i bit in ccr or i2 to i0 bits in exr). the priority level that is automa tically assigned when the ipsete bit is 1 differs according to the interrupt control mode. in interrupt control mode 0, the i bit in ccr of the cpu is reflected in bit cpup2. bits cpup1 and cpup0 are fixed 0. in interrupt control mode 2, the values of bits i2 to i0 in exr of the cpu are reflected in bits cpup2 to cpup0. table 7.7 shows the cpu priority control. table 7.7 cpu priority control control status interrupt control mode interrupt priority interrupt mask bit ipsete in cpupcr cpup2 to cpup0 updating of cpup2 to cpup0 0 default i = any 0 b'111 to b'000 enabled i = 0 1 b'000 disabled i = 1 b'100 2 ipr setting i2 to i0 0 b'111 to b'000 enabled 1 i2 to i0 disabled section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 160 of 1340 rej09b0499-0200 table 7.8 shows a setting example of the priority control function over the dtc, dmac, and exdmac, and the transfer request control state. a priority level can be independently set to each channel of dmac and exdmac, but the table on ly shows one channel fo r example. transfers through the dmac and exdmac channels can be separately controlled by assigning different priority levels for channels. table 7.8 example of priority contro l function setting and control state transfer request control state interrupt control mode cpupce in cpupce cpup2 to cpup0 dtcp2 to dtcp0 dmap2 to dmap0 edmap2 to edmap0 dtc dmac exdmac 0 0 any any any any enabled enabled enabled 1 b'000 b'000 b'000 b'000 e nabled enabled enabled b'100 b'000 b'000 b'000 masked masked masked b'100 b'000 b'011 b'100 masked masked enabled b'100 b'111 b'101 b'000 e nabled enabled masked b'000 b'111 b'101 b'000 e nabled enabled enabled 2 0 any any any any enabled enabled enabled 1 b'000 b'000 b'000 b'000 e nabled enabled enabled b'000 b'011 b'101 b'110 e nabled enabled enabled b'011 b'011 b'101 b'110 e nabled enabled enabled b'100 b'011 b'101 b'110 ma sked enabled enabled b'101 b'011 b'101 b'110 ma sked enabled enabled b'110 b'011 b'101 b'110 masked masked enabled b'111 b'011 b'101 b'110 masked masked masked b'101 b'011 b'101 b'011 masked enabled masked b'101 b'110 b'101 b'011 e nabled enabled masked section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 161 of 1340 rej09b0499-0200 7.8 usage notes 7.8.1 conflict between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 7.7 shows an example in which the tciev bit in tier of the tpu is cleared to 0. the above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. internal address bus internal write signal p tciev tcfv tciv interrupt signal tier_0 write cycle by cpu tciv exception handling tier_0 address figure 7.7 conflict between int errupt generation and disabling similarly, when an interrupt is requested immediately before the dtc enable bit is changed to activate the dtc, dtc activation and the interrupt exception handling by the cpu are both executed. when changing the dtc enable bit, ma ke sure that an interrupt is not requested. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 162 of 1340 rej09b0499-0200 7.8.2 instructions that disable interrupts instructions that disable interrupts immediat ely after execution are ldc, andc, orc, and xorc. after any of these instructions is execut ed, all interrupts including nmi are disabled and the next instruction is always ex ecuted. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 7.8.3 times when interrupts are disabled there are times when interru pt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt accep tance for a 3-state period after the cpu has updated the mask level with an ldc, andc, o rc, or xorc instruction, and for a period of writing to the registers of the interrupt controller. 7.8.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b and the eepmov.w instructions. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the tr ansfer is completed. with the eepmov.w instruction, if an interrupt re quest is issued during the transfer, interrupt exception handling starts at the end of the individu al transfer cycle. the pc value saved on the stack in this case is the address of the next inst ruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 7.8.5 interrupts during execution of movmd and movsd instructions with the movmd or movsd instruction, if an in terrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. the pc value saved on the stack in this case is the address of the movmd or movsd in struction. the transfer of the remaining data is resumed after returning from the interrupt handling routine. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 163 of 1340 rej09b0499-0200 7.8.6 interrupts of p eripheral modules to clear an interrupt source flag by the cpu using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. this makes the request signal synchronized with the peripheral modu le clock. for details, refer to section 26.5.1, notes on clock pulse generator. section 7 interrupt controller rev. 2.00 oct. 20, 2009 page 164 of 1340 rej09b0499-0200 section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 165 of 1340 rej09b0499-0200 section 8 user break controller (ubc) the user break controller (ubc) generates a ubc break interrupt request each time the state of the program counter matches a specified break condition. the ubc break interrupt is a non- maskable interrupt and is always accepted, regardle ss of the interrupt contro l mode and the state of the interrupt mask bit of the cpu. for each channel, the break control register (brcr) and break address register (bar) are used to specify the break condition as a combination of address bits and type of bus cycle. four break conditions are independently specifiable on four channels, a to d. 8.1 features ? number of break channels: four (channels a, b, c, and d) ? break comparison cond itions (each channel) ? address ? bus master (cpu cycle) ? bus cycle (instruction execution (pc break)) ? ubc break interrupt exception handling is executed immediately before execution of the instruction fetched from the specified address (pc break). ? module stop state can be set section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 166 of 1340 rej09b0499-0200 8.2 block diagram a ch pc condition match b ch pc condition match c ch pc condition match d ch pc condition match ubc break interrupt request break control mode control sequential control break address break control instruction execution pointer cpu status internal bus (input side) internal bus (output side) instruction execution pointer barah baral barbh barbl barch barcl bardh bardl brcra brcrb brcrc brcrd pc break control address comparator a ch condition match determination condition match determination condition match determination condition match determination address comparator b ch address comparator c ch address comparator d ch flag set control figure 8.1 block diagram of ubc section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 167 of 1340 rej09b0499-0200 8.3 register descriptions table 8.1 lists the register configuration of the ubc. table 8.1 register configuration register name abbreviation r/w initial value address access size barah r/w h'0000 h'ffa00 16 break address register a baral r/w h'0000 h'ffa02 16 bamrah r/w h'0000 h'ffa04 16 break address mask register a bamral r/w h'0000 h'ffa06 16 barbh r/w h'0000 h'ffa08 16 break address register b barbl r/w h'0000 h'ffa0a 16 bamrbh r/w h'0000 h'ffa0c 16 break address mask register b bamrbl r/w h'0000 h'ffa0e 16 barch r/w h'0000 h'ffa10 16 break address register c barcl r/w h'0000 h'ffa12 16 bamrch r/w h'0000 h'ffa14 16 break address mask register c bamrcl r/w h'0000 h'ffa16 16 bardh r/w h'0000 h'ffa18 16 break address register d bardl r/w h'0000 h'ffa1a 16 bamrdh r/w h'0000 h'ffa1c 16 break address mask register d bamrdl r/w h'0000 h'ffa1e 16 break control register a brcra r/w h'0000 h'ffa28 8/16 break control register b b rcrb r/w h'0000 h'ffa2c 8/16 break control register c brcrc r/w h'0000 h'ffa30 8/16 break control register d brcrd r/w h'0000 h'ffa34 8/16 section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 168 of 1340 rej09b0499-0200 8.3.1 break address register n (bara, barb, barc, bard) each break address register n (barn) consists of break address register nh (barnh) and break address register nl (barnl). together, barnh and barnl specify the address used as a break condition on channel n of the ubc. bit: initial value: r/w: bit: initial value: r/w: 31 barn31 0 r/w 30 barn30 0 r/w 29 barn29 0 r/w 28 barn28 0 r/w 27 barn27 0 r/w 24 barn24 0 r/w 26 barn26 0 r/w 25 barn25 0 r/w 23 barn23 0 r/w 22 barn22 0 r/w 21 barn21 0 r/w 20 barn20 0 r/w 19 barn19 0 r/w 16 barn16 0 r/w 18 barn18 0 r/w 17 barn17 0 r/w 15 barn15 0 r/w 14 barn14 0 r/w 13 barn13 0 r/w 12 barn12 0 r/w 11 barn11 0 r/w 8 barn8 0 r/w 10 barn10 0 r/w 9 barn9 0 r/w 7 barn7 0 r/w 6 barn6 0 r/w 5 barn5 0 r/w 4 barn4 0 r/w 3 barn3 0 r/w 0 barn0 0 r/w 2 barn2 0 r/w 1 barn1 0 r/w barnh barnl ? barnh bit bit name initial value r/w description 31 to 16 barn31 to barn16 all 0 r/w break address n31 to 16 these bits hold the upper bit values (bits 31 to 16) for the address break-condition on channel n. [legend] n = channels a to d ? barnl bit bit name initial value r/w description 15 to 0 barn15 to barn0 all 0 r/w break address n15 to 0 these bits hold the lower bit values (bits 15 to 0) for the address break-condition on channel n. [legend] n = channels a to d section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 169 of 1340 rej09b0499-0200 8.3.2 break address mask re gister n (bamra, bamrb, bamrc, bamrd) be sure to write h'ff00 0000 to break address mask register n (bamrn). operation is not guaranteed if another value is written here. bit: initial value: r/w: bit: initial value: r/w: 31 bamrn31 0 r/w 30 bamrn30 0 r/w 29 bamrn29 0 r/w 28 bamrn28 0 r/w 27 bamrn27 0 r/w 24 bamrn24 0 r/w 26 bamrn26 0 r/w 25 bamrn25 0 r/w 23 bamrn23 0 r/w 22 bamrn22 0 r/w 21 bamrn21 0 r/w 20 bamrn20 0 r/w 19 bamrn19 0 r/w 16 bamrn16 0 r/w 18 bamrn18 0 r/w 17 bamrn17 0 r/w 15 bamrn15 0 r/w 14 bamrn14 0 r/w 13 bamrn13 0 r/w 12 bamrn12 0 r/w 11 bamrn11 0 r/w 8 bamrn8 0 r/w 10 bamrn10 0 r/w 9 bamrn9 0 r/w 7 bamrn7 0 r/w 6 bamrn6 0 r/w 5 bamrn5 0 r/w 4 bamrn4 0 r/w 3 bamrn3 0 r/w 0 bamrn0 0 r/w 2 bamrn2 0 r/w 1 bamrn1 0 r/w bamrnh bamrnl ? bamrnh bit bit name initial value r/w description 31 to 16 bamrn31 to bamrn16 all 0 r/w break address mask n31 to 16 be sure to write h'ff00 here before setting a break condition in the break control register. [legend] n = channels a to d ? bamrnl bit bit name initial value r/w description 15 to 0 bamrn15 to bamrn0 all 0 r/w break address mask n15 to 0 be sure to write h'0000 here before setting a break condition in the break control register. [legend] n = channels a to d section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 170 of 1340 rej09b0499-0200 8.3.3 break control register n (brcra, brcrb, brcrc, brcrd) brcra, brcrb, brcrc, and brcrd are used to specify and control conditions for channels a, b, c, and d of the ubc. bit: initial value: r/w: [legend] n = channels a to d 15 ? 0 r/w 14 ? 0 r/w 13 cmfcpn 0 r/w 12 ? 0 r/w 11 cpn2 0 r/w 8 ? 0 r/w 10 cpn1 0 r/w 9 cpn0 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 idn1 0 r/w 4 idn0 0 r/w 3 rwn1 0 r/w 0 ? 0 r/w 2 rwn0 0 r/w 1 ? 0 r/w bit bit name initial value r/w description 15 14 ? ? 0 0 r/w r/w reserved these bits are always read as 0. the write value should always be 0. 13 cmfcpn 0 r/w condition match cpu flag ubc break source flag that indicates satisfaction of a specified cpu bus cycle condition. 0: the cpu cycle condition for channel n break requests has not been satisfied. 1: the cpu cycle condition for channel n break requests has been satisfied. 12 ? 0 r/w reserved these bits are always read as 0. the write value should always be 0. 11 10 9 cpn2 cpn1 cpn0 0 0 0 r/w r/w r/w cpu cycle select these bits select cpu cycl es as the bus cycle break condition for the given channel. 000: break requests will not be generated. 001: the bus cycle break condition is cpu cycles. 01x: setting prohibited 1xx: setting prohibited 8 7 6 ? ? ? 0 0 0 r/w r/w r/w reserved these bits are always read as 0. the write value should always be 0. section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 171 of 1340 rej09b0499-0200 bit bit name initial value r/w description 5 4 idn1 idn0 0 0 r/w r/w break condition select these bits select the pc break as the source of ubc break interrupt requests for the given channel. 00: break requests will not be generated. 01: ubc break condition is the pc break. 1x: setting prohibited 3 2 rwn1 rwn0 0 0 r/w r/w read select these bits select read cycles as the bus cycle break condition for the given channel. 00: break requests will not be generated. 01: the bus cycle break condition is read cycles. 1x: setting prohibited 1 0 ? ? 0 0 r/w r/w reserved these bits are always read as 0. the write value should always be 0. [legend] n = channels a to d section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 172 of 1340 rej09b0499-0200 8.4 operation the ubc does not detect condition matches in standby states (sleep mode, all module clock stop mode, software standby mode, deep software standby, and hardware standby mode). 8.4.1 setting of break control conditions 1. the address condition for the break is set in break address register n (barn). a mask for the address is set in break address mask register n (bamrn). 2. the bus and break conditions are set in br eak control register n (brcrn). bus conditions consist of cpu cycle, pc break, and reading. condition comparison is not performed when the cpu cycle setting is cpn = b'000, the pc break setting is idn = b'00, or the read setting is rwn = b'00. 3. the condition match cpu flag (cmfcpn) is set in the event of a break condition match on the corresponding channel. these flags are set wh en the break condition matches but are not cleared when it no long er does. to confirm setting of the sa me flag again, read the flag once from the break interrupt handling routine, and then write 0 to it (the flag is cleared by writing 0 to it after reading it as 1). [legend] n = channels a to d 8.4.2 pc break 1. when specifying a pc break, speci fy the address as the first addres s of the required instruction. if the address for a pc break condition is not the first address of an instruction, a break will never be generated. 2. the break occurs after fetching and execution of the target instruction have been confirmed. in cases of contention between a break before instruction execution and a user maskable interrupt, priority is given to the break before instruction execution. 3. a break will not be generated even if a break be fore instruction execution is set in a delay slot. 4. the pc break condition is generated by specif ying cpu cycles as the bus condition in break control register n (brcrn.cpn0 = 1), pc break as the break condition (idn0 = 1), and read cycles as the bus-cycle condition (rwn0 = 1). [legend] n = channels a to d section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 173 of 1340 rej09b0499-0200 8.4.3 condition match flag condition match flags are set when the break conditions match. the condition match flags of the ubc are listed in table 8.2. table 8.2 list of condition match flags register flag bit source brcra cmfcpa (bit 13) indicates that t he condition matches in the cpu cycle for channel a brcrb cmfcpb (bit 13) indicates that t he condition matches in the cpu cycle for channel b brcrc cmfcpc (bit 13) indicates that t he condition matches in the cpu cycle for channel c brcrd cmfcpd (bit 13) indicates that t he condition matches in the cpu cycle for channel d section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 174 of 1340 rej09b0499-0200 8.5 usage notes 1. pc break usage note ? contention between a s leep instruction (to place the chip in the sleep state or on software standby) and pc break if a break before a pc break instruction is se t for the instruction after a sleep instruction and the sleep instruction is executed with the ssby bit cleared to 0, break interrupt exception handling is executed without sleep mode being entered. in this case, the instruction after the sleep instruction is executed after the rte instruction. when the ssby bit is set to 1, break inte rrupt exception handling is executed after the oscillation settling time has elapsed subsequent to the transition to software standby mode. when an interrupt is the canceling source, interrupt exception handling is executed after the rte instruction, and the instruction following the sleep instruction is then executed. sleep break interr upt exception handling interr upt exception handling software standby (pc break source ) (cancelling source ) cancelling source clk figure 8.2 contention between sleep inst ruction (software standby) and pc break 2. prohibition on setting of pc break ? setting of a ubc break interrupt for program within the ubc break interrupt handling routine is prohibited. 3. the procedure for clearing a ubc flag bit (condition match flag) is shown below. a flag bit is cleared by writing 0 to it after reading it as 1. as the register that cont ains the flag bits is accessible in byte units, bit manipulation instructions can be used. section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 175 of 1340 rej09b0499-0200 cks register read the value read as 1 is retained register write flag bit flag bit is set to 1 flag bit is cleared to 0 figure 8.3 flag bit clearing sequence (condition match flag) 4. after setting break conditions for the ubc, an unexpected ubc break interrupt may occur after the execution of an illegal instruction. this depends on the value of the program counter and the internal bus cycle. section 8 user break controller (ubc) rev. 2.00 oct. 20, 2009 page 176 of 1340 rej09b0499-0200 section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 177 of 1340 rej09b0499-0200 section 9 bus controller (bsc) this lsi has an on-chip bus controller (bsc) that manages the external address space divided into eight areas. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters; cpu, dmac, exdmac, and dtc. 9.1 features ? manages external addre ss space in area units manages the external address space divided into eight areas chip select signals ( cs0 to cs7 ) can be output for each area bus specifications can be set independently for each area 8-bit access or 16-bit access can be selected for each area burst rom, byte control sram, or address/data multiplexed i/o interface can be set an endian conversion function is provid ed to connect a device of little endian ? basic bus interface this interface can be connect ed to the sram and rom 2-state access or 3-state access can be selected for each area program wait cycles can be inserted for each area wait cycles can be inserted by the wait pin. extension cycles can be inserted while csn is asserted for each area (n = 0 to 7) the negation timing of the read strobe signal ( rd ) can be modified ? byte control sram interface byte control sram interface can be set for areas 0 to 7 the sram that has a byte control pin can be directly connected ? burst rom interface burst rom interface can be set for areas 0 and 1 burst rom interface parameters can be set independently for areas 0 and 1 ? address/data multiplexed i/o interface address/data multiplexed i/o interf ace can be set for areas 3 to 7 section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 178 of 1340 rej09b0499-0200 ? idle cycle insertion idle cycles can be inserted between ex ternal read accesses to different areas idle cycles can be inserted before the exte rnal write access after an external read access idle cycles can be inserted before the exte rnal read access after an external write access idle cycles can be inserted before the exte rnal access after a dmac/exdmac single address transfer (w rite access) ? write buffer function external write cycles an d internal accesses can be executed in parallel write accesses to the on-chip pe ripheral module and on-chip memory accesses can be executed in parallel dmac single address transf ers and internal accesses can be executed in parallel ? external bus release function ? bus arbitration function includes a bus arbiter that arbitrates bus mastership among the cpu, dmac, exdmac, dtc, and external bus master ? exdmac transfers to the external buses and in ternal accesses can be executed in parallel ? multi-clock function the internal peripheral functions can be operated in synchronization with the peripheral module clock (p ). accesses to the external address sp ace can be operated in synchronization with the external bus clock (b ). ? the bus start ( bs ) and read/write (rd/ wr ) signals can be output. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 179 of 1340 rej09b0499-0200 a block diagram of the bus controller is shown in figure 9.1. address selector area decoder internal bus control unit internal data bus [legend] internal bus control signals external bus control unit external bus arbiter internal bus arbiter cpu address bus cs7 to cs0 wait breq back breqo dtc address bus dmac address bus cpu bus mastership acknowledge signal dtc bus mastership acknowledge signal cpu bus mastership request signal dtc bus mastership request signal dmac bus mastership acknowledge signal dmac bus mastership request signal external bus control signals control register abwcr astcr wtcra wtcrb rdncr csacr idlcr bcr1 bcr2 endiancr sramcr bromcr mpxcr abwcr: astcr: wtcra: wtcrb: rdncr: csacr: idlcd: bus width control register access state control register wait control register a wait control register b read strobe timing control register cs assertion period control register idle control register bcr1: bcr2: endiancr: sramcr: bromcr: mpxcr: bus control register 1 bus control register 2 endian control register sram mode control register burst rom interface control register address/data multiplexed i/o control register exdmac address bus exdmac bus mastership acknowledge signal exdmac bus mastership request signal figure 9.1 block diagram of bus controller section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 180 of 1340 rej09b0499-0200 9.2 register descriptions the bus controller has the following registers. ? bus width control register (abwcr) ? access state control register (astcr) ? wait control register a (wtcra) ? wait control register b (wtcrb) ? read strobe timing control register (rdncr) ? cs assertion period control register (csacr) ? idle control register (idlcr) ? bus control register 1 (bcr1) ? bus control register 2 (bcr2) ? endian control register (endiancr) ? sram mode control register (sramcr) ? burst rom interface contro l register (bromcr) ? address/data multiplexed i/o control register (mpxcr) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 181 of 1340 rej09b0499-0200 9.2.1 bus width control register (abwcr) abwcr specifies the data bus width for each area in the external address space. bit bit name initial value r/w 15 abwh7 1 r/w 14 abwh6 1 r/w 13 abwh5 1 r/w 12 abwh4 1 r/w 11 abwh3 1 r/w 10 abwh2 1 r/w 9 abwh1 1 r/w 8 abwh0 1/0 r/w bit bit name initial value r/w note: * initial value at 16-bit bus initiation is h'feff, and that at 8-bit bus initiation is h'ffff. 7 abwl7 1 r/w 6 abwl6 1 r/w 5 abwl5 1 r/w 4 abwl4 1 r/w 3 abwl3 1 r/w 2 abwl2 1 r/w 1 abwl1 1 r/w 0 abwl0 1 r/w bit bit name initial value * 1 r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 abwh7 abwh6 abwh5 abwh4 abwh3 abwh2 abwh1 abwl0 abwl7 abwl6 abwl5 abwl4 abwl3 abwl2 abwl1 abwl0 1 1 1 1 1 1 1 1/0 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w area 7 to 0 bus width control these bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. abwhn abwln (n = 7 to 0) 0: setting prohibited 0 1: area n is designated as 16-bit access space 1 1: area n is designated as 8-bit access space * 2 [legend] : don't care notes: 1. initial value at 16-bit bus initiation is h'feff, and that at 8-bit bus initiation is h'ffff. 2. an address space specified as byte contro l sram interface must not be specified as 8- bit access space. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 182 of 1340 rej09b0499-0200 9.2.2 access state control register (astcr) astcr designates each area in the external addres s space as either 2-st ate access space or 3-state access space and enables/disabl es wait cycle insertion. bit bit name initial value r/w 15 ast7 1 r/w 14 ast6 1 r/w 13 ast5 1 r/w 12 ast4 1 r/w 11 ast3 1 r/w 10 ast2 1 r/w 9 ast1 1 r/w 8 ast0 1 r/w bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 15 14 13 12 11 10 9 8 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w area 7 to 0 access state control these bits select whether the corresponding area is to be designated as 2-state acce ss space or 3-state access space. wait cycle insertion is enabled or disabled at the same time. 0: area n is designated as 2-state access space wait cycle insertion in area n access is disabled 1: area n is designated as 3-state access space wait cycle insertion in area n access is enabled (n = 7 to 0) 7 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 183 of 1340 rej09b0499-0200 9.2.3 wait control registers a and b (wtcra, wtcrb) wtcra and wtcrb select the number of program wait cycles for each area in the external address space. bit bit name initial value r/w 15 ? 0 r ? wtcra ? wtcrb 14 w72 1 r/w 13 w71 1 r/w 12 w70 1 r/w 11 ? 0 r 10 w62 1 r/w 9 w61 1 r/w 8 w60 1 r/w bit bit name initial value r/w 7 ? 0 r 6 w52 1 r/w 5 w51 1 r/w 4 w50 1 r/w 3 ? 0 r 2 w42 1 r/w 1 w41 1 r/w 0 w40 1 r/w bit bit name initial value r/w 15 ? 0 r 14 w32 1 r/w 13 w31 1 r/w 12 w30 1 r/w 11 ? 0 r 10 w22 1 r/w 9 w21 1 r/w 8 w20 1 r/w bit bit name initial value r/w 7 ? 0 r 6 w12 1 r/w 5 w11 1 r/w 4 w10 1 r/w 3 ? 0 r 2 w02 1 r/w 1 w01 1 r/w 0 w00 1 r/w section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 184 of 1340 rej09b0499-0200 ? wtcra bit bit name initial value r/w description 15 ? 0 r reserved this is a read-only bit and cannot be modified. 14 13 12 w72 w71 w70 1 1 1 r/w r/w r/w area 7 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 7 while bit ast7 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 ? 0 r reserved this is a read-only bit and cannot be modified. 10 9 8 w62 w61 w60 1 1 1 r/w r/w r/w area 6 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 6 while bit ast6 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 ? 0 r reserved this is a read-only bit and cannot be modified. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 185 of 1340 rej09b0499-0200 bit bit name initial value r/w description 6 5 4 w52 w51 w50 1 1 1 r/w r/w r/w area 5 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 5 while bit ast5 in astcr is 1. 000: program cycle wait not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3 ? 0 r reserved this is a read-only bit and cannot be modified. 2 1 0 w42 w41 w40 1 1 1 r/w r/w r/w area 4 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 4 while bit ast4 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 186 of 1340 rej09b0499-0200 ? wtcrb bit bit name initial value r/w description 15 ? 0 r reserved this is a read-only bit and cannot be modified. 14 13 12 w32 w31 w30 1 1 1 r/w r/w r/w area 3 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 3 while bit ast3 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 ? 0 r reserved this is a read-only bit and cannot be modified. 10 9 8 w22 w21 w20 1 1 1 r/w r/w r/w area 2 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 2 while bit ast2 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 ? 0 r reserved this is a read-only bit and cannot be modified. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 187 of 1340 rej09b0499-0200 bit bit name initial value r/w description 6 5 4 w12 w11 w10 1 1 1 r/w r/w r/w area 1 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 1 while bit ast1 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3 ? 0 r reserved this is a read-only bit and cannot be modified. 2 1 0 w02 w01 w00 1 1 1 r/w r/w r/w area 0 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 0 while bit ast0 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 188 of 1340 rej09b0499-0200 9.2.4 read strobe timing control register (rdncr) rdncr selects the negation timing of the read strobe signal ( rd ) when reading the external address spaces specified as a ba sic bus interface or the address/ data multiplexed i/o interface. bit bit name initial value r/w 15 rdn7 0 r/w 14 rdn6 0 r/w 13 rdn5 0 r/w 12 rdn4 0 r/w 11 rdn3 0 r/w 10 rdn2 0 r/w 9 rdn1 0 r/w 8 rdn0 0 r/w bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 15 14 13 12 11 10 9 8 rdn7 rdn6 rdn5 rdn4 rdn3 rdn2 rdn1 rdn0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w read strobe timing control rdn7 to rdn0 set the negation timing of the read strobe in a corresponding area read access. as shown in figure 9.2, the read strobe for an area for which the rdnn bit is set to 1 is negated one half- cycle earlier than that for an area for which the rdnn bit is cleared to 0. the read data setup and hold time are also given one half-cycle earlier. 0: in an area n read access, the rd signal is negated at the end of the read cycle 1: in an area n read access, the rd signal is negated one half-cycle before t he end of the read cycle (n = 7 to 0) 7 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. notes: 1. in an external address space which is specified as byte control sram interface, the rdncr setting is ignored and the same operation when rdnn = 1 is performed. 2. in an external address space which is specified as burst rom interface, the rdncr setting is ignored during read accesses by the cpu and exdmac cluster transfer, and the same operation when rdnn = 0 is performed. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 189 of 1340 rej09b0499-0200 bus cycle t 1 t 2 rd b data rd data rdnn = 0 rdnn = 1 t 3 (n = 7 to 0) figure 9.2 read strobe negation timing (example of 3-state access space) 9.2.5 cs assertion period control registers (csacr) csacr selects whether or not the asserti on periods of the chip select signals ( csn ) and address signals for the basic bus, byte-control sram, burst rom, and address/data multiplexed i/o interface are to be extended. extend ing the assertion period of the csn and address signals allows the setup time and hold time of read strobe ( rd ) and write strobe ( lhwr / llwr ) to be assured and to make the write data setup time and hol d time for the write strobe become flexible. bit bit name initial value r/w 15 csxh7 0 r/w 14 csxh6 0 r/w 13 csxh5 0 r/w 12 csxh4 0 r/w 11 csxh3 0 r/w 10 csxh2 0 r/w 9 csxh1 0 r/w 8 csxh0 0 r/w bit bit name initial value r/w 7 csxt7 0 r/w 6 csxt6 0 r/w 5 csxt5 0 r/w 4 csxt4 0 r/w 3 csxt3 0 r/w 2 csxt2 0 r/w 1 csxt1 0 r/w 0 csxt0 0 r/w section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 190 of 1340 rej09b0499-0200 bit bit name initial value r/w description 15 14 13 12 11 10 9 8 csxh7 csxh6 csxh5 csxh4 csxh3 csxh2 csxh1 csxh0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w cs and address signal assertion period control 1 these bits specify whether or not the th cycle is to be inserted (see figure 9.3). when an area for which bit csxhn is set to 1 is accessed, one th cycle, in which the csn and address signals are asserted, is inserted before the normal access cycle. 0: in access to area n, the csn and address assertion period (th) is not extended 1: in access to area n, the csn and address assertion period (th) is extended (n = 7 to 0) 7 6 5 4 3 2 1 0 csxt7 csxt6 csxt5 csxt4 csxt3 csxt2 csxt1 csxt0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w cs and address signal assertion period control 2 these bits specify whether or not the tt cycle is to be inserted (see figure 9.3). when an area for which bit csxtn is set to 1 is accessed, one tt cycle, in which the csn and address signals are retained, is inserted after the normal access cycle. 0: in access to area n, the csn and address assertion period (tt) is not extended 1: in access to area n, the csn and address assertion period (tt) is extended (n = 7 to 0) note: * in burst rom interface, the csxtn settings are ignored during read accesses by the cpu and exdmac cluster transfer section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 191 of 1340 rej09b0499-0200 read data write data bus cycle t h t 1 t 2 t 3 t t b address csn as bs rd/ wr rd read write data bus data bus lhwr , llwr figure 9.3 cs and address assertio n period extension (example of basic bus interface, 3-state access space, and rdnn = 0) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 192 of 1340 rej09b0499-0200 9.2.6 idle control register (idlcr) idlcr specifies the idle cycle insertion c onditions and the number of idle cycles. bit bit name initial value r/w 15 idls3 1 r/w 14 idls2 1 r/w 13 idls1 1 r/w 12 idls0 1 r/w 11 idlcb1 1 r/w 10 idlcb0 1 r/w 9 idlca1 1 r/w 8 idlca0 1 r/w bit bit name initial value r/w 7 idlsel7 0 r/w 6 idlsel6 0 r/w 5 idlsel5 0 r/w 4 idlsel4 0 r/w 3 idlsel3 0 r/w 2 idlsel2 0 r/w 1 idlsel1 0 r/w 0 idlsel0 0 r/w bit bit name initial value r/w description 15 idls3 1 r/w idle cycle insertion 3 inserts an idle cycle between the bus cycles when the dmac/exdmac single address transfer (write cycle) is followed by external access. 0: no idle cycle is inserted 1: an idle cycle is inserted 14 idls2 1 r/w idle cycle insertion 2 inserts an idle cycle between the bus cycles when the external write cycle is followed by external read cycle. 0: no idle cycle is inserted 1: an idle cycle is inserted 13 idls1 1 r/w idle cycle insertion 1 inserts an idle cycle between the bus cycles when the external read cycles of different areas continue. 0: no idle cycle is inserted 1: an idle cycle is inserted section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 193 of 1340 rej09b0499-0200 bit bit name initial value r/w description 12 idls0 1 r/w idle cycle insertion 0 inserts an idle cycle between the bus cycles when the external read cycle is followed by external write cycle. 0: no idle cycle is inserted 1: an idle cycle is inserted 11 10 idlcb1 idlcb0 1 1 r/w r/w idle cycle state number select b specifies the number of idle cycles to be inserted for the idle condition specified by idls1 and idls0. 00: no idle cycle is inserted 01: 2 idle cycles are inserted 00: 3 idle cycles are inserted 01: 4 idle cycles are inserted 9 8 idlca1 idlca0 1 1 r/w r/w idle cycle state number select a specifies the number of idle cycles to be inserted for the idle condition specified by idls3 to idls0. 00: 1 idle cycle is inserted 01: 2 idle cycles are inserted 10: 3 idle cycles are inserted 11: 4 idle cycles are inserted 7 6 5 4 3 2 1 0 idlsel7 idlsel6 idlsel5 idlsel4 idlsel3 idlsel2 idlsel1 idlsel0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w idle cycle number select specifies the number of idle cycles to be inserted for each area for the idle insert ion condition specified by idls1 and idls0. 0: number of idle cycles to be inserted for area n is specified by idlca1 and idlca0. 1: number of idle cycles to be inserted for area n is specified by idlcb1 and idlcb0. (n = 7 to 0) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 194 of 1340 rej09b0499-0200 9.2.7 bus control register 1 (bcr1) bcr1 is used for selection of the external bus released state protocol, enabling/disabling of the write data buffer function, and enabling/disabling of the wait pin input. bit bit name initial value r/w 15 brle 0 r/w 14 breqoe 0 r/w 13 ? 0 r 12 ? 0 r 11 ? 0 r/w 10 ? 0 r/w 9 wdbe 0 r/w 8 waite 0 r/w bit bit name initial value r/w 7 dkc 0 r/w 6 edkc 0 r/w 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 15 brle 0 r/w external bus release enable enables/disables external bus release. 0: external bus release disabled breq , back , and breqo pins can be used as i/o ports 1: external bus release enabled * for details, see section 13, i/o ports. 14 breqoe 0 r/w breqo pin enable controls outputting the bus request signal ( breqo ) to the external bus master in the external bus released state when an internal bus master performs an external address space access. 0: breqo output disabled breqo pin can be used as i/o port 1: breqo output enabled section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 195 of 1340 rej09b0499-0200 bit bit name initial value r/w description 13, 12 ? all 0 r reserved these are read-only bits and cannot be modified. 11, 10 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 9 wdbe 0 r/w write data buffer enable the write data buffer function can be used for an external write cycle and a dmac single address transfer cycle. the changed setting may not affect an external access immediately after the change. 0: write data buffer function not used 1: write data buffer function used 8 waite 0 r/w wait pin enable selects enabling/disabling of wait input by the wait pin. 0: wait input by wait pin disabled wait pin can be used as i/o port 1: wait input by wait pin enabled for details, see section 13, i/o ports. 7 dkc 0 r/w dack control selects the timing of dmac transfer acknowledge signal assertion. 0: dack signal is asserted at the b falling edge 1: dack signal is asserted at the b rising edge 6 edkc 0 r/w edack control selects the timing of exdmac transfer acknowledge signal assertion. 0: edack signal is asserted at the b falling edge 1: edack signal is asserted at the b rising edge 5 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. note: when external bus release is enabled or input by the wait pin is enabled, make sure to set the icr bit to 1. for details , see section 13, i/o ports. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 196 of 1340 rej09b0499-0200 9.2.8 bus control register 2 (bcr2) bcr2 is used for bus arbitration control of the cpu, dmac, exdmac, and dtc, and enabling/disabling of the write data buffer function to the peripheral modules. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ebccs 0 r/w 4 ibccs 0 r/w 3 ? 0 r 2 ? 0 r 1 ? 1 r/w 0 pwdbe 0 r/w bit bit name initial value r/w description 7, 6 ? all 0 r reserved these are read-only bits and cannot be modified. 5 ebccs 0 r/w external bus cycle control select selects the external bus arbiter function. 0: releases the bus mastership according to the priority 1: executes the bus cycles alternatively when an exdmac or external bus master conflict with a cpu, dmac, or dtc external space access request 4 ibccs 0 r/w internal bus cycle control select selects the internal bus arbiter function. 0: releases the bus mastership according to the priority 1: executes the bus cycles alternatively when a cpu bus mastership request conflicts with a dmac or dtc bus mastership request 3, 2 ? all 0 r reserved these are read-only bits and cannot be modified. 1 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. 0 pwdbe 0 r/w peripheral module write data buffer enable specifies whether or not to use the write data buffer function for the peripher al module write cycles. 0: write data buffer function not used 1: write data buffer function used section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 197 of 1340 rej09b0499-0200 9.2.9 endian control register (endiancr) endiancr selects the endian format for each area of the external address space. though the data format of this lsi is big endian, data can be transferred in the little endian format during external address space access. note that the data format for the areas used as a program area or a stack area should be big endian. bit bit name initial value r/w 7 le7 0 r/w 6 le6 0 r/w 5 le5 0 r/w 4 le4 0 r/w 3 le3 0 r/w 2 le2 0 r/w 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 7 6 5 4 3 2 le7 le6 le5 le4 le3 le2 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w little endian select selects the endian for the corresponding area. 0: data format of area n is specified as big endian 1: data format of area n is specified as little endian (n = 7 to 2) 1, 0 ? all 0 r reserved these are read-only bits and cannot be modified. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 198 of 1340 rej09b0499-0200 9.2.10 sram mode control register (sramcr) sramcr specifies the bus interface of each area in the external address space as a basic bus interface or a byte co ntrol sram interface. in areas specified as 8-bit access space by abw cr, the sramcr setting is ignored and the byte control sram interface cannot be specified. bit bit name initial value r/w 15 bcsel7 0 r/w 14 bcsel6 0 r/w 13 bcsel5 0 r/w 12 bcsel4 0 r/w 11 bcsel3 0 r/w 10 bcsel2 0 r/w 9 bcsel1 0 r/w 8 bcsel0 0 r/w bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 15 14 13 12 11 10 9 8 bcsel7 bcsel6 bcsel5 bcsel4 bcsel3 bcsel2 bcsel1 bcsel0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w byte control sram interface select selects the bus interface for the corresponding area. when setting a bit to 1, the bus interface select bits in bromcr and mpxcr must be cleared to 0. 0: area n is basic bus interface 1: area n is byte control sram interface (n = 7 to 0) 7 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 199 of 1340 rej09b0499-0200 9.2.11 burst rom interface cont rol register (bromcr) bromcr specifies the burst rom interface. bit bit name initial value r/w 15 bsrm0 0 r/w 14 bsts02 0 r/w 13 bsts01 0 r/w 12 bsts00 0 r/w 11 ? 0 r 10 ? 0 r 9 bswd01 0 r/w 8 bswd00 0 r/w bit bit name initial value r/w 7 bsrm1 0 r/w 6 bsts12 0 r/w 5 bsts11 0 r/w 4 bsts10 0 r/w 3 ? 0 r 2 ? 0 r 1 bswd11 0 r/w 0 bswd10 0 r/w bit bit name initial value r/w description 15 bsrm0 0 r/w area 0 burst rom interface select specifies the area 0 bus interface. to set this bit to 1, clear bit bcsel0 in sramcr to 0. 0: basic bus interface or byte-control sram interface 1: burst rom interface 14 13 12 bsts02 bsts01 bsts00 0 0 0 r/w r/w r/w area 0 burst cycle select specifies the number of burst cycles of area 0 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles 11, 10 ? all 0 r reserved these are read-only bits and cannot be modified. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 200 of 1340 rej09b0499-0200 bit bit name initial value r/w description 9 8 bswd01 bswd00 0 0 r/w r/w area 0 burst word number select selects the number of words in burst access to the area 0 burst rom interface 00: up to 4 words (8 bytes) 01: up to 8 words (16 bytes) 10: up to 16 words (32 bytes) 11: up to 32 words (64 bytes) 7 bsrm1 0 r/w area 1 burst rom interface select specifies the area 1 bus inte rface as a basic interface or a burst rom interface. to set this bit to 1, clear bit bcsel1 in sramcr to 0. 0: basic bus interface or byte-control sram interface 1: burst rom interface 6 5 4 bsts12 bsts11 bsts10 0 0 0 r/w r/w r/w area 1 burst cycle select specifies the number of cycles of area 1 burst cycle 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles 3 2 ? all 0 r reserved these are read-only bits and cannot be modified. 1 0 bswd11 bswd10 0 0 r/w r/w area 1 burst word number select selects the number of words in burst access to the area 1 burst rom interface 00: up to 4 words (8 bytes) 01: up to 8 words (16 bytes) 10: up to 16 words (32 bytes) 11: up to 32 words (64 bytes) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 201 of 1340 rej09b0499-0200 9.2.12 address/data multiplexed i/ o control register (mpxcr) mpxcr specifies the address/data multiplexed i/o interface. bit bit name initial value r/w 15 mpxe7 0 r/w 14 mpxe6 0 r/w 13 mpxe5 0 r/w 12 mpxe4 0 r/w 11 mpxe3 0 r/w 10 ? 0 r 9 ? 0 r 8 ? 0 r bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 addex 0 r/w bit bit name initial value r/w description 15 14 13 12 11 mpxe7 mpxe6 mpxe5 mpxe4 mpxe3 0 0 0 0 0 r/w r/w r/w r/w r/w address/data multiplex ed i/o interface select specifies the bus interface for the corresponding area. to set this bit to 1, clear the bcseln bit in sramcr to 0. 0: area n is specified as a basic interface or a byte control sram interface. 1: area n is specified as an address/data multiplexed i/o interface (n = 7 to 3) 10 to 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 addex 0 r/w address output cycle extension specifies whether a wait cycle is inserted for the address output cycle of addr ess/data multiplexed i/o interface. 0: no wait cycle is inserted for the address output cycle 1: one wait cycle is inse rted for the address output cycle section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 202 of 1340 rej09b0499-0200 9.3 bus configuration figure 9.4 shows the internal bus configuration of this lsi. the internal bus of this lsi consists of the following three types. ? internal system bus 1 a bus that connects the cpu, dtc, dmac, on-chip ram, on-chip rom, internal peripheral bus, and external access bus. ? internal system bus 2 a bus that connects the exdm ac and external access bus. ? internal peripheral bus a bus that accesses registers in the bus contro ller, interrupt controller, dmac, and exdmac, and registers of peripheral modules such as sci and timer. ? external access bus a bus that accesses external devices via the external bus interface. cpu dtc dmac b synchronization p synchronization i synchronization bus controller, interrupt controller, power-down controller external bus interface peripheral functions on-chip ram on-chip rom internal system bus 1 internal peripheral bus write data buffer write data buffer external access bus internal system bus 2 exdmac figure 9.4 internal bus configuration section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 203 of 1340 rej09b0499-0200 9.4 multi-clock function and number of access cycles the internal functions of th is lsi operate synchronousl y with the system clock (i ), the peripheral module clock (p ), or the external bus clock (b ). table 9.1 shows the synchronization clock and their corresponding functions. table 9.1 synchronization clocks and their corresponding functions synchronization clock function name i mcu operating mode interrupt controller bus controller cpu dtc dmac exdmac internal memory clock pulse generator power down control p i/o ports tpu ppg tmr wdt sci a/d d/a iic2 usb b external bus interface the frequency of each synchronization clock (i , p , and b ) is specified by the system clock control register (sckcr) independently. for further details, see section 26, clock pulse generator. there will be cases when p and b are equal to i and when p and b are different from i according to the sckcr specificati ons. in any case, access cycles for internal peripheral functions and external space is perfor med synchronously with p and b , respectively. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 204 of 1340 rej09b0499-0200 for example, in an external address sp ace access where the frequency rate of i and b is n : 1, the operation is performed in synchronization with b . in this case, external 2-state access space is 2n cycles and external 3-state acce ss space is 3n cycles (no wait cycl es is inserted) if the number of access cycles is counted based on i . if the frequencies of i , p and b are different, the start of bu s cycle may not synchronize with p or b according to the bus cycle in itiation timing. in this case, clock synchronization cycle (tsy) is inserted at the beginning of each bus cycle. for example, if an external address space access occurs when the frequency rate of i and b is n : 1, 0 to n-1 cycles of tsy may be inserted. if an internal peripheral module access occurs when the frequency rate of i and p is m : 1, 0 to m-1 cycles of tsy may be inserted. figure 9.5 shows the external 2-state acce ss timing when the frequency rate of i and b is 4 : 1. figure 9.6 shows the external 3-state acce ss timing when the frequency rate of i and b is 2 : 1. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 205 of 1340 rej09b0499-0200 divided clock synchronization cycle t 1 address i b as csn rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 read lhwr llwr write t 2 t sy bs rd/ wr figure 9.5 system clock: external bus clock = 4:1, external 2-state access section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 206 of 1340 rej09b0499-0200 divided clock synchronization cycle t 1 address i b as csn rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 read lhwr llwr write t 2 t sy t 3 bs rd/ wr figure 9.6 system clock: external bus clock = 2:1, external 3-state access section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 207 of 1340 rej09b0499-0200 9.5 external bus 9.5.1 input/output pins table 9.2 shows the pin configuration of the bus controller and table 9.3 shows the pin functions on each interface. table 9.2 pin configuration name symbol i/o function bus cycle start bs output signal indicating that the bus cycle has started address strobe/ address hold as / ah output ? strobe signal indicating that the basic bus, byte control sram, or burst rom space is accessed and address output on address bus is enabled ? signal to hold the address during access to the address/data multiplexed i/o interface read strobe rd output strobe signal indicating that the basic bus, byte control sram, burst rom, or address/data multiplexed i/o space is being read read/write rd/ wr output ? signal indicating the input or output direction ? write enable signal of the sram during access to the byte control sram space low-high write/ lower-upper byte select lhwr / lub output ? strobe signal indicating that the basic bus, burst rom, or address/data mu ltiplexed i/o space is written to, and the upper byte (d15 to d8) of data bus is enabled ? strobe signal indicating that the byte control sram space is accessed, and the upper byte (d15 to d8) of data bus is enabled low-low write/ lower-lower byte select llwr / llb output ? strobe signal indicating that the basic bus, burst rom, or address/data mu ltiplexed i/o space is written to, and the lower byte (d7 to d0) of data bus is enabled ? strobe signal indicating that the byte control sram space is accessed, and the lower byte (d7 to d0) of data bus is enabled section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 208 of 1340 rej09b0499-0200 name symbol i/o function chip select 0 cs0 output strobe signal indica ting that area 0 is selected chip select 1 cs1 output strobe signal indicati ng that area 1 is selected chip select 2 cs2 output strobe signal indicati ng that area 2 is selected chip select 3 cs3 output strobe signal indicati ng that area 3 is selected chip select 4 cs4 output strobe signal indicati ng that area 4 is selected chip select 5 cs5 output strobe signal indicati ng that area 5 is selected chip select 6 cs6 output strobe signal indicati ng that area 6 is selected chip select 7 cs7 output strobe signal indicati ng that area 7 is selected wait wait input wait request signal when accessing external address space. bus request breq input request signal for release of bus to external bus master bus request acknowledge back output acknowledge signal indicating that bus has been released to external bus master bus request output breqo output external bus request signal used when internal bus master accesses external address space in the external-bus released state data transfer acknowledge 3 (dmac_3) dack3 output data transfer acknowledge signal for dmac_3 single address transfer data transfer acknowledge 2 (dmac_2) dack2 output data transfer acknowledge signal for dmac_2 single address transfer data transfer acknowledge 1 (dmac_1) dack1 output data transfer acknowledge signal for dmac_1 single address transfer data transfer acknowledge 0 (dmac_0) dack0 output data transfer acknowledge signal for dmac_0 single address transfer data transfer acknowledge 1 (exdmac_1) edack1 output data transfer acknowledge signal for exdmac_1 single address transfer data transfer acknowledge 0 (exdmac_0) edack0 output data transfer acknowledge signal for exdmac_0 single address transfer external bus clock b output external bus clock section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 209 of 1340 rej09b0499-0200 table 9.3 pin functions in each interface initial state basic bus byte control sram burst rom address/data multiplexed i/o pin name 16 8 single- chip 16 8 16 16 8 16 8 remarks b output output ? o o o o o o o cs0 output output ? o o o o o ? ? cs1 ? ? ? o o o o o ? ? cs2 ? ? ? o o o ? ? ? ? cs3 ? ? ? o o o ? ? o o cs4 ? ? ? o o o ? ? o o cs5 ? ? ? o o o ? ? o o cs6 ? ? ? o o o ? ? o o cs7 ? ? ? o o o ? ? o o bs ? ? ? o o o o o o o rd/ wr ? ? ? o o o o o o o as output output ? o o o o o ? ? ah ? ? ? ? ? ? ? ? o o rd output output ? o o o o o o o lhwr / lub output output ? o ? o o ? o ? llwr / llb output output ? o o o o o o o wait ? ? ? o o o o o o o controlled by waite [legend] o: used as a bus control signal ? : not used as a bus control signal (used as a port input when initialized) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 210 of 1340 rej09b0499-0200 9.5.2 area division the bus controller divides the 16-mbyte address sp ace into eight areas, and performs bus control for the external address space in ar ea units. chip select signals ( cs0 to cs7 ) can be output for each area. figure 9.7 shows an area division of the 16-mbyte address space. for details on address map, see section 3, mcu operating modes. 16-mbyte space area 0 (2 mbytes) area 1 (2 mbytes) area 2 (8 mbytes) area 3 (2 mbytes) area 4 (1 mbyte) area 5 (1 mbyte ? 8 kbytes) area 6 (8 kbytes ? 256 bytes) area 7 (256 bytes) h'000000 h'1fffff h'200000 h'3fffff h'400000 h'bfffff h'c00000 h'dfffff h'e00000 h'efffff h'f00000 h'ffdfff h'ffe000 h'fffeff h'ffff00 h'ffffff figure 9.7 address space area division section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 211 of 1340 rej09b0499-0200 9.5.3 chip select signals this lsi can output chip select signals ( cs0 to cs7 ) for areas 0 to 7. the signal outputs low when the corresponding external address space area is accessed. figure 9.8 shows an example of csn (n = 0 to 7) signal output timing. enabling or disabling of csn signal output is set by the port function control register (pfcr). for details, see section 13.3, port function controller. in on-chip rom disabled extended mode, pin cs0 is placed in the output state after a reset. pins cs1 to cs7 are placed in the input state after a reset and so the correspond ing pfcr bits should be set to 1 when outputting signals cs1 to cs7 . in on-chip rom enabled extended mode, pins cs0 to cs7 are all placed in the input state after a reset and so the corresponding pfcr bits should be set to 1 when outputting signals cs0 to cs7 . the pfcr can specify multiple cs outputs for a pin. if multiple csn outputs are specified for a single pin by the pfcr, cs to be output are generated by mixing all the cs signals. in this case, the settings for the external bus interface areas in which the csn signals are output to a single pin should be the same. figure 9.9 shows the signal output timing when the cs signals to be output to areas 5 and 6 are output to the same pin. bus cycle t 1 t 2 t 3 external address of area n address bus b csn figure 9.8 csn signal output timing (n = 0 to 7) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 212 of 1340 rej09b0499-0200 output waveform b area 5 access cs6 cs5 area 6 access area 5 access area 6 access address bus figure 9.9 timing when cs signal is output to the same pin 9.5.4 external bus interface the type of the external bus in terfaces, bus width, endian form at, number of access cycles, and strobe assert/negate timings can be set for each area in the external address space. the bus width and the number of access cycles fo r both on-chip memory and intern al i/o registers are fixed, and are not affected by the external bus settings. (1) type of external bus interface four types of external bus interfaces are provid ed and can be selected in area units. table 9.4 shows each interface name, description, area name to be set for each interface. table 9.5 shows the areas that can be specified for each interface. the initial state of each area is a basic bus interface. table 9.4 interface names and area names interface description area name basic interface directly connected to rom and ram basic bus space byte control sram interface directly connected to byte sram with byte control pin byte control sram space burst rom interface directly connected to the rom that allows page access burst rom space address/data multiplexed i/o interface directly connected to the peripheral lsi that requires address and data multiplexing address/data multiplexed i/o space section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 213 of 1340 rej09b0499-0200 table 9.5 areas specifiab le for each interface areas interface related registers 0 1 2 3 4 5 6 7 basic interface o o o o o o o o byte control sram interface sramcr o o o o o o o o burst rom interface bromcr o o ? ? ? ? ? ? address/data multiplexed i/o interface mpxcr ? ? ? o o o o o (2) bus width a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space and an ar ea for which a 16-bit bus is selected functions as a 16-bit access space. in addition, the bus width of address/data multiplex ed i/o space is 8 bits or 16 bits, and the bus width for the byte control sram space is 16 bits. the initial state of the bus width is specified by the operating mode. if all areas are designated as 8-bit access space, 8-b it bus mode is set; if any area is designated as 16-bit access space, 16-b it bus mode is set. (3) endian format though the endian format of this lsi is big endian, data can be converted into little endian format when reading or writing to the external address space. areas 7 to 2 can be specified as either big endian or little endian format by the le7 to le2 bits in endiancr. the initial state of each area is the big endian format. note that the data format for the areas used as a program area or a stack area should be big endian. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 214 of 1340 rej09b0499-0200 (4) number of access cycles (a) basic bus interface the number of access cycles in the basic bus interface can be specifi ed as two or three cycles by the astcr. an area specified as 2-state acce ss is specified as 2-state access space; an area specified as 3-state access is sp ecified as 3-state access space. for the 2-state access space, a wait cycle insertio n is disabled. for the 3-state access space, a program wait (0 to 7 cycles) specified by wtcra and wtcrb or an external wait by wait can be inserted. assertion period of the chip select signal can be extended by csacr. number of access cycles in the basic bus interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of cs extension cycles (0, 1, 2) [+ number of external wait cycles by the wait pin] (b) byte control sr am interface the number of access cycles in th e byte control sram interface is the same as that in the basic bus interface. number of access cycles in byte control sram interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of cs extension cycles (0, 1, 2) [+ number of external wait cycles by the wait pin] (c) burst rom interface the number of access cycles at fu ll access in the burst rom interface is the same as that in the basic bus interface. the number of access cycles in the burst access can be specified as one to eight cycles by the bsts bit in bromcr. number of access cycles in the burst rom interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of cs extension cycles (0, 1) [+number of external wait cycles by the wait pin] + number of burst access cycles (1 to 8) number of burst accesses (0 to 63) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 215 of 1340 rej09b0499-0200 (d) address/data multiplexed i/o interface the number of access cycles in da ta cycle of the address/data multiplexed i/o interface is the same as that in the basic bus interface. the nu mber of access cycles in address cycle can be specified as two or three cycles by the addex bit in mpxcr. number of access cycles in the addr ess/data multiplexed i/o interface = number of address output cycles (2, 3) + number of data output cycles (2, 3) + number of program wait cycles (0 to 7) + number of cs extension cycles (0, 1, 2) [+number of external wait cycles by the wait pin] table 9.6 lists the number of access cycles for each interface. table 9.6 number of access cycles = = = = = = = tma [2,3] = tma [2,3] th [0,1] th [0,1] th [0,1] th [0,1] th [0,1] th [0,1] +th [0,1] +th [0,1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +tt [0,1] +tt [0,1] +tt [0,1] +tt [0,1] +tt [0,1] +tt [0,1] [2 to 4] [3 to 12 + n] [2 to 4] [3 to 12 + n] [(2 to 3) + (1 to 8) m] [(2 to 11 + n) + (1 to 8) m] [4 to 7] [5 to 15 + n] +tpw [0 to 7] +tpw [0 to 7] +tpw [0 to 7] +tpw [0 to 7] +ttw [n] +ttw [n] +ttw [n] +ttw [n] +t3 [1] +t3 [1] +t3 [1] +t3 [1] basic bus interface byte control sram interface burst rom interface address/data multiplexed i/o interface +tb [(1 to 8) m] +tb [(1 to 8) m] [legend] numbers: number of access cycles n: pin wait (0 to ) m: number of burst accesses (0 to 63) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 216 of 1340 rej09b0499-0200 (5) strobe assert/negate timings the assert and negate timings of the strobe signals can be modified as we ll as number of access cycles. ? read strobe ( rd ) in the basic bus interface ? chip select assertion period extens ion cycles in the basic bus interface ? data transfer acknowledge ( dack3 to dack0 ) output for dmac single address transfers ? data transfer acknowledge ( edack1 and edack0 ) output for exdmac single address transfers 9.5.5 area and external bus interface (1) area 0 area 0 includes on-chip rom. a ll of area 0 is used as extern al address space in on-chip rom disabled extended mode, and the space excludin g on-chip rom is external address space in on- chip rom enabled extended mode. when area 0 external address space is accessed, the cs0 signal can be output. either of the basic bus interface, byte contro l sram interface, or burst rom interface can be selected for area 0 by bit bsrm0 in bromcr and bit bcsel0 in sramcr. table 9.7 shows the external interface of area 0. table 9.7 area 0 ex ternal interface register setting interface bsrm0 of bromcr bcsel0 of sramcr basic bus interface 0 0 byte control sram interface 0 1 burst rom interface 1 0 setting prohibited 1 1 section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 217 of 1340 rej09b0499-0200 (2) area 1 in externally extended mode, all of area 1 is external address space. in on-chip rom enabled extended mode, the space excluding on-ch ip rom is external address space. when area 1 external address space is accessed, the cs1 signal can be output. either of the basic bus interface, byte control sram, or burst ro m interface can be selected for area 1 by bit bsrm1 in bromcr and bit bcsel1 in sramcr. table 9.8 shows the external interface of area 1. table 9.8 area 1 ex ternal interface register setting interface bsrm1 of bromcr bcsel1 of sramcr basic bus interface 0 0 byte control sram interface 0 1 burst rom interface 1 0 setting prohibited 1 1 (3) area 2 in externally extended mode, all of area 2 is external address space. when area 2 external address space is accessed, the cs2 signal can be output. either the basic bus interface or byte control sr am interface can be selected for area 2 by bit bcsel2 in sramcr. table 9.9 shows th e external interf ace of area 2. table 9.9 area 2 ex ternal interface register setting interface bcsel2 of sramcr basic bus interface 0 byte control sram interface 1 section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 218 of 1340 rej09b0499-0200 (4) area 3 in externally extended mode, all of area 3 is external address space. when area 3 external address space is accessed, the cs3 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 3 by bit mpxe3 in mpxcr and bit bcsel3 in sramcr. table 9.10 shows the external interface of area 3. table 9.10 area 3 external interface register setting interface mpxe3 of mpxcr bcsel3 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 (5) area 4 in externally extended mode, all of area 4 is external address space. when area 4 external address space is accessed, the cs4 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 4 by bit mpxe4 in mpxcr and bit bcsel4 in sramcr. table 9.11 shows the external interface of area 4. table 9.11 area 4 external interface register setting interface mpxe4 of mpxcr bcsel4 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 219 of 1340 rej09b0499-0200 (6) area 5 area 5 includes the on-chip ram and access prohibited sp aces. in external extended mode, area 5, other than the on-chip ram and access prohibited spaces, is external address space. note that the on-chip ram is enabled when the rame bit in syscr are set to 1. if the rame bit in syscr is cleared to 0, the on- chip ram is disabled and the corresponding addresses are an external address space. for details, s ee section 3, mcu operating modes. when area 5 external address space is accessed, the cs5 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 5 by the mpxe5 bit in mpxcr and the bcsel5 bit in sramcr. table 9.12 shows the external interface of area 5. table 9.12 area 5 external interface register setting interface mpxe5 of mpxcr bcsel5 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 220 of 1340 rej09b0499-0200 (7) area 6 area 6 includes internal i/o regi sters. in external extended mo de, area 6 other than on-chip i/o register area is external address space. when area 6 external address space is accessed, the cs6 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 6 by the mpxe6 bit in mpxcr and the bcsel6 bit in sramcr. table 9.13 shows the external interface of area 6. table 9.13 area 6 external interface register setting interface mpxe6 of mpxcr bcsel6 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 (8) area 7 area 7 includes internal i/o regi sters. in external extended mode , area 7 other than internal i/o register area is external address space. when area 7 external address space is accessed, the cs7 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 7 by the mpxe7 bit in mpxcr and the bcsel7 bit in sramcr. table 9.14 shows the external interface of area 7. table 9.14 area 7 external interface register setting interface mpxe7 of mpxcr bcsel7 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 221 of 1340 rej09b0499-0200 9.5.6 endian and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and contro ls whether the upper byte data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-b it access space), the data size, and endian format when accessing external address space. (1) 8-bit access space with the 8-bit access space, the lower byte data bu s (d7 to d0) is always used for access. the amount of data that can be accessed at one tim e is one byte: a word access is performed as two byte accesses, and a longword acces s, as four byte accesses. figures 9.10 and 9.11 illustrate data alignmen t control for the 8-bit access space. figure 9.10 shows the data alignment when the data endian format is specified as big endian. figure 9.11 shows the data alignment when the data endian format is specified as little endian. longword access address access count 23 7 15 8 0 7 data size byte byte byte byte byte byte byte byte word 1 1st 1st 2nd 1st 2nd 3rd 4th 2 4 bus cycle data size data bus d15 d8 d7 d0 rd 7 15 31 8 0 24 16 0 lhwr / lub llwr / llb strobe signal n n n figure 9.10 access sizes and data alignmen t control for 8-bit access space (big endian) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 222 of 1340 rej09b0499-0200 longword access address access count 15 15 23 16 24 31 data size byte byte byte byte byte byte byte byte word 1 1st 1st 2nd 1st 2nd 3rd 4th 2 4 bus cycle data size data bus d15 d8 d7 d0 rd 7 7 7 0 8 0 8 0 lhwr / lub llwr / llb strobe signal n n n figure 9.11 access sizes and data a lignment control for 8-bit access space (little endian) (2) 16-bit access space with the 16-bit access space, the upper byte data bu s (d15 to d8) and lower byte data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word. figures 9.12 and 9.13 illustrate data alignment control for the 16-bit access space. figure 9.12 shows the data alignment when the data endian format is specified as big endian. figure 9.13 shows the data alignment when the data endian format is specified as little endian. in big endian, byte access for an even address is performed by using the upper byte data bus and byte access for an odd address is performe d by using the lower byte data bus. in little endian, byte access for an even address is performed by using the lower byte data bus, and byte access for an odd address is performe d by using the third byte data bus. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 223 of 1340 rej09b0499-0200 longword access address access count 15 31 24 0 7 access size byte byte byte byte byte word word word word byte byte word 1 1 1 1st 1st 1st 1st 2nd 1st 2nd 1st 2nd 3rd 2 2 3 bus cycle data size data bus d15 d8 d7 d0 rd 15 23 8 8 7 0 7 0 7 0 23 16 16 15 8 31 24 7 0 15 8 7 0 lhwr / lub llwr / llb strobe signal even (2n) (2n) odd even (2n+1) odd (2n+1) odd (2n+1) even (2n) figure 9.12 access sizes and data alignment control for 16-bit access space (big endian) longword access address access count 15 31 24 0 7 access size byte byte byte byte byte word word word word byte byte word 1 1 1 1st 1st 1st 1st 2nd 1st 2nd 1st 2nd 3rd 2 2 3 bus cycle data size 15 23 8 8 7 0 7 0 7 0 23 16 16 15 8 31 24 7 0 15 8 7 0 even (2n) (2n) odd even (2n+1) odd (2n+1) odd (2n+1) even (2n) data bus d15 d8 d7 d0 rd lhwr / lub llwr / llb strobe signal figure 9.13 access sizes and data alig nment control for 16 -bit access space (little endian) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 224 of 1340 rej09b0499-0200 9.6 basic bus interface the basic bus interface can be connected direc tly to the rom and sram . the bus specifications can be specified by the abwcr, ast cr, wtcra, wtcrb, rdncr, csacr, and endiancr. 9.6.1 data bus data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and contro ls whether the upper byte data bus (d15 to d8) or lower byte data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-b it access space), the data size, and endian format when accessing external address space,. for details, s ee section 9.5.6, endian and data alignment. 9.6.2 i/o pins used for basic bus interface table 9.15 shows the pins us ed for basic bus interface. table 9.15 i/o pins for basic bus interface name symbol i/o function bus cycle start bs output signal indicating that the bus cycle has started address strobe as * output strobe signal indicati ng that an address output on the address bus is valid during access read strobe rd output strobe signal indicating the read access read/write rd/ wr output signal indicating the data bus input or output direction low-high write lhwr output strobe signal indicating that the upper byte (d15 to d8) is valid during write access low-low write llwr output strobe signal indicating that the lower byte (d7 to d0) is valid during write access chip select 0 to 7 cs0 to cs7 output strobe signal indicati ng that the area is selected wait wait input wait request signal used when an external address space is accessed note: * when the address/data multiplexed i/o is selected, this pin only functions as the ah output and does not function as the as output. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 225 of 1340 rej09b0499-0200 9.6.3 basic timing this section describes the basic timing when the data is specified as big endian. (1) 16-bit 2-state access space figures 9.14 to 9.16 sh ow the bus timing of 16 -bit 2-state access space. when accessing 16-bit acces s space, the upper byte data bus (d 15 to d8) is used for even addresses access, and the lower byte data bus (d7 to d0) is used for odd addresses. no wait cycles can be inserted. 1. n = 0 to 7 2. when rdnn = 0 3. when dkc, edkc = 0 valid invalid valid t 1 t 2 address csn as rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr read write notes: high level high-z b bus cycle bs rd/ wr dack or edack figure 9.14 16-bit 2-stat e access space bus timing (b yte access for even address) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 226 of 1340 rej09b0499-0200 invalid valid t 1 t 2 address csn as rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr dack or edack read write high level high-z b bus cycle valid bs rd/ wr 1. n = 0 to 7 2. when rdnn = 0 3. when dkc, edkc = 0 notes: figure 9.15 16-bit 2-stat e access space bus timing (b yte access for odd address) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 227 of 1340 rej09b0499-0200 valid valid t 1 t 2 address csn as rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr dack or edack read write b bus cycle valid valid bs rd/ wr 1. n = 0 to 7 2. when rdnn = 0 3. when dkc, edkc= 0 notes: figure 9.16 16-bit 2-stat e access space bus timing (w ord access for even address) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 228 of 1340 rej09b0499-0200 (2) 16-bit 3-state access space figures 9.17 to 9.19 sh ow the bus timing of 16 -bit 3-state access space. when accessing 16-bit access space, the upper byte data bus (d 15 to d8) is used for even addresses, and the lower byte data bus (d7 to d0 ) is used for odd addresses. wait cycles can be inserted. valid invalid t 1 t 2 t 3 address csn as rd dack or edack d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr high level high-z b bus cycle valid bs rd/ wr read write 1. n = 0 to 7 2. when rdnn = 0 3. when dkc, edkc= 0 notes: figure 9.17 16-bit 3-stat e access space bus timing (b yte access for even address) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 229 of 1340 rej09b0499-0200 invalid valid t 1 t 2 t 3 address csn as rd dack or edack d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr high level high-z b bus cycle valid bs rd/ wr read write 1. n = 0 to 7 2. when rdnn = 0 3. when dkc, edkc= 0 notes: figure 9.18 16-bit 3-stat e access space bus timing (w ord access for odd address) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 230 of 1340 rej09b0499-0200 valid valid t 1 t 2 t 3 address csn as rd b bus cycle valid valid rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr read write bs rd/ wr dack or edack 1. n = 0 to 7 2. when rdnn = 0 3. when dkc, edkc= 0 notes: figure 9.19 16-bit 3-stat e access space bus timing (w ord access for even address) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 231 of 1340 rej09b0499-0200 9.6.4 wait control this lsi can extend the bus cycle by inserting wait cycles (tw) when the ex ternal address space is accessed. there are two ways of inserting wait cy cles: program wait (tpw) insertion and pin wait (ttw) insertion using the wait pin. (1) program wait insertion from 0 to 7 wait cycles can be in serted automatically between the t 2 state and t 3 state for 3-state access space, according to the settings in wtcra and wtcrb. (2) pin wait insertion for 3-state access space, when th e waite bit in bcr1 is set to 1 and the corresponding icr bit is set to 1, wait input by means of the wait pin is enabled. when the external address space is accessed in this state, a program wait (tpw) is first inserted according to the wtcra and wtcrb settings. if the wait pin is low at the falling edge of b in the last t2 or tpw cycle, another ttw cycle is inserted until the wait pin is brought high. the pin wait insertion is effective when the tw cycles are inserted to seven cycles or mo re, or when the number of tw cycles to be inserted is changed according to the external devices. the waite bit is common to all areas. for details on icr, see section 13, i/o ports. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 232 of 1340 rej09b0499-0200 figure 9.20 shows an example of wait cycle insertion timing. afte r a reset, the 3-state access is specified, the program wait is inse rted for seven cycles, and the wait input is disabled. wait by program wait t 1 address b as csn rd data bus read read data lhwr , llwr write data write notes: 1. upward arrows indicate the timing of wait pin sampling. 2. n = 0 to 7 3. when rdnn = 0 wait data bus t 2 t pw t tw t tw t 3 wait by wait pin bs rd/ wr figure 9.20 example of wa it cycle insertion timing section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 233 of 1340 rej09b0499-0200 9.6.5 read strobe ( rd ) timing the read strobe timing can be modified in area units by setting bits rdn7 to rdn0 in rdncr to 1. note that the rd timing with respect to the dack or edack rising edge will change if the read strobe timing is modified by setting rdnn to 1 when the dmac or exdmac is used in the single address mode. figure 9.21 shows an example of timing when the read strobe timing is changed in the basic bus 3- state access space. bus cycle t 1 t 2 address bus b csn as rd t 3 data bus rd data bus rdnn = 0 rdnn = 1 bs rd/ wr dack or edack 1. n = 0 to 7 2. when dkc, edkc = 0 notes: figure 9.21 example of read strobe timing section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 234 of 1340 rej09b0499-0200 9.6.6 extension of chip select ( cs ) assertion period some external i/o devices require a setu p time and hold time between address and cs signals and strobe signals such as rd , lhwr , and llwr . settings can be made in csacr to insert cycles in which only the cs , as , and address signals are asserted before and after a basic bu s space access cycle. extension of the cs assertion period can be set in area units. with the cs assertion extension period in wr ite access, the data setup and hold times are less stringent since the write data is output to the data bus. figure 9.22 shows an example of the timing when the cs assertion period is extended in basic bus 3-state access space. both extension cycle th inserted before the basi c bus cycle and extension cycle tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. insertion or non- insertion can be specified for the th cycle w ith the upper eight bits (csxh7 to csxh0) in csacr, and for the tt cycle with the lower eight bits (csxt7 to csxt0). section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 235 of 1340 rej09b0499-0200 t h t 1 t 2 t 3 t t address bus cycle b as csn rd data bus read data read lhwr , llwr write data write data bus bs rd/ wr dack or edack 1. n = 0 to 7 2. when dkc, edkc = 0 notes: figure 9.22 example of timing when ch ip select assertion period is extended section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 236 of 1340 rej09b0499-0200 9.6.7 dack and edack signal output timings for dmac or exdmac single address transfers, the dack or edack signal assert timing can be modified by using the dkc or edkc bit in bcr1. figure 9.23 shows the dack and edack signal output timings. setting the dkc or edkc bit to 1 asserts the dack or edack signal a half cycle earlier. t 1 t 2 bus cycle b address bus write data write read data read csn as rd data bus data bus lhwr , llwr bs rd/ wr dkc, edck = 0 dkc, edck = 1 dack or edack notes: 1. n = 7 to 0 2. rdnn = 0 figure 9.23 dack and edack signal output timings section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 237 of 1340 rej09b0499-0200 9.7 byte control sram interface the byte control sram interface is a memory interface for outputting a byte select strobe during a read or a write bus cycle. this interface has 16 -bit data input/output pins and can be connected to the sram that has the upper byte select a nd the lower byte select strobes such as ub and lb . the operation of the byte contro l sram interface is the same as the basic bus interface except that: the byte select strobes ( lub and llb ) are output from the write strobe output pins ( lhwr and llwr ), respectively; th e read strobe ( rd ) negation timing is a half cy cle earlier than that in the case where rdnn = 0 in the basic bus interface regardless of the rdncr settings; and the rd/ wr signal is used as write enable. 9.7.1 byte control sram space setting byte control sram interface can be specified for areas 0 to 7. each area can be specified as byte control sram interface by setting bits bcseln (n = 0 to 7) in sramcr. for the area specified as burst rom interface or addr ess/data multiplexed i/o interface, the sramcr setting is invalid and byte control sram interface cannot be used. 9.7.2 data bus the bus width of the byte control sram space can be specified as 16- bit byte control sram space according to bits abwhn an d abwln (n = 0 to 7) in abw cr. the area specified as 8-bit access space cannot be specified as the byte control sram space. for the 16-bit byte control sram space, data bus (d15 to d0) is valid. access size and data alignment are the same as th e basic bus interface. for details, see section 9.5.6, endian and data alignment. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 238 of 1340 rej09b0499-0200 9.7.3 i/o pins used for byte control sram interface table 9.16 shows the pins used for the byte control sram interface. in the byte control sram inte rface, write strobe signals ( lhwr and llwr ) are output from the byte select strobes. the rd/ wr signal is used as a write enable signal. table 9.16 i/o pins for byte control sram interface pin when byte control sram is specified name i/o function as / ah as address strobe output strobe signal indi cating that the address output on the address bus is valid when a basic bus interface space or byte control sram space is accessed csn csn chip select output strobe signal indicating that area n is selected rd rd read strobe output output enable for the sram when the byte control sram space is accessed rd/ wr rd/ wr read/write output write enable signal for the sram when the byte control sram space is accessed lhwr / lub lub lower-upper byte select output upper byte select when the 16-bit byte control sram space is accessed llwr / llb llb lower-lower byte select output lower byte select when the 16-bit byte control sram space is accessed wait wait wait input wait request signal used when an external address space is accessed a20 to a0 a20 to a0 address pin output address output pin d15 to d0 d15 to d0 data pin input/ output data input/output pin section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 239 of 1340 rej09b0499-0200 9.7.4 basic timing (1) 2-state access space figure 9.24 shows the bus timing when the byte control sram space is specified as a 2-state access space. data buses used for 16-bit access space is the same as those in basic bus interface. no wait cycles can be inserted. b address d15 to d8 d7 to d0 high level d15 to d8 d7 to d0 bus cycle csn as rd lub llb dack or edack bs rd/ wr rd rd/ wr t 1 t 2 note: n = 0 to 7 valid valid read write valid valid figure 9.24 16-bit 2-stat e access space bus timing section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 240 of 1340 rej09b0499-0200 (2) 3-state access space figure 9.25 shows the bus timing when the byte control sram space is specified as a 3-state access space. data buses used for 16-bit access space is the same as those in the basic bus interface. wait cycles can be inserted. b address high level bus cycle csn as t 1 t 2 t 3 valid valid valid valid d15 to d8 d7 to d0 d15 to d8 d7 to d0 rd lub llb dack or edack bs rd/ wr rd rd/ wr note: n = 0 to 7 read write figure 9.25 16-bit 3-st ate access space bus timing section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 241 of 1340 rej09b0499-0200 9.7.5 wait control the bus cycle can be extended for the byte contro l sram interface by inserting wait cycles (tw) in the same way as the basic bus interface. (1) program wait insertion from 0 to 7 wait cycles can be inserted automa tically between t2 cycle and t3 cycle for the 3- state access space in area units, according to the settings in wtcra and wtcrb. (2) pin wait insertion for 3-state access space, when the waite bit in bcr1 is set to 1, the corresponding ddr bit is cleared to 0, and the icr bit is set to 1, wait input by means of the wait pin is enabled. for details on ddr and icr, see section 13, i/o ports. figure 9.26 shows an example of wait cycle insertion timing. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 242 of 1340 rej09b0499-0200 wait by program wait t 1 address b as dack or edack lub , llb csn rd rd rd/ wr rd/ wr data bus read data read bs write data high level write notes: 1. upward arrows indicate the timing of wait pin sampling. 2. n = 0 to 7 wait data bus t 2 t pw t tw t tw t 3 wait by wait pin figure 9.26 example of wa it cycle insertion timing section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 243 of 1340 rej09b0499-0200 9.7.6 read strobe ( rd ) when the byte control sram space is specified , the rdncr setting for the corresponding space is invalid. the read strobe negation timing is the same timing as when rdnn = 1 in the basic bus interface. note that the rd timing with respect to the dack or edack rising edge becomes different. 9.7.7 extension of chip select ( cs ) assertion period in the byte control sram interface, the extension cycles can be inserted before and after the bus cycle in the same way as the basic bus interface. fo r details, see section 9. 6.6, extension of chip select ( cs ) assertion period. 9.7.8 dack and edack signal output timings for dmac or exdmac single address transfers, the dack or edack signal assert timing can be modified by using the dkc or edkc bit in bcr1. figure 9.27 shows the dack and edack signal output timings. setting the dkc or edkc bit to 1 asserts the dack or edack signal a half cycle earlier. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 244 of 1340 rej09b0499-0200 b address d15 to d8 d7 to d0 high level d15 to d8 d7 to d0 dkc, edkc = 0 dkc, edkc = 1 bus cycle csn as rd lub llb bs dack or edack rd/ wr rd rd/ wr t 1 t 2 valid valid read write valid valid figure 9.27 dack and edack signal output timings section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 245 of 1340 rej09b0499-0200 9.8 burst rom interface in this lsi, external address space areas 0 and 1 can be designated as burst rom space, and burst rom interfacing performed. the burst rom interface enables rom with page access capability to be accessed at high speed. areas 1 and 0 can be designated as burst ro m space by means of bits bsrm1 and bsrm0 in bromcr. consecutive burst accesses of up to 32 words can be performe d, according to the setting of bits bswdn1 and bswdn0 (n = 0, 1) in bromcr. from one to eight cycles can be selected for burst access. settings can be made independently for area 0 and area 1. in the burst rom interface, the burst access covers only cpu read accesses and cluster transfer read accesses of exdmac. other accesses are performe d with the similar method to the basic bus interface. 9.8.1 burst rom space setting burst rom interface can be specified for areas 0 and 1. areas 0 and 1 can be specified as burst rom space by setting bits bsrm n (n = 0, 1) in bromcr. 9.8.2 data bus the bus width of the burst rom space can be sp ecified as 8-bit or 16-bit burst rom interface space according to the abwhn and abwl n bits (n = 0, 1) in abwcr. for the 8-bit bus width, data bus (d7 to d0) is valid. for the 16-bit bus width, data bus (d15 to d0) is valid. access size and data alignment are the same as th e basic bus interface. for details, see section 9.5.6, endian and data alignment. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 246 of 1340 rej09b0499-0200 9.8.3 i/o pins used for burst rom interface table 9.17 shows the pins used for the burst rom interface. table 9.17 i/o pins used for burst rom interface name symbol i/o function bus cycle start bs output signal indicati ng that the bus cycle has started. address strobe as output strobe signal indicating that an address output on the address bus is valid during access read strobe rd output strobe signal indicating the read access read/write rd/ wr output signal indicating the data bus input or output direction low-high write lhwr output strobe signal indicating that the upper byte (d15 to d8) is valid during write access low-low write llwr output strobe signal indicating that the lower byte (d7 to d0) is valid during write access chip select 0 to 7 cs0 to cs7 output strobe signal indicati ng that the area is selected wait wait input wait request signal used when an external address space is accessed section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 247 of 1340 rej09b0499-0200 9.8.4 basic timing the number of access cycles in the initial cycle (full access) on the burst rom interface is determined by the basic bus interface settings in abwcr, astcr, wtcra, wtcrb, and bits csxhn in csacr (n = 0 to 7) . when area 0 or area 1 designated as burst rom space, the settings in rdncr and bits csxtn in csacr (n = 0 to 7) are ignored during read accesses by the cpu and exdmac cluster transfer. from one to eight cycles can be selected for th e burst cycle, according to the settings of bits bsts02 to bsts00 and bsts12 to bsts10 in bromcr. wait cycles cannot be inserted. in addition, 4-word, 8-word, 16-w ord, or 32-word consecutive burst access can be performed according to the settings of bsts01, bsts00 , bsts11, and bsts10 bits in bromcr. the basic access timing for burst rom spac e is shown in figures 9.28 and 9.29. t 1 t 2 t 1 t 2 t 1 t 2 t 3 b upper address bus note: n = 1, 0 lower address bus data bus full access burst access csn as rd bs rd/ wr figure 9.28 example of burst rom acce ss timing (astn = 1, two burst cycles) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 248 of 1340 rej09b0499-0200 t 1 t 2 t 1 t 1 b upper address bus lower address bus data bus full access burst access csn as rd bs rd/ wr note: n = 1, 0 figure 9.29 example of burst rom acce ss timing (astn = 0, one burst cycle) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 249 of 1340 rej09b0499-0200 9.8.5 wait control as with the basic bus interface, either program wait insertion or pin wait insertion by the wait pin can be used in the initial cycle (full access) on the burst rom interfa ce. see section 9.6.4, wait control. wait cycles cannot be inserted in a burst cycle. 9.8.6 read strobe ( rd ) timing in the burst rom space, the rdncr setting for th e corresponding space is invalid during read accesses by the cpu or exdmac cluster transfer. the read strobe negation timing is the same timing as when rdnn = 0 in the basic bus interface. 9.8.7 extension of chip select ( cs ) assertion period in the burst rom interface, the exte nsion cycles can be inserted in the same way as the basic bus interface. for the burst rom space, the burst access can be en abled only during read accesses by the cpu or exdmac cluster transfer. in this case, the setti ng of the corresponding csxtn bit in csacr is ignored and an extension cycle can be inserted only before the full access cycle. note that no extension cycle can be inserted befo re or after the burst access cycles. for accesses except read accesses by the cpu or exdmac cluster transfer, the burst rom space is equivalent to the basic bus in terface space. accordingly, extensio n cycles can be inserted before and after the burst access cycles. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 250 of 1340 rej09b0499-0200 9.9 address/data multiplexed i/o interface if areas 3 to 7 of external address space are specified as address/data multiplexed i/o space in this lsi, the address/data multiplexed i/o interface can be performed. in the address/data multiplexed i/o interface, peripheral lsis that require the mu ltiplexed address/data can be connected directly to this lsi. 9.9.1 address/data multiplexed i/o space setting address/data multiplexed i/o interface can be sp ecified for areas 3 to 7. each area can be specified as the address/data multiplexed i/o space by setting bi ts mpxen (n = 3 to 7) in mpxcr. 9.9.2 address/data multiplex in the address/data multiplexed i/o space, data bu s is multiplexed with address bus. table 9.18 shows the relationship between the bus width and address output. table 9.18 address/data multiplex bus width cycle data pins address data address data 8 bits 16 bits pi7 - - a15 d15 pi6 - - a14 d14 pi5 - - a13 d13 pi4 - - a12 d12 pi3 - - a11 d11 pi2 - - a10 d10 pi1 - - a9 d9 pi0 - - a8 d8 ph7 a7 d7 a7 d7 ph6 a6 d6 a6 d6 ph5 a5 d5 a5 d5 ph4 a4 d4 a4 d4 ph3 a3 d3 a3 d3 ph2 a2 d2 a2 d2 ph1 a1 d1 a1 d1 ph0 a0 d0 a0 d0 9.9.3 data bus the bus width of the address/data multiplexed i/ o space can be specified for either 8-bit access space or 16-bit access space by th e abwhn and abwln bits (n = 3 to 7) in abwcr. for the 8-bit access space, d7 to d0 are valid for both addr ess and data. for 16-bit access space, d15 to d0 are valid for both address and data. if the address/data multiplexed i/o space is accessed, the corresponding address w ill be output to the address bus. for details on access size and data alignment, s ee section 9.5.6, endian and data alignment. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 251 of 1340 rej09b0499-0200 9.9.4 i/o pins used for address/data multiplexed i/o interface table 9.19 shows the pins used for the address/data multiplexed i/o interface. table 9.19 i/o pins for address/ data multiplexed i/o interface pin when byte control sram is specified name i/o function csn csn chip select output chip select (n = 3 to 7) when area n is specified as the address/data multiplexed i/o space as / ah ah * address hold output signal to hold an address when the address/data multiplexed i/o space is specified rd rd read strobe output signal indicating that the address/data multiplexed i/o space is being read lhwr / lub lhwr low-high write output strobe signal indicating that the upper byte (d15 to d8) is valid when the address/data multiplexed i/o space is written llwr / llb llwr low-low write output strobe signal indicating that the lower byte (d7 to d0) is valid when the address/data multiplexed i/o space is written d15 to d0 d15 to d0 address/data input/ output address and data multiplexed pins for the address/data multiplexed i/o space. only d7 to d0 are valid when the 8-bit space is specified. d15 to d0 are valid when the 16-bit space is specified. a20 to a0 a20 to a0 address output address output pin wait wait wait input wait request signal used when the external address space is accessed bs bs bus cycle start output signal to indicate the bus cycle start rd/ wr rd/ wr read/write output signal indicating t he data bus input or output direction note: * the ah output is multiplexed with the as output. at the timing that an area is specified as address/data multiplexed i/o, this pin starts to function as the ah output meaning that this pin cannot be used as the as output. at this time, when other areas set to the basic bus interface is accessed, this pin does not function as the as output. until an area is specified as address/data multiplex ed i/o, be aware that this pin functions as the as output. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 252 of 1340 rej09b0499-0200 9.9.5 basic timing the bus cycle in the address/data multiplexed i/o in terface consists of an address cycle and a data cycle. the data cycle is based on the basi c bus interface timing sp ecified by the abwcr, astcr, wtcra, wtcrb, rdncr, and csacr. figures 9.30 and 9.31 show the basic access timings. t ma1 t ma2 t 2 t 1 b address bus d7 to d0 d7 to d0 address cycle data cycle csn llwr ah rd dack or edack bs rd/ wr note: n = 3 to 7 address read data address write data read write figure 9.30 8-bit access space acce ss timing (abwhn = 1, abwln = 1) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 253 of 1340 rej09b0499-0200 rd t ma1 t ma2 t 2 t 1 b address bus d15 to d0 d15 to d0 address cycle bus cycle data cycle csn lhwr llwr ah dack or edack bs rd/ wr note: n = 3 to 7 address read data address write data read write figure 9.31 16-bit access space acces s timing (abwhn = 0, abwln = 1) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 254 of 1340 rej09b0499-0200 9.9.6 address cycle control an extension cycle (tmaw) can be inserted be tween tma1 and tma2 cycles to extend the ah signal output period by setting the addex bit in mpxcr. by inserting the tmaw cycle, the address setup for ah and the ah minimum pulse width can be assured. figure 9.32 shows the access timing when the address cycle is three cycles. t ma1 t maw t ma2 t 2 t 1 b address bus d15 to d0 d15 to d0 address cycle data cycle csn lhwr llwr ah rd dack or edack bs rd/ wr note: n = 3 to 7 address read data address write data read write figure 9.32 access timing of 3 address cycles (addex = 1) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 255 of 1340 rej09b0499-0200 9.9.7 wait control in the data cycle of the address/data multiplexed i/o interface, program wait insertion and pin wait insertion by the wait pin are enabled in the same way as in the basic bus interface. for details, see section 9.6.4, wait control. wait control settings do not affect the address cycles. 9.9.8 read strobe ( rd ) timing in the address/data multiplexed i/o interface, the read strobe timing of data cycles can be modified in the same way as in basic bus interface. for details, see section 9.6.5, read strobe ( rd ) timing. figure 9.33 shows an example when the read strobe timing is modified. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 256 of 1340 rej09b0499-0200 t ma1 t ma2 t 2 t 1 b address bus d15 to d0 d15 to d0 address cycle data cycle csn rd ah rd dack or edack bs rd/ wr note: n = 3 to 7 address read data address read data rdnn = 0 rdnn = 1 figure 9.33 read strobe timing section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 257 of 1340 rej09b0499-0200 9.9.9 extension of chip select ( cs ) assertion period in the address/data multiplexed in terface, the extension cycles can be inserted before and after the bus cycle. for details, see section 9.6.6, extension of chip select ( cs ) assertion period. figure 9.34 shows an exam ple of the chip select ( cs ) assertion period extension timing. t ma1 t ma2 t 2 t t t 1 t h b address bus d15 to d0 d15 to d0 address cycle bus cycle data cycle csn lhwr llwr ah rd dack or edack bs rd/ wr note: n = 3 to 7 address read data address write data read write figure 9.34 chip select ( cs ) assertion period extensio n timing in data cycle section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 258 of 1340 rej09b0499-0200 when consecutively reading from the same area co nnected to a peripheral lsi whose data hold time is long, data outputs from the peripheral ls i and this lsi may conflict. inserting the chip select assertion period extension cycle afte r the access cycle can avoid the data conflict. figure 9.35 shows an example of the operation. in the figure, both bus cycles a and b are read access cycles to the address/data multiplexed i/o sp ace. an example of the da ta conflict is shown in (a), and an example of avoiding the data conflict by the cs assertion period extension cycle in (b). b address bus data bus bus cycle a bus cycle b cs ah rd (a) without cs assertion period extension cycle (csxtn = 0) (b) with cs assertion period extension cycle (csxtn = 1) data hold time is long. data conflict b address bus data bus bus cycle a bus cycle b cs ah rd figure 9.35 consecutive read accesses to same area (address/data multiplexed i/o space) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 259 of 1340 rej09b0499-0200 9.9.10 dack and edack signal output timings for dmac or exdmac single address transfers, the dack and edack signals assert timing can be modified by using the dkc and edkc bits in bcr1. figure 9.36 shows the dack and edack signal output timings. setting the dkc or edkc bit to 1 asserts the dack or edack signal a half cycle earlier. t ma1 t ma2 t 2 t 1 b dkc, edkc = 0 dkc, edkc = 1 address bus d15 to d0 d15 to d0 address cycle data cycle csn rd ah rd bs rd/ wr note: n = 3 to 7 address read data rdnn = 0 rdnn = 1 address read data dack or edack figure 9.36 dack and edack signal output timings section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 260 of 1340 rej09b0499-0200 9.10 idle cycle in this lsi, idle cycles can be inserted between the consecutive external ac cesses. by inserting the idle cycle, data conflicts between rom read cycl e whose output floating time is long and an access cycle from/to high-speed memory or i/o interface can be prevented. 9.10.1 operation when this lsi consecutively accesses external addres s space, it can insert an idle cycle between bus cycles in the following four cases. these co nditions are determined by the sequence of read and write and previously accessed area. 1. when read cycles of different areas in the external address sp ace occur consecutively 2. when an external write cycle occurs immediately after an external read cycle 3. when an external read cycle occurs immediately after an external write cycle 4. when an external access occurs immediat ely after a dmac or exdmac single address transfer (wr ite cycle) up to four idle cycles can be inserted under the conditions shown above. the number of idle cycles to be inserted should be specified to prevent data conflicts between the output data from a previously accessed device and data from a subsequently accessed device. under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of idle cycles can be selected from setting a specified by bits idlca1 and idlca0 in idlcr or setting b specified by bits idlcb1 and idlcb0 in idlcr: setting a can be selected from one to four cycles, and setting b can be selected from one or two to four cycles. setting a or b can be specified for each area by setting bits idlsel7 to idlsel0 in idlcr. note that bits idlsel7 to idlsel0 correspond to the previously accessed area of the consecutive accesses. the number of idle cycles to be inserted under conditions 3 and 4, which are conditions to insert idle cycles after write, can be determ ined by setting a as described above. after the reset release, idlcr is initialized to four idle cycle insertion under all conditions 1 to 4 shown above. table 9.20 shows the correspondence between conditions 1 to 4 and number of idle cycles to be inserted for each area. table 9.21 shows the corre spondence between the number of idle cycles to be inserted specified by settings a and b, and number of cycles to be inserted. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 261 of 1340 rej09b0499-0200 table 9.20 number of idle cycle in sertion selection in each area bit settings idlsn idlseln area for previous access insertion condition n setting n = 0 to 7 0 1 2 3 4 5 6 7 0 ? invalid 0 a a a a a a a a consecutive reads in different areas 1 1 1 b b b b b b b b 0 ? invalid 0 a a a a a a a a write after read 0 1 1 b b b b b b b b 0 invalid read after write 2 1 ? a 0 invalid external access after single address transfer 3 1 ? a [legend] a: number of idle cycle insertion a is selected. b: number of idle cycle insertion b is selected. invalid: no idle cycle is inserted for the corresponding condition. table 9.21 number of idle cycle insertions bit settings a b idlca1 idlca0 idlcb1 idlcb0 number of cycles ? ? 0 0 0 0 0 ? ? 1 0 1 0 1 2 1 0 1 0 3 1 1 1 1 4 section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 262 of 1340 rej09b0499-0200 (1) consecutive reads in different areas if consecutive reads in di fferent areas occur while bit idls1 in idlcr is set to 1, idle cycles specified by bits idlca1 and id lca0 when bit idlseln in idl cr is cleared to 0, or bits idlcb1 and idlcb0 when bit idls eln is set to 1 are inserted at the start of the second read cycle (n = 0 to 7). figure 9.37 shows an example of the operation in th is case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a read cycle for sram, each being located in a different area. in (a), an idle cycle is not inserted, and a conflict occurs in bus cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data conflict is prevented. data hold time is long. data conflict bus cycle a bus cycle b (a) no idle cycle inserted (idls1 = 0) (b) idle cycle inserted b address bus cs (area a) cs (area b) rd data bus t 1 t 2 t 3 t 1 t 2 bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 (idls1 = 1, idlseln = 0, idlca1 = 0, idlca0 = 0) figure 9.37 example of idle cycle operat ion (consecutive read s in different areas) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 263 of 1340 rej09b0499-0200 (2) write after read if an external write occurs after an external read while bit idls0 in idlcr is set to 1, idle cycles specified by bits idlca1 and idlca0 when bit idlseln in idlcr is cleared to 0 when idlseln = 0, or bits idlcb1 and idlcb0 when id lseln is set to 1 are inserted at the start of the write cycle (n = 0 to 7). figure 9.38 shows an example of the operation in th is case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a conflict occurs in bus cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data conflict is prevented. data hold time is long. data conflict bus cycle a bus cycle b b address bus cs (area a) cs (area b) rd llwr data bus t 1 t 2 t 3 t 1 t 2 (b) idle cycle inserted bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 (a) no idle cycle inserted (idls0 = 0) (idls0 = 1, idlseln = 0, idlca1 = 0, idlca0 = 0) figure 9.38 example of idle cy cle operation (write after read) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 264 of 1340 rej09b0499-0200 (3) read after write if an external read occurs after an external write while bit idls2 in idlcr is set to 1, idle cycles specified by bits idlca1 and idlca0 are inserted at the start of the read cycle (n = 0 to 7). figure 9.39 shows an example of the operation in this case. in this exampl e, bus cycle a is a cpu write cycle and bus cycle b is a read cycle from th e sram. in (a), an idle cycle is not inserted, and a conflict occurs in bus cycle b between the cpu write data and read data from an sram device. in (b), an idle cy cle is inserted, and a data conflict is prevented. output floating time is long. data conflict bus cycle a bus cycle b b address bus cs (area a) cs (area b) rd llwr data bus t 1 t 2 t 3 t 1 t 2 bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 (a) no idle cycle inserted (idls2 = 0) (b) idle cycle inserted (idls2 = 1, idlca1 = 0, idlca0 = 0) figure 9.39 example of idle cy cle operation (read after write) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 265 of 1340 rej09b0499-0200 (4) external access after sing le address transfer write if an external access occurs after a single addre ss transfer write while bit idls3 in idlcr is set to 1, idle cycles specified by bits idlca1 and idlca0 are inserted at the start of the external access (n = 0 to 7). figure 9.40 shows an example of the operation in this case. in this example, bus cycle a is a single address transfer (wr ite cycle) and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a conflict occurs in bus cycle b between the external device write data and this lsi write data. in (b), an idle cycle is inserted, and a data conflict is prevented. output floating time is long. data conflict bus cycle a bus cycle b (a) no idle cycle inserted (idls3 = 0) b address bus cs (area a) cs (area b) llwr dack or edack data bus t 1 t 2 t 3 t 1 t 2 (b) idle cycle inserted bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 (idls3 = 1, idlca1 = 0, idlca0 = 0) figure 9.40 example of idle cycle operation (write after single address transfer write) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 266 of 1340 rej09b0499-0200 (5) external nop cycles and idle cycles a cycle in which an external space is not accessed du e to internal operations is called an external nop cycle. even when an external nop cycle occu rs between consecutive ex ternal bus cycles, an idle cycle can be inserted. in this case, the numb er of external nop cycl es is included in the number of idle cycles to be inserted. figure 9.41 shows an example of external nop and idle cycle insertion. t 1 t 2 t 3 t pw t 1 t 2 t 3 t pw t i t i address bus no external access (nop) specified number of idle cycles or more including no external access cycles (nop) idle cycle (remaining) following bus cycle preceding bus cycle (condition: number of idle cycles to be inserted when different reads continue: 4 cycles) data bus b cs (area b) cs (area a) rd figure 9.41 idle cycle insertion example section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 267 of 1340 rej09b0499-0200 (6) relationship between chip select ( cs ) signal and read ( rd ) signal depending on the system's load conditions, the rd signal may lag behind the cs signal. an example is shown in figure 9.42. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the rd signal in bus cycle a and the cs signal in bus cycle b. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset releas e, idle cycle indicated in (b) is set. bus cycle a bus cycle b b address bus cs (area a) cs (area b) rd t 1 t 2 t 3 t 1 t 2 bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 overlap time may occur between the cs (area b) and rd (a) no idle cycle inserted (idls1 = 0) (b) idle cycle inserted (idls1 = 1, idlseln = 0, idlca1 = 0, idlca0 = 0) figure 9.42 relationship between chip select ( cs ) and read ( rd ) section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 268 of 1340 rej09b0499-0200 table 9.22 idle cycles in mi xed accesses to normal space idls idlsel idlca idlcb previous access next access 3 2 1 0 7 to 0 1 0 1 0 idle cycle ? ? 0 ? ? ? ? ? ? disabled normal space read normal space read ? ? 1 ? 0 0 0 ? ? 1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 1 ? ? 0 0 0 cycle inserted 0 1 2 cycle inserted 1 0 3 cycles inserted 1 1 4 cycles inserted ? ? ? 0 ? ? ? ? ? disabled normal space read normal space write ? ? ? 1 0 0 0 ? ? 1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 1 ? ? 0 0 0 cycle inserted 0 1 2 cycle inserted 1 0 3 cycles inserted 1 1 4 cycles inserted ? 0 ? ? ? ? ? ? ? disabled normal space write normal space read ? 1 ? ? ? 0 0 ? ? 1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 0 ? ? ? ? ? ? ? ? disabled single address transfer write normal space read 1 ? ? ? ? 0 0 ? ? 1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 269 of 1340 rej09b0499-0200 9.10.2 pin states in idle cycle table 9.23 shows the pin st ates in an idle cycle. table 9.23 pin states in idle cycle pins pin state a20 to a0 contents of following bus cycle d15 to d0 high impedance csn (n = 7 to 0) high as high rd high bs high rd/ wr high ah low lhwr , llwr high dackn (n = 3 to 0) high edackn (n = 1 to 0) high section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 270 of 1340 rej09b0499-0200 9.11 bus release this lsi can release the external bus in response to a bus request from an external device. in the external bus released state, inte rnal bus masters except the exdmac continue to operate as long as there is no external access. in addition, in the external bus released state, the breqo signal can be driven low to output a bus request externally. 9.11.1 operation in external extended mode, when the brle bit in bcr1 is set to 1 and the icr bits for the corresponding pin are set to 1, the bus can be released to the external. driving the breq pin low issues an external bus request to this lsi. when the breq pin is sampled, at the prescribed timing, the back pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing th e external bus released state. for details on ddr and icr, see section 13, i/o ports. in the external bus released state, the cpu, dtc, and dmac can access the internal space using the internal bus. when the cpu, dtc, dmac , or exdmac attempts to access the external address space, it temporarily defers initiation of th e bus cycle, and waits for the bus request from the external bus mast er to be canceled. if the breqoe bit in bcr1 is set to 1, the breqo pin can be driven low when any of the following requests are issued, to request ca ncellation of the bus request externally. ? when the cpu, dtc, dmac, or exdmac atte mpts to access the external address space ? when a sleep instruction is executed to place the chip in software standby mode or all- module-clock-stop mode ? when sckcr is written to for setting the clock frequency if an external bus release request and external access occur simultaneously, the priority is as follows: (high) exdmac > external bus release > ex ternal access by cpu, dtc, or dmac (low) when the breq pin is driven high, the back pin is driven high at the prescribed timing and the external bus released state is terminated. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 271 of 1340 rej09b0499-0200 9.11.2 pin states in external bus released state table 9.24 shows pin states in th e external bus released state. table 9.24 pin states in bus released state pins pin state a20 to a0 high impedance d15 to d0 high impedance bs high impedance csn (n = 7 to 0) high impedance as high impedance ah high impedance rd/ wr high impedance rd high impedance lub , llb high impedance lhwr , llwr high impedance dackn (n = 3 to 0) high level edackn (n = 1 to 0) high level section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 272 of 1340 rej09b0499-0200 9.11.3 transition timing figure 9.43 shows the timing for transition to the bus released state. b address bus csn lhwr , llwr as hi-z hi-z [1] [2] [3] [4] [7] [5] [6] [8] hi-z hi-z hi-z hi-z rd breq back breqo external space access cycle cpu cycle external bus released state data bus t 1 t 2 [1] a low level of the breq signal is sampled at the rising edge of the b signal. [2] the bus control signals are driven high at the end of the external space access cycle. it takes two cycles or more after the low level of the breq signal is sampled. [3] the back signal is driven low, releasing bus to the external bus master. [4] the breq signal state sampling is continued in the external bus released state. [5] a high level of the breq signal is sampled. [6] the external bus released cycles are ended one cycle after the breq signal is driven high. [7] when the external space is accessed by an internal bus master during external bus released while the breqoe bit is set to 1, the breqo signal goes low. [8] normally the breqo signal goes high at the rising edge of the back signal. figure 9.43 bus released state transition timing section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 273 of 1340 rej09b0499-0200 9.12 internal bus 9.12.1 access to internal address space the internal address spaces of this lsi are the on-chip rom space, on-chip ram space, and register space for the on-chip peripheral module s. the number of cycles necessary for access differs according the space. table 9.25 shows the number of access cycles for each on-chip memory space. table 9.25 number of access cycl es for on-chip memory spaces access space access number of access cycles read one i cycle on-chip rom space write three i cycles read one i cycle on-chip ram space write one i cycle in access to the registers for on -chip peripheral modul es, the number of access cycles differs according to the register to be accessed. when the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access in the same way as for external bus clock division. table 9.26 lists the number of access cycles for registers of on-chip peripheral modules. table 9.26 number of access cycles for registers of on-chip peripheral modules number of cycles module to be accessed read write write data buffer function dmac and exdmac registers two i two i disabled mcu operating mode, clock pulse generator, power-down control registers, interrupt controller, bus controller, and dtc registers two i three i disabled i/o port registers of pfcr and wdt two p three p disabled i/o port registers other than pfcr and portm, ppg0, tpu, tmr0, tmr1, sci0 to sci2, sci4, iic2, d/a, and a/d_0 registers two p two p enabled i/o port registers of portm, tmr2, tmr3, usb, sci5, sci6, a/d_1, and ppg1 registers three p three p enabled section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 274 of 1340 rej09b0499-0200 9.13 write data buffer function 9.13.1 write data buffer function for external data bus this lsi has a write data buffer function for the external data bus. using the write data buffer function enables internal accesses in parallel with external writes or dmac single address transfers. the write data buffer function is made available by setting the wdbe bit to 1 in bcr1. figure 9.44 shows an example of the timing when the write data buffer function is used. when this function is used, if an external address space write or a dmac single address transfer continues for two cycles or longer, and there is an internal access next, an exte rnal write only is executed in the first two cycles. however, fr om the next cycle onward, intern al accesses (on-chip memory or internal i/o register read/write) and the external address space write rather than waiting until it ends are executed in parallel. on-chip memory read peripheral module read peripheral module address external write cycle on-chip memory 2 on-chip memory 1 external address internal address bus b address bus csn lhwr , llwr d15 to d0 external space write t 1 t 2 t 3 i figure 9.44 example of timing when write data buffer function is used section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 275 of 1340 rej09b0499-0200 9.13.2 write data buffer function for peripheral modules this lsi has a write data buffer function for th e peripheral module access. using the write data buffer function enables peripheral module writes and on-chip memory or external access to be executed in parallel. the write data buffer function is made available by setting the pwdbe bit in bcr2 to 1. for details on the on-chip peripheral module registers, see table 9.26, number of access cycles for registers of on-chip peripheral modules in section 9.12, internal bus. figure 9.45 shows an example of the timing when the write data buffer function is used. when this function is used, if an internal i/o register write continues for two cycles or longer and then there is an on-chip ram, an on-chip rom, or an exte rnal access, internal i/o register write only is performed in the first two cycles. however, from the next cycle onward an internal memory or an external access and internal i/o regi ster write are executed in para llel rather than waiting until it ends. on-chip memory read peripheral module write peripheral module address internal address bus p i internal i/o address bus internal i/o data bus figure 9.45 example of timing when peripheral module write data buffer function is used section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 276 of 1340 rej09b0499-0200 9.14 bus arbitration this lsi has bus arbiters that arbitrate bus ma stership operations (bus arbitration). this lsi incorporates internal access and external access bu s arbiters that can be used and controlled independently. the internal bus arbiter handles the cpu, dtc, and dmac accesses. the external bus arbiter handles the external access by the cpu, dtc, and dmac, external access by the exdmac, and external bus release request (external bus master). the bus arbiters determine priorities at the prescr ibed timing, and permit use of the bus by means of the bus request acknowledge signal. 9.14.1 operation the bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the priority of the internal bus arbitration: (high) dmac > dtc > cpu (low) the priority of the exte rnal bus arbitration: (high) exdmac > external bus release reques t > external access by the cpu, dtc, and dmac (low) if the dmac or dtc accesses continue, the cpu ca n be given priority over the dmac or dtc to execute the bus cycles alternatively between them by setting the ibccs bit in bcr2. in this case, the priority between the dmac and dtc does not change. if the external bus release request or exdmac accesses continue, the external acce ss by the cpu, dtc, an d dmac can be given priority over the exdmac or exte rnal bus release request to execu te the bus cycles alternatively between them by setting the ebccs bit in bcr2. in this case, the priority between the exdmac and external bus release request does not change. an internal bus access by the cpu, dtc, or dm ac, an external bus access by an external bus release request, and an external bus access by the exdmac can be executed in parallel. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 277 of 1340 rej09b0499-0200 9.14.2 bus transfer timing even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately. there ar e specific timings at which each bu s master can release the bus. (1) cpu the cpu is the lowest-priority bus master, and if a bus request is received from the dtc or dmac, the internal bus arbiter transfers the bus to the bus master that issued the request. if an external bus cycle is executed by the cpu, the external bus ar biter transfers the bus to the exdmac that issued the request. the timing for transfer of the bus is at the end of the bu s cycle. in sleep mode, the bus is transferred synchronously with the clock. note, however, that the bu s cannot be transferred in the following cases. ? the word or longword access is performed in some divisions. ? stack handling is performed in multiple bus cycles. ? transfer data read or write by memory transfer instructions, block transfer instructions, or tas instruction. (in the block transfer instructions, the bus ca n be transferred in the write cycle and the following transfer data read cycle.) ? from the target read to write in the bit manipulation instructions or memory operation instructions. (in an instruction that performs no write operatio n according to the instruction condition, up to a cycle corresponding the write cycle) (2) dtc the dtc sends the internal bus arbiter a request for the bus wh en an activation request is generated. when the dtc accesses an external bu s space, the dtc first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. once the dtc takes control of the bus, the dtc co ntinues the transfer pro cessing cycles. if a bus master whose priority is higher than the dtc re quests the bus, the dtc transfers the bus to the higher priority bus master. if the ibccs bit in bcr2 is set to 1, the dtc transfers the bus to the cpu. note, however, that the bu s cannot be transferred in the following cases. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 278 of 1340 rej09b0499-0200 ? during transfer information read ? during the first data transfer ? during transfer information write back the dtc releases the bus when the cons ecutive transfer cy cles completed. (3) dmac the dmac sends the internal bus arbiter a request for the bus when an activation request is generated. when the dmac accesses an external bus space, the dmac first takes control of the bus from the internal bus arbiter and then requ ests a bus to the external bus arbiter. after the dmac takes control of the bus, it may con tinue the transfer proce ssing cycles or release the bus at the end of every bus cycle depending on the conditions. the dmac continues transfers without releasing the bus in the following case: ? between the read cycle in the dual-address mode and the write cycle corresponding to the read cycle if no bus master of a higher priority than the dmac requests the bus and the ibccs bit in bcr2 is cleared to 0, the dmac continues transfers w ithout releasing the bus in the following cases: ? during 1-block transfers in the block transfer mode ? during transfers in the burst mode in other cases, the dmac transfers th e bus at the end of the bus cycle. (4) exdmac the exdmac sends the external bus arbiter a requ est for the bus when an activation request is generated. during external access by the intern al bus master, the bus is transferred to the exdmac at the timing the bus can be transferred. after the exdmac takes control of the bus, it may continue the transfer processing cycles or release the bus at the end of every bu s cycle depending on the conditions. the exdmac continues transf ers without releasing the bu s in the following case: ? between the read cycle in the dual-address mode and the write cycle corresponding to the read cycle ? during transfers in the cluster transfer mode section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 279 of 1340 rej09b0499-0200 if no bus master of a higher priority than the exdmac requests the bus and the ebccs bit in bcr2 is cleared to 0, the exdmac continues tran sfers without releasing the bus in the following cases: ? during 1-block transfers in the block transfer mode ? during transfers in the burst mode in other cases, the exdmac transf ers the bus at the end of the bu s cycle. if startup requests are issued to the multiple exdmac channels when other bus masters do not request the bus, the exdmac takes control of the bus and continues to transfer processing cycles. (5) external bus release when the breq pin goes low and an external bus release request is issued while the brle bit in bcr1 is set to 1 with the corresponding icr bit set to 1, a bus request is sent to the bus arbiter. external bus release can be performed on completion of an ex ternal bus cycle. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 280 of 1340 rej09b0499-0200 9.15 bus controller operation in reset in a reset, this lsi, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 9.16 usage notes (1) setting registers the bsc registers must be specified before accessi ng the external address space. in on-chip rom disabled mode, the bsc registers must be specifie d before accessing the external address space for other than an instruction fetch access. (2) external bus release function and all-module-clock-stop mode in this lsi, if the acse bit in mstpcra is set to 1, and then a sleep instruction is executed with the setting for all peripheral module clocks to be stopped (mstpcra and mstpcrb = h'ffffffff) or for operation of the 8-bit timer module alone (mstpcra and mstpcrb = h'f[f to c]ffffff), and a transition is made to the sleep state, the all-module-clock-stop mode is entered in which the clock is also stopped for the bus controller and i/o ports. for details, see section 27, power-down modes. in this state, the external bus release function is halted. to use the external bus release function in sleep mode, the acse bit in mstpcra must be cl eared to 0. conversely, if a sleep instruction to place the chip in all-module-clo ck-stop mode is executed in the external bus released state, the transition to all-module-clock-stop mode is deferred and performed until after the bus is recovered. (3) external bus release function and software standby in this lsi, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip rom, et c., and no external access occurs. if a sleep instruction to place the chip in software standb y mode is executed whil e the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered. also, since clock oscillation halts in software standby mode, if the breq signal goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby mode. note that the back and breqo pins are both in the high-imped ance state in software standby mode. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 281 of 1340 rej09b0499-0200 (4) breqo output timing when the breqoe bit is set to 1 and the breqo signal is output, both the breqo and back signals may go low simultaneously. this will occur if the next external access request occurs while internal bus arbitration is in progress after the chip samples a low level of the breq signal. section 9 bus controller (bsc) rev. 2.00 oct. 20, 2009 page 282 of 1340 rej09b0499-0200 section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 283 of 1340 rej09b0499-0200 section 10 dma controller (dmac) this lsi includes a 4-chan nel dma controller (dmac). 10.1 features ? maximum of 4-g byte address space can be accessed ? byte, word, or longword can be set as data transfer unit ? maximum of 4-g bytes (4,294,967,295 bytes) can be set as total transfer size supports free-running mode in which tota l transfer size setting is not needed ? dmac activation methods are auto -request, on-chip module interr upt, and external request. auto request: cpu activates (cycle st ealing or burst access can be selected) on-chip module interrupt: interrupt requests from on-chip peripheral modules can be selected as an activation source external request: low level or falling edge detection of the dreq signal can be selected. external request is available for all four channels. ? dual or single address mode can be selected as address mode dual address mode: both source and de stination are specified by addresses single address mode: either source or destination is specified by the dack signal and the other is specified by address ? normal, repeat, or block transfer ca n be selected as transfer mode normal transfer mode: one byte, one word, or one longword data is transferred at a single transfer request repeat transfer mode: one byte, one word, or one longword data is transferred at a single transfer request repeat size of data is transfer red and then a transfer address returns to the transfer start address up to 65536 transfers (65,536 bytes/words/longwords) can be set as repeat size block transfer mode: one block data is transferred at a single transfer request up to 65,536 bytes/words/longwords can be set as block size section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 284 of 1340 rej09b0499-0200 ? extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available one bit (two bytes) to 27 bits (128 mbytes) for transfer source and destination can be set as extended repeat areas ? address update can be selected from fixed address, offset additio n, and increment or decrement by 1, 2, or 4 address update by offset addition enables to tr ansfer data at addresses which are not placed continuously ? word or longword data can be transferred to an address which is not aligned with the respective boundary data is divided according to its address (byte or word) when it is transferred ? two types of interrupts can be requested to the cpu a transfer end interrupt is genera ted after the number of data sp ecified by the transfer counter is transferred. a transfer esca pe end interrupt is generated wh en the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows. ? module stop state can be set. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 285 of 1340 rej09b0499-0200 a block diagram of the dmac is shown in figure 10.1. external pins dreqn dackn tendn interrupt signals requested to the cpu by each channel internal activation sources internal activation source detector controller dmdr_n dmrsr_n dacr_n dofr_n internal address bus internal data bus dsar_n ddar_n dtcr_n dbsr_n module data bus address buffer data buffer operation unit operation unit ... [legend] dsar_n: dma source address register dreqn : dma transfer request ddar_n: dma destination address register dackn : dma transfer acknowledge dofr_n: dma offset register tendn : dma transfer end dtcr_n: dma transfer count register n = 0 to 3 dbsr_n: dma block size register dmdr_n: dma mode control register dacr_n: dma address control register dmrsr_n: dma module request select register figure 10.1 block diagram of dmac section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 286 of 1340 rej09b0499-0200 10.2 input/output pins table 10.1 shows the pin configuration of the dmac. table 10.1 pin configuration channel pin name abbr. i/o function dma transfer request 0 dreq0 input channel 0 external request dma transfer acknowledge 0 dack0 output channel 0 single address transfer acknowledge 0 dma transfer end 0 tend0 output channel 0 transfer end dma transfer request 1 dreq1 input channel 1 external request dma transfer acknowledge 1 dack1 output channel 1 single address transfer acknowledge 1 dma transfer end 1 tend1 output channel 1 transfer end dma transfer request 2 dreq2 input channel 2 external request dma transfer acknowledge 2 dack2 output channel 2 single address transfer acknowledge 2 dma transfer end 2 tend2 output channel 2 transfer end dma transfer request 3 dreq3 input channel 3 external request dma transfer acknowledge 3 dack3 output channel 3 single address transfer acknowledge 3 dma transfer end 3 tend3 output channel 3 transfer end section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 287 of 1340 rej09b0499-0200 10.3 register descriptions the dmac has the following registers. channel 0: ? dma source address register_0 (dsar_0) ? dma destination address register_0 (ddar_0) ? dma offset register_0 (dofr_0) ? dma transfer count re gister_0 (dtcr_0) ? dma block size register_0 (dbsr_0) ? dma mode control register_0 (dmdr_0) ? dma address control register_0 (dacr_0) ? dma module request select register_0 (dmrsr_0) channel 1: ? dma source address register_1 (dsar_1) ? dma destination address register_1 (ddar_1) ? dma offset register_1 (dofr_1) ? dma transfer count re gister_1 (dtcr_1) ? dma block size register_1 (dbsr_1) ? dma mode control register_1 (dmdr_1) ? dma address control register_1 (dacr_1) ? dma module request select register_1 (dmrsr_1) channel 2: ? dma source address register_2 (dsar_2) ? dma destination address register_2 (ddar_2) ? dma offset register_2 (dofr_2) ? dma transfer count re gister_2 (dtcr_2) ? dma block size register_2 (dbsr_2) ? dma mode control register_2 (dmdr_2) ? dma address control register_2 (dacr_2) ? dma module request select register_2 (dmrsr_2) section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 288 of 1340 rej09b0499-0200 channel 3: ? dma source address register_3 (dsar_3) ? dma destination address register_3 (ddar_3) ? dma offset register_3 (dofr_3) ? dma transfer count re gister_3 (dtcr_3) ? dma block size register_3 (dbsr_3) ? dma mode control register_3 (dmdr_3) ? dma address control register_3 (dacr_3) ? dma module request select register_3 (dmrsr_3) 10.3.1 dma source address register (dsar) dsar is a 32-bit readable/writable register that specifies the transfer source address. dsar updates the transfer source addres s every time data is transferred. when ddar is specified as the destination address (the dirs bit in dacr is 1) in single address mode, dsar is ignored. although dsar can always be read from by the cpu, it must be read from in longwords and must not be written to while data for the channel is being transferred. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 289 of 1340 rej09b0499-0200 10.3.2 dma destination address register (ddar) ddar is a 32-bit readable/writable register that specifies the transfer de stination address. ddar updates the transfer destination ad dress every time data is transferre d. when dsar is specified as the source address (the dirs bit in dacr is 0) in single address mode, ddar is ignored. although ddar can always be read from by the cpu, it must be read from in longwords and must not be written to while data fo r the channel is being transferred. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 290 of 1340 rej09b0499-0200 10.3.3 dma offset register (dofr) dofr is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. although different values are specified for individual channels, the same values must be specified for the source an d destination sides of a single channel. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 291 of 1340 rej09b0499-0200 10.3.4 dma transfer count register (dtcr) dtcr is a 32-bit readable/writable register that speci fies the size of data to be transferred (total transfer size). to transfer 1-byte data in total, set h'00000001 in dtcr. when h'00000000 is set in this register, it means that the total transfer size is not specifie d and data is transferred with the tran sfer counter stopped (free running mo de). when h'ffffffff is set, the total transfer size is 4 gbytes (4,294,967,295), which is the maximum size. while data is being transferred, this register indicates the remaining transfer size. the value co rresponding to its data access size is subtracted every time data is transferred (byte: ? 1, word: ? 2, and longword: ? 4). although dtcr can always be read from by the cpu, it must be read from in longwords and must not be written to while data for the channel is being transferred. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 292 of 1340 rej09b0499-0200 10.3.5 dma block size register (dbsr) dbsr specifies the repeat size or block size. dbsr is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. 31 bkszh31 0 r/w 30 bkszh30 0 r/w 29 bkszh29 0 r/w 28 bkszh28 0 r/w 27 bkszh27 0 r/w 24 bkszh24 0 r/w 26 bkszh26 0 r/w 25 bkszh25 0 r/w bit bit name initial value r/w 23 bkszh23 0 r/w 22 bkszh22 0 r/w 21 bkszh21 0 r/w 20 bkszh20 0 r/w 19 bkszh19 0 r/w 16 bkszh16 0 r/w 18 bkszh18 0 r/w 17 bkszh17 0 r/w bit bit name initial value r/w 15 bksz15 0 r/w 14 bksz14 0 r/w 13 bksz13 0 r/w 12 bksz12 0 r/w 11 bksz11 0 r/w 8 bksz8 0 r/w 10 bksz10 0 r/w 9 bksz9 0 r/w bit bit name initial value r/w 7 bksz7 0 r/w 6 bksz6 0 r/w 5 bksz5 0 r/w 4 bksz4 0 r/w 3 bksz3 0 r/w 0 bksz0 0 r/w 2 bksz2 0 r/w 1 bksz1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 31 to 16 bkszh31 to bkszh16 all 0 r/w specify the repeat size or block size. when h'0001 is set, the repeat or block size is one byte, one word, or one longword. when h'0000 is set, it means the maximum value (refer to table 10.1). while the dma is in operation, the setting is fixed. 15 to 0 bksz15 to bksz0 all 0 r/w indicate the remaining repeat or block size while the dma is in operation. the value is decremented by 1 every time data is transferred. when the remaining size becomes 0, the value of t he bkszh bits is loaded. set the same value as the bkszh bits. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 293 of 1340 rej09b0499-0200 table 10.2 data access size, valid bits, and settable size mode data access size bkszh valid bits bksz valid bits settable size (byte) byte 1 to 65,536 word 2 to 131,072 repeat transfer and block transfer longword 31 to 16 15 to 0 4 to 262,144 10.3.6 dma mode control register (dmdr) dmdr controls the dmac operation. ? dmdr_0 31 dte 0 r/w 30 dacke 0 r/w 29 tende 0 r/w 28 ? 0 r/w 27 dreqs 0 r/w 24 ? 0 r 26 nrd 0 r/w 25 ? 0 r bit bit name initial value r/w 23 act 0 r 22 ? 0 r 21 ? 0 r 20 ? 0 r 19 errf 0 r/(w) * 16 dtif 0 r/(w) * 18 ? 0 r 17 esif 0 r/(w) * bit bit name initial value r/w 15 dtsz1 0 r/w 14 dtsz0 0 r/w 13 mds1 0 r/w 12 mds0 0 r/w 11 tseie 0 r/w 8 dtie 0 r/w 10 ? 0 r 9 esie 0 r/w bit bit name initial value r/w 7 dtf1 0 r/w 6 dtf0 0 r/w 5 dta 0 r/w 4 ? 0 r 3 ? 0 r 0 dmap0 0 r/w 2 dmap2 0 r/w 1 dmap1 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit after having been read as 1, to clear the flag. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 294 of 1340 rej09b0499-0200 ? dmdr_1 to dmdr_3 31 dte 0 r/w 30 dacke 0 r/w 29 tende 0 r/w 28 ? 0 r/w 27 dreqs 0 r/w 24 ? 0 r 26 nrd 0 r/w 25 ? 0 r bit bit name initial value r/w 23 act 0 r 22 ? 0 r 21 ? 0 r 20 ? 0 r 19 ? 0 r 16 dtif 0 r/(w) * 18 ? 0 r 17 esif 0 r/(w) * bit bit name initial value r/w 15 dtsz1 0 r/w 14 dtsz0 0 r/w 13 mds1 0 r/w 12 mds0 0 r/w 11 tseie 0 r/w 8 dtie 0 r/w 10 ? 0 r 9 esie 0 r/w bit bit name initial value r/w 7 dtf1 0 r/w 6 dtf0 0 r/w 5 dta 0 r/w 4 ? 0 r 3 ? 0 r 0 dmap0 0 r/w 2 dmap2 0 r/w 1 dmap1 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit after having been read as 1, to clear the flag. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 295 of 1340 rej09b0499-0200 bit bit name initial value r/w description 31 dte 0 r/w data transfer enable enables/disables a data transfer for the corresponding channel. when this bit is set to 1, it indicates that the dmac is in operation. setting this bit to 1 starts a transfer when the auto- request is selected. when the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. while data is being transferred, clearing this bit to 0 stops the transfer. in block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. if an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. operating modes and transfer methods must not be changed while this bit is set to 1. 0: disables a data transfer 1: enables a data transfer (dma is in operation) [clearing conditions] ? when the specified total transfer size of transfers is completed ? when a transfer is stopped by an overflow interrupt by a repeat size end ? when a transfer is stopped by an overflow interrupt by an extended repeat size end ? when a transfer is stopped by a transfer size error interrupt ? when clearing this bit to 0 to stop a transfer in block transfer mode, this bit changes after the current block transfer. ? when an address error or an nmi interrupt is requested ? in the reset state or hardware standby mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 296 of 1340 rej09b0499-0200 bit bit name initial value r/w description 30 dacke 0 r/w dack signal output enable enables/disables the dack signal output in single address mode. this bit is ignored in dual address mode. 0: disables dack signal output 1: enables dack signal output 29 tende 0 r/w tend signal output enable enables/disables the tend signal output. 0: disables tend signal output 1: enables tend signal output 28 ? 0 r/w reserved initial value should not be changed. 27 dreqs 0 r/w dreq select selects whether a low level or the falling edge of the dreq signal used in external request mode is detected. 0: low level detection 1: falling edge detection (the first transfer after a transfer enabled is detected on a low level) 26 nrd 0 r/w next request delay selects the accepting timing of the next transfer request. 0: starts accepting the next transfer request after completion of the current transfer 1: starts accepting the next transfer request one cycle of b after completion of the current transfer 25, 24 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 23 act 0 r active state indicates the operating state for the channel. 0: waiting for a transfer request or a transfer disabled state by clearing the dte bit to 0 1: active state 22 to 20 ? all 0 r reserved these bits are always read as 0 and cannot be modified. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 297 of 1340 rej09b0499-0200 bit bit name initial value r/w description 19 errf 0 r/(w) * system error flag indicates that an address error or an nmi interrupt has been generated. this bit is available only in dmdr_0. setting this bit to 1 prohibits writing to the dte bit for all the channels. this bit is reserved in dmdr_1 to dmdr_3. it is always read as 0 and cannot be modified. 0: an address error or an nmi interrupt has not been generated 1: an address error or an nmi interrupt has been generated [clearing condition] ? when clearing to 0 after reading errf = 1 [setting condition] ? when an address error or an nmi interrupt has been generated however, when an address error or an nmi interrupt has been generated in dmac module stop mode, this bit is not set to 1. 18 ? 0 r reserved this bit is always read as 0 and cannot be modified. 17 esif 0 r/(w) * transfer escape interrupt flag indicates that a transfer escape end interrupt has been requested. a transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: a transfer escape end interrupt has not been requested 1: a transfer escape end interrupt has been requested [clearing conditions] ? when setting the dte bit to 1 ? when clearing to 0 before reading esif = 1 [setting conditions] ? when a transfer size error interrupt is requested ? when a repeat size end interrupt is requested ? when a transfer end interrupt by an extended repeat area overflow is requested section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 298 of 1340 rej09b0499-0200 bit bit name initial value r/w description 16 dtif 0 r/(w) * data transfer interrupt flag indicates that a transfer end interrupt by the transfer counter has been requested. 0: a transfer end interrupt by the transfer counter has not been requested 1: a transfer end interrupt by the transfer counter has been requested [clearing conditions] ? when setting the dte bit to 1 ? when clearing to 0 after reading dtif = 1 [setting condition] ? when dtcr reaches 0 and the transfer is completed 15 14 dtsz1 dtsz0 0 0 r/w r/w data access size 1 and 0 select the data access size for a transfer. 00: byte size (eight bits) 01: word size (16 bits) 10: longword size (32 bits) 11: setting prohibited 13 12 mds1 mds0 0 0 r/w r/w transfer mode select 1 and 0 select the transfer mode. 00: normal transfer mode 01: block transfer mode 10: repeat transfer mode 11: setting prohibited section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 299 of 1340 rej09b0499-0200 bit bit name initial value r/w description 11 tseie 0 r/w transfer size error interrupt enable enables/disables a transfer size error interrupt. when the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the dte bit is cleared to 0. at this time, the esif bit is set to 1 to indica te that a transfer size error interrupt has been requested. the sources of a transfer size error are as follows: ? in normal or repeat transfer mode, the total transfer size set in dtcr is less than the data access size ? in block transfer mode, the total transfer size set in dtcr is less than the block size 0: disables a transfer size error interrupt request 1: enables a transfer size error interrupt request 10 ? 0 r reserved this bit is always read as 0 and cannot be modified. 9 esie 0 r/w transfer escape interrupt enable enables/disables a transfer escape end interrupt request. when the esif bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the cpu or dtc. the transfer end interrupt request is cleared by clearing this bit or the esif bit to 0. 0: disables a transfer escape end interrupt 1: enables a transfer escape end interrupt 8 dtie 0 r/w data transfer end interrupt enable enables/disables a transfer end interrupt request by the transfer counter. when the dtif bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the cpu or dtc. the transfer end interrupt request is cleared by clearing this bit or the dtif bit to 0. 0: disables a transfer end interrupt 1: enables a transfer end interrupt section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 300 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 6 dtf1 dtf0 0 0 r/w r/w data transfer factor 1 and 0 select a dmac activation source. when the on-chip peripheral module setting is selected, the interrupt source should be selected by dmrsr. when the external request setting is selected, the sampling method should be selected by the dreqs bit. 00: auto request (cycle stealing) 01: auto request (burst access) 10: on-chip module interrupt 11: external request 5 dta 0 r/w data transfer acknowledge this bit is valid in dma transfer by the on-chip module interrupt source. this bit enables or disables to clear the source flag selected by dmrsr. 0: to clear the source in dma transfer is disabled. since the on-chip module interrupt source is not cleared in dma transfer, it should be cleared by the cpu or dtc transfer. 1: to clear the source in dma transfer is enabled. since the on-chip module interrupt source is cleared in dma transfer, it does not require an interrupt by the cpu or dtc transfer. 4, 3 ? all 0 r reserved these bits are always read as 0 and cannot be modified. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 301 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 1 0 dmap2 dmap1 dmap0 0 0 0 r/w r/w r/w dma priority level 2 to 0 select the priority level of the dmac when using the cpu priority control function over dmac. when the cpu has priority over the dmac, the dmac masks a transfer request and waits for the timing when the cpu priority becomes lower than the dmac priority. the priority levels can be set to the individual channels. this bit is valid when the cpupce bit in cpupcr is set to 1. 000: priority level 0 (low) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (high) note: * only 0 can be written to, to clear the flag. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 302 of 1340 rej09b0499-0200 10.3.7 dma address control register (dacr) dacr specifies the operating mode and transfer method. 31 ams 0 r/w 30 dirs 0 r/w 29 ? 0 r 28 ? 0 r 27 ? 0 r 24 ars0 0 r/w 26 rptie 0 r/w 25 ars1 0 r/w bit bit name initial value r/w 23 ? 0 r 22 ? 0 r 21 sat1 0 r/w 20 sat0 0 r/w 19 ? 0 r 16 dat0 0 r/w 18 ? 0 r 17 dat1 0 r/w bit bit name initial value r/w 15 sarie 0 r/w 14 ? 0 r 13 ? 0 r 12 sara4 0 r/w 11 sara3 0 r/w 8 sara0 0 r/w 10 sara2 0 r/w 9 sara1 0 r/w bit bit name initial value r/w 7 darie 0 r/w 6 ? 0 r 5 ? 0 r 4 dara4 0 r/w 3 dara3 0 r/w 0 dara0 0 r/w 2 dara2 0 r/w 1 dara1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 31 ams 0 r/w address mode select selects address mode from single or dual address mode. in single address mode, the dack pin is enabled according to the dacke bit. 0: dual address mode 1: single address mode 30 dirs 0 r/w single address direction select specifies the data transfer direction in single address mode. this bit s ignored in dual address mode. 0: specifies dsar as source address 1: specifies ddar as destination address 29 to 27 ? 0 r/w reserved these bits are always read as 0 and cannot be modified. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 303 of 1340 rej09b0499-0200 bit bit name initial value r/w description 26 rptie 0 r/w repeat size end interrupt enable enables/disables a repeat size end interrupt request. in repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the dte bit in dmdr is cleared to 0. at this time, the esif bit in dmdr is set to 1 to indicate that a repeat size end interrupt is requested. even when the re peat area is not specified (ars1 = 1 and ars0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. in addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the dte bit in dmdr is cleared to 0. at this time, the esif bit in dmdr is set to 1 to indicate that a repeat size end interrupt is requested. 0: disables a repeat size end interrupt 1: enables a repeat size end interrupt 25 24 ars1 ars0 0 0 r/w r/w area select 1 and 0 specify the block area or repeat area in block or repeat transfer mode. 00: specify the block area or repeat area on the source address 01: specify the block area or repeat area on the destination address 10: do not specify the block area or repeat area 11: setting prohibited 23, 22 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 21 20 sat1 sat0 0 0 r/w r/w source address update mode 1 and 0 select the update method of the source address (dsar). when dsar is not specified as the transfer source in single address mode, this bit is ignored. 00: source address is fixed 01: source address is updated by adding the offset 10: source address is updated by adding 1, 2, or 4 according to the data access size 11: source address is updated by subtracting 1, 2, or 4 according to the data access size section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 304 of 1340 rej09b0499-0200 bit bit name initial value r/w description 19, 18 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 17 16 dat1 dat0 0 0 r/w r/w destination address update mode 1 and 0 select the update method of the destination address (ddar). when ddar is not specified as the transfer destination in single address mode, this bit is ignored. 00: destination address is fixed 01: destination address is upda ted by adding the offset 10: destination address is upda ted by adding 1, 2, or 4 according to the data access size 11: destination address is upda ted by subtracting 1, 2, or 4 according to the data access size 15 sarie 0 r/w interrupt enable for source address extended area overflow enables/disables an interrupt request for an extended area overflow on the source address. when an extended repeat area overflow on the source address occurs while this bit is set to 1, the dte bit in dmdr is cleared to 0. at this time, the esif bit in dmdr is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. when block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. when setting the dte bit in dmdr of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. when the extended repeat area is not specified, this bit is ignored. 0: disables an interrupt request for an extended area overflow on the source address 1: enables an interrupt request for an extended area overflow on the source address 14, 13 ? all 0 r reserved these bits are always read as 0 and cannot be modified. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 305 of 1340 rej09b0499-0200 bit bit name initial value r/w description 12 11 10 9 8 sara4 sara3 sara2 sara1 sara0 0 0 0 0 0 r/w r/w r/w r/w r/w source address extended repeat area specify the extended repeat area on the source address (dsar). with the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. the extended repeat area size is specified from four bytes to 128 mbytes in units of byte and a power of 2. when the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. when an overflow in the extended repeat area occurs with the sarie bit set to 1, an interrupt can be requested. table 10.3 shows the settings and areas of the extended repeat area. 7 darie 0 r/w destination address extended repeat area overflow interrupt enable enables/disables an interrupt request for an extended area overflow on the destination address. when an extended repeat area overflow on the destination address occurs while this bit is set to 1, the dte bit in dmdr is cleared to 0. at this time, the esif bit in dmdr is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. when block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. when setting the dte bit in dmdr of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. when the extended repeat area is not specified, this bit is ignored. 0: disables an interrupt request for an extended area overflow on the destination address 1: enables an interrupt request for an extended area overflow on the destination address 6, 5 ? all 0 r reserved these bits are always read as 0 and cannot be modified. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 306 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 3 2 1 0 dara4 dara3 dara2 dara1 dara0 0 0 0 0 0 r/w r/w r/w r/w r/w destination address extended repeat area specify the extended rep eat area on the destination address (ddar). with the ex tended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. the extended repeat area size is specified from four bytes to 128 mbytes in units of byte and a power of 2. when the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. when an overflow in the extended repeat area occurs with the darie bit set to 1, an interrupt can be requested. table 10.3 shows the settings and areas of the extended repeat area. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 307 of 1340 rej09b0499-0200 table 10.3 settings and area s of extended repeat area sara4 to sara0 or dara4 to dara0 extended repeat area 00000 not specified 00001 2 bytes specified as extended repeat area by the lower 1 bit of the address 00010 4 bytes specified as extended repeat area by the lower 2 bits of the address 00011 8 bytes specified as extended repeat area by the lower 3 bits of the address 00100 16 bytes specified as extended repeat area by the lower 4 bits of the address 00101 32 bytes specified as extended repeat area by the lower 5 bits of the address 00110 64 bytes specified as extended repeat area by the lower 6 bits of the address 00111 128 bytes specified as extended repeat area by the lower 7 bits of the address 01000 256 bytes specified as extended repeat area by the lower 8 bits of the address 01001 512 bytes specified as extended repeat area by the lower 9 bits of the address 01010 1 kbyte specified as extended repeat area by the lower 10 bits of the address 01011 2 kbytes specified as extended repeat area by the lower 11 bits of the address 01100 4 kbytes specified as extended repeat area by the lower 12 bits of the address 01101 8 kbytes specified as extended repeat area by the lower 13 bits of the address 01110 16 kbytes specified as extended repeat ar ea by the lower 14 bits of the address 01111 32 kbytes specified as extended repeat ar ea by the lower 15 bits of the address 10000 64 kbytes specified as extended repeat ar ea by the lower 16 bits of the address 10001 128 kbytes specified as extended repeat area by the lower 17 bits of the address 10010 256 kbytes specified as extended repeat area by the lower 18 bits of the address 10011 512 kbytes specified as extended repeat area by the lower 19 bits of the address 10100 1 mbyte specified as extended repeat area by the lower 20 bits of the address 10101 2 mbytes specified as extended repeat area by the lower 21 bits of the address 10110 4 mbytes specified as extended repeat area by the lower 22 bits of the address 10111 8 mbytes specified as extended repeat area by the lower 23 bits of the address 11000 16 mbytes specified as extended repeat ar ea by the lower 24 bits of the address 11001 32 mbytes specified as extended repeat ar ea by the lower 25 bits of the address 11010 64 mbytes specified as extended repeat ar ea by the lower 26 bits of the address 11011 128 mbytes specified as extended repeat area by the lower 27 bits of the address 111 setting prohibited [legend] : don't care section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 308 of 1340 rej09b0499-0200 10.3.8 dma module request select register (dmrsr) dmrsr is an 8-bit readable/writable register th at specifies the on-chip module interrupt source. the vector number of the interrupt source is specified in eight bits. however, 0 is regarded as no interrupt source. for the vector numbers of the interrupt sources, refer to table 10.5. 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 309 of 1340 rej09b0499-0200 10.4 transfer modes table 10.4 shows the dmac transfer modes. the transfer modes can be specified to the individual channels. table 10.4 transfer modes address register address mode transfer mode activati on source common function source destina- tion dual address ? normal transfer ? repeat transfer ? block transfer repeat or block size = 1 to 65,536 bytes, 1 to 65,536 words, or 1 to 65,536 longwords ? auto request (activated by cpu) ? on-chip module interrupt ? external request ? total transfer size: 1 to 4 gbytes or not specified ? offset addition ? extended repeat area function dsar ddar single address ? instead of specifying the source or destination address registers, data is directly tr ansferred from/to the external device using the dack pin ? the same settings as above are available other than address register setting (e.g., above transfer modes can be specified) ? one transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes) dsar/ dack dack / ddar when the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. when the total transfer size is not specified (dtcr = h'00000000), the transfer counter is stopped and the transfer is continue d without the limitation of the transfer count. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 310 of 1340 rej09b0499-0200 10.5 operations 10.5.1 address modes (1) dual address mode in dual address mode, the transfer source address is specified in ds ar and the transfer destination address is specified in ddar. a tr ansfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more th an two because one bus cycle is divided into multiple bus cycles). in the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. the read and write cycles are not separated. othe r bus cycles (bus cycle by other bus masters, refresh cycle, and extern al bus release cycle) are not generated between read and write cycles. the tend signal output is enabled or disabled by the tende bit in dmdr. the tend signal is output in two bus cycles. when an idle cycle is inserted before the bus cycle, the tend signal is also output in the idle cycle. the dack signal is not output. figure 10.2 shows an example of the signal timing in dual address mode and figure 10.3 shows the operation in dual address mode. address bus b rd wr tend dma read cycle dma write cycle dsar ddar figure 10.2 example of signal timing in dual address mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 311 of 1340 rej09b0499-0200 transfer address t a address b a address update setting is as follows: source address increment fixed destination address address t b figure 10.3 operations in dual address mode (2) single address mode in single address mode, data between an external device and an external memory is directly transferred using the dack pin instead of dsar or ddar. a transfer at a time is performed in one bus cycle. in this mode, the data bus widt h must be the same as the data access size. for details on the data bus width, see section 9, bus controller (bsc). the dmac accesses an external device as the tr ansfer source or destination by outputting the strobe signal ( dack ) to the external device with dack and accesses the other transfer target by outputting the address. accordingly, the dma transfer is performed in one bus cycle. figure 10.4 shows an example of a transfer between an exte rnal memory and an external device with the dack pin. in this example, the external device outputs data on the data bus and the data is written to the external memory in the same bus cycle. the transfer direction is decided by the dirs bit in dacr which sp ecifies an external device with the dack pin as the transfer source or destination. when dirs = 0, data is transferred from an external memory (dsar) to an external device with the dack pin. when dirs = 1, data is transferred from an ex ternal device with the dack pin to an external memory (ddar). the settings of registers which are not used as th e transfer source or de stination are ignored. the dack signal output is enabled in single address mode by the dacke bit in dmdr. the dack signal is low active. the tend signal output is enabled or disabled by the tende bit in dmdr. the tend signal is output in one bus cycle. when an idle cycl e is inserted before the bus cycle, the tend signal is also output in the idle cycle. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 312 of 1340 rej09b0499-0200 figure 10.5 shows an example of timing charts in single address mode and figure 10.6 shows an example of operation in single address mode. lsi data flow external address bus external data bus dmac dack dreq external memory external device with dack figure 10.4 data flow in single address mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 313 of 1340 rej09b0499-0200 dma cycle dsar address for external memory space rd signal for external memory space data output by external memory address bus b rd wr dack tend data bus dma cycle ddar address for external memory space wr signal for external memory space b address bus transfer from external memory to external device with dack rd wr dack tend data bus data output by external device with dac k transfer from external device with dack to external memory high high figure 10.5 example of signal timing in single address mode transfer address t address b dac k figure 10.6 operations in single address mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 314 of 1340 rej09b0499-0200 10.5.2 transfer modes (1) normal transfer mode in normal transfer mode, one data access size of data is transferred at a single transfer request. up to 4 gbytes can be specified as a total transfer size by dtcr. dbsr is ignored in normal transfer mode. the tend signal is output only in the last dma transfer. figure 10.7 shows an example of the signal timing in normal transfer mode and figure 10.8 shows the operation in norm al transfer mode. read write read write dma transfer cycle last dma transfer cycle bus cycle auto request transfer in dual address mode: external request transfer in single address mode: tend dma dma dreq bus cycle dack figure 10.7 example of signal timing in normal transfer mode transfer total transfer size (dtcr) address t a address b a address t b address b b figure 10.8 operations in normal transfer mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 315 of 1340 rej09b0499-0200 (2) repeat transfer mode in repeat transfer mode, one data access size of data is transferred at a singl e transfer request. up to 4 gbytes can be specified as a total transfer size by dtcr. the repeat size can be specified in dbsr up to 65536 data access size. the repeat area can be specified for the source or destination address side by bits ars1 and ars0 in dacr. the addr ess specified as the repeat area returns to the transfer star t address when the repeat size of transfers is comp leted. this operation is repeated until the total transfer size specified in dtcr is completed. when h'00000000 is specified in dtcr, it is regarded as the free running mode and repeat tran sfer is continued until the dte bit in dmdr is cleared to 0. in addition, a dma transfer can be stopped and a repeat size end interrupt can be requested to the cpu or dtc when the repeat size of transfers is completed. when the next transfer is requested after completion of a 1-repeat size data transfer while the rptie bit is set to 1, the dte bit in dmdr is cleared to 0 and the esif bit in dmdr is set to 1 to complete the transfer. at this time, an interrupt is requested to the cpu or dtc when the esie bit in dmdr is set to 1. the timing of the tend signal is the same as in normal transfer mode. figure 10.9 shows the operation in repeat transfer mode while dual address mode is set. when the repeat area is specified as neither source nor destination address side, the operation is the same as the normal transfer mode operation sh own in figure 10.8. in this case, a repeat size end interrupt can also be request ed to the cpu when the repeat size of transfers is completed. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 316 of 1340 rej09b0499-0200 transfer address t a address t b address b b address b a operation when the repeat area is specified to the source side repeat size = bkszh data access size total transfer size (dtcr) figure 10.9 operations in repeat transfer mode (3) block transfer mode in block transfer mode, one block size of data is transferred at a single transfer request. up to 4 gbytes can be specified as total transfer size by dtcr. the block size can be specified in dbsr up to 64 k data access size. while one block of data is being transferred, transfer requests from other channels are suspended. when the transfer is completed, the bu s is released to the other bus master. the block area can be specified fo r the source or destination address side by bits ars1 and ars0 in dacr. the addres s specified as the block area returns to the transfer star t address when the block size of data is completed. when the block area is specified as neither source nor destination address side, the operation continues without return ing the address to the tr ansfer start address. a repeat size end interrupt can be requested. the tend signal is output every time 1-block data is transferred in the last dma transfer cycle. when an interrupt request by an extended repeat area overflow is used in block transfer mode, settings should be selected carefully. for deta ils, see section 10.5.5, extended repeat area function. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 317 of 1340 rej09b0499-0200 figure 10.10 shows an example of the dma transfer timing in block transfer mode. the transfer conditions are as follows: ? address mode: single address mode ? data access size: byte ? 1-block size: three bytes the block transfer mode operations in single address mode and in dual address mode are shown in figures 10.11 and 10.12, respectively. cpu cpu dmac dmac dmac cpu bus cycle tend dreq no cpu cycle generated transfer cycles for one block figure 10.10 operations in block transfer mode transfer address t address b dac k block bkszh data access size figure 10.11 operation in single a ddress mode in block transfer mode (block area specified) section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 318 of 1340 rej09b0499-0200 transfer address t a address b a address t b address b b nth block second block first block nth block second block first block bkszh data access size total transfer size (dtcr) figure 10.12 operation in dual a ddress mode in block transfer mode (block area not specified) section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 319 of 1340 rej09b0499-0200 10.5.3 activation sources the dmac is activated by an auto request, an on -chip module interrupt, and an external request. the activation source is specified by bits dtf1 and dtf0 in dmdr. (1) activation by auto request the auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. a transfer request is automatically generated inside the dmac. in auto request activation, setting the dte bit in dmdr starts a transfer. the bus mode can be selected from cycle steal ing and burst modes. (2) activation by on-chip module interrupt an interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. when a dma transfer is enabled (dte = 1), the dma transfer is started by an on-chip module interrupt. the activation source of the on-chip module inte rrupt is selected by the dma module request select register (dmrsr). the ac tivation sources are specified to the individual channels. table 10.5 is a list of on-chip module interrupts for the dmac. the interrupt request selected as the activation source can generate an interrupt request simultaneously to the cpu or dtc. for details, refer to section 7, interrupt controller. the dmac receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. therefore, the dmac is not affected by priority given in the interrupt controller. when the dmac is activated while dta = 1, the in terrupt request flag is automatically cleared by a dma transfer. if multiple channels use a single transfer request as an activation source, when the channel having priority is activated, the interr upt request flag is cleared. in this case, other channels may not be activated because the tr ansfer request is not held in the dmac. when the dmac is activated while dta = 0, the interrupt request flag is not cleared by the dmac and should be cleared by the cpu or dtc transfer. when an activation source is selected while dte = 0, the activation source does not request a transfer to the dmac. it requests an interrupt to the cpu or dtc. in addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the dte bit. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 320 of 1340 rej09b0499-0200 table 10.5 list of on-chi p module interrupts to dmac on-chip module interrupt source on-chip module dmrsr (vector number) adi0 (conversion end interrupt for a/d_0 converter unit 0) a/d_0 86 tgi0a (tgi0a input capture/compare match) tpu_0 88 tgi1a (tgi1a input capture/compare match) tpu_1 93 tgi2a (tgi2a input capture/compare match) tpu_2 97 tgi3a (tgi3a input capture/compare match) tpu_3 101 tgi4a (tgi4a input capture/compare match) tpu_4 106 tgi5a (tgi5a input capture/compare match) tpu_5 110 rxi0 (receive data full interrupt for sci channel 0) sci_0 145 txi0 (transmit data empty interr upt for sci channel 0) sci_0 146 rxi1 (receive data full interrupt for sci channel 1) sci_1 149 txi1 (transmit data empty interr upt for sci channel 1) sci_1 150 rxi2 (receive data full interrupt for sci channel 2) sci_2 153 txi2 (transmit data empty interr upt for sci channel 2) sci_2 154 rxi4 (receive data full interrupt for sci channel 4) sci_4 161 txi4 (transmit data empty interr upt for sci channel 4) sci_4 162 tgi6a (tgi6a input capture/compare match) tpu_6 164 tgi7a (tgi7a input capture/compare match) tpu_7 169 tgi8a (tgi8a input capture/compare match) tpu_8 173 tgi9a (tgi9a input capture/compare match) tpu_9 177 tgi10a (tgi10a input capture/compare match) tpu_10 182 tgi11a (tgi11a input capture/compare match) tpu_11 188 rxi5 (receive data full interrupt for sci channel 5) sci_5 220 txi5 (transmit data empty interr upt for sci channel 5) sci_5 221 rxi6 (receive data full interrupt for sci channel 6) sci_6 224 txi6 (transmit data empty interr upt for sci channel 6) sci_6 225 usbintn0 (ep1fifo full interrupt) usb 232 usbintn1 (ep2fifo empty interrupt) usb 233 adi1 (conversion end interrupt for a/d converter unit 1) a/d_1 237 section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 321 of 1340 rej09b0499-0200 (3) activation by external request a transfer is started by a transfer request signal ( dreq ) from an external device. when a dma transfer is enabled (dte = 1), th e dma transfer is started by the dreq assertion. when a dma transfer between on-chip peripheral modules is performed, select an activ ation source from the auto request and on-chip module interrupt (the external request cannot be used). a transfer request signal is input to the dreq pin. the dreq signal is detected on the falling edge or low level. whether the falling edge or low level detection is used is selected by the dreqs bit in dmdr. when an external request is selected as an ac tivation source, clear the ddr bit to 0 and set the icr bit to 1 for the corresponding pin. for details, see section 13, i/o ports. 10.5.4 bus access modes there are two types of bus access modes: cycle stealing and burst. when an activation source is the au to request, the cycle stealing or burst mode is selected by bit dtf0 in dmdr. when an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) cycle stealing mode in cycle stealing mode, the dmac releases the bus every time one unit of transfers ( byte, word, longword, or 1-block size) is completed. after that, when a transfer is requested, the dmac obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. this operation is continued until the transfer end condition is satisfied. when a transfer is requested to another channel during a dma transfer, the dmac releases the bus and then transfers data for the requested channel. for details on operations when a transfer is requested to multiple channels, see section 10.5.8, priority of channels. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 322 of 1340 rej09b0499-0200 figure 10.13 shows an example of timing in cycl e stealing mode. the tran sfer conditions are as follows: ? address mode: single address mode ? sampling method of the dreq signal: low level detection cpu cpu cpu dmac cpu dmac dreq bus cycle bus released temporarily for the cpu figure 10.13 example of ti ming in cycle stealing mode (2) burst access mode in burst mode, once it takes the bus, the dmac con tinues a transfer without releasing the bus until the transfer end condition is satisfied. even if a transfer is requested from another channel having priority, the transfer is not stopped once it is star ted. the dmac releases th e bus in the next cycle after the transfer for the channel in burst mode is completed. this is similarly to operation in cycle stealing mode. however, setting the ibccs bit in bcr2 of the bus controller makes the dmac release the bus to pass the bus to another bus master. in block transfer mode, the burst mode setting is i gnored (operation is the same as that in burst mode during one block of transfers). the dmac is always operated in cycle stealing mode. clearing the dte bit in dmdr stops a dma transfer . a transfer requested before the dte bit is cleared to 0 by the dmac is execu ted. when an interrupt by a tran sfer size error, a repeat size end, or an extended repeat area overflow occurs, the dte bit is cl eared to 0 and the transfer ends. figure 10.14 shows an example of timing in burst mode. cpu cpu cpu cpu dmac dmac dmac bus cycle no cpu cycle generated figure 10.14 example of timing in burst mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 323 of 1340 rej09b0499-0200 10.5.5 extended repeat area function the source and destination address sides can be speci fied as the extended repeat area. the contents of the address register repeat ad dresses within the area specified as the extended repeat area. for example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every tim e the contents reach the end address of the buffer (overflow on the ring buffer address). this operation can automatically be performed using the extended repeat area function of the dmac. the extended repeat areas can be specified inde pendently to the source a ddress register (dsar) and destination address register (ddar). the extended repeat area on the source address is specified by bits sara4 to sara0 in dacr. the extended repeat area on the destination ad dress is specified by bits dara4 to dara0 in dacr. the extended repeat area sizes for ea ch side can be specified independently. a dma transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the cpu when the contents of the address regist er reach the end address of the extended repeat area. when an overflow on the extended repeat area set in dsar occurs while the sarie bit in dacr is set to 1, the esif bit in dmdr is set to 1 and the dte bit in dmdr is cleared to 0 to stop the transfer. at this time, if the esie bit in dmdr is set to 1, an interrupt by an extended repeat area overflow is requested to the cpu. when the darie bit in dacr is set to 1, an overflow on the extended repeat area set in ddar occurs, meaning that the destination side is a target. during the interrupt handling, setting the dte bit in dmdr resumes the transfer. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 324 of 1340 rej09b0499-0200 figure 10.15 shows an example of th e extended repeat area operation. external memory when the area represented by the lower three bits of dsar (eight bytes) is specified as the extended repeat area (sara4 to sara0 = b'00011) repeat an interrupt request by extended repeat area overflow can be generated. area specified by dsar h'23fffe h'23ffff h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240008 h'240009 h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 ... ... figure 10.15 example of extended repeat area operation when an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. when a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. when an overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended and the transfer overruns. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 325 of 1340 rej09b0499-0200 figure 10.16 shows examples when the extended repeat area function is used in block transfer mode. external memory area specified by dsar 1st block transfer 2nd block transfer h'23fffe h'23ffff h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240008 h'240009 h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240000 h'240001 h'240002 h'240003 h'240004 h'240000 h'240001 h'240005 h'240006 h'240007 interrupt request generated block transfer continued when the are represented by the lower three bits (eight bytes) of dsar are specified as the extended repeat area (sara4 to sara0 = 3) and the block size in block transfer mode is specified to 5 (bits 23 to 16 in dtcr = 5). ... ... figure 10.16 example of extended repeat area function in block transfer mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 326 of 1340 rej09b0499-0200 10.5.6 address update function using offset the source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. when the offset addition is select ed, the offset specified by the offset register (dofr) is added to the address every time the dm ac transfers the data access size of data. this function realizes a data transfer where ad dresses are allocated to separated areas. figure 10.17 shows the address update method. 0 + offset 1, 2, or 4 address not updated data access size added to or subtracted from address (addresses are continuous) offset is added to address (addresses are not continuous) (a) address fixed (b) increment or decrement by 1, 2, or 4 (c) offset addition external memory external memory external memory figure 10.17 address update method in item (a), address fixed, the transfer source or destination address is not updated indicating the same address. in item (b), increment or decrem ent by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. byte, word, or longword can be specified as the data access size. the value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. th is operation realizes the data transfer placed in consecutive areas. in item (c), offset addition, th e address update does not depend on the data access size. the offset specified by dofr is added to the address every time the dmac transfers data of the data access size. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 327 of 1340 rej09b0499-0200 the address is calculated by the offset set in dofr and the contents of dsar and ddar. although the dmac calculates only addition, an of fset subtraction can be realized by setting the negative value in dofr. in this case, the negative value must be 2's complement. (1) basic transfer using offset figure 10.18 shows a basic operation of a transfer using the offset addition. data 1 offset address a1 transfer address a2 = address a1 + offset address b1 address b2 = address b1 + 4 address b3 = address b2 + 4 address b4 = address b3 + 4 address b5 = address b4 + 4 address a3 = address a2 + offset address a4 = address a3 + offset address a5 = address a4 + offset offset offset offset transfer source: offset addition transfer destination: increment by 4 (longword) data 1 data 2 data 3 data 4 data 5 : : : : data 2 data 3 data 4 data 5 figure 10.18 operation of offset addition in figure 10.18, the offset additi on is selected as the transfer source address update and increment or decrement by 1, 2, or 4 is selected as the tr ansfer destination address. the address update means that data at the address which is away from the previous transfer source address by the offset is read from. the data read from the address away from the previo us address is written to the consecutive area in the destination side. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 328 of 1340 rej09b0499-0200 (2) xy conversion using offset figure 10.19 shows the xy conversion using the offset addition in repeat transfer mode. data 1 data 2 data 3 data 4 data 5 data 11 data 12 data 16 data 16 data 15 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 5 data 9 data 13 data 2 data 11 data 15 data 12 data 8 data 4 data 7 data 3 data 14 data 10 data 6 1st transfer 1st transfer 2nd transfer 2nd transfer 3rd transfer 3rd transfer 4th transfer 1st transfer 2nd transfer 3rd transfer 4th transfer data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 5 data 9 data 13 data 12 data 2 data 11 data 15 data 16 data 8 data 4 data 7 data 3 data 14 data 10 data 6 transfer transfer interrupt request generated interrupt request generated address initialized interrupt request generated address initialized transfer source addresses changed by cpu transfer source addresses changed by cpu offset offset offset figure 10.19 xy conversion operation using offset addition in repeat transfer mode in figure 10.19, the source addres s side is specified to the rep eat area by dacr and the offset addition is selected. the offset value is set to 4 data access size (when the data access size is longword, h'00000010 is set in dofr, as an example). the repeat size is set to 4 data access size (when the data access size is long word, the repeat size is set to 4 4 = 16 bytes, as an example). the increment or decrement by 1, 2, or 4 is specified as the transfer de stination address. a repeat size end interrupt is requested when th e rptie bit in dacr is set to 1 and the repeat size of transfers is completed. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 329 of 1340 rej09b0499-0200 when a transfer starts, the transfer source address is added to the offset every time data is transferred. the transfer data is written to the de stination continuous addresses. when data 4 is transferred meaning that the rep eat size of transfers is complete d, the transfer source address returns to the transfer start addr ess (address of data 1 on the tran sfer source) and a repeat size end interrupt is requested. while this interrupt stops th e transfer temporarily, the contents of dsar are written to the address of data 5 by the cpu (whe n the data access size is longword, write the data 1 address + 4). when the dte bit in dmdr is set to 1, the transfer is resumed from the state when the transfer is stopped. accordin gly, operations are repeated an d the transfer source data is transposed to the destin ation area (xy conversion). figure 10.20 shows a flowchart of the xy conversion. : user operation : dmac operation start set address and transfer count set repeat transfer mode set dte bit to 1 receives transfer request transfers data decrements transfer count and repeat size enable repeat escape interrupt set transfer source address + 4 initializes transfer source address generates repeat size end interrupt request transfer count = 0? repeat size = 0? end no no ye s ye s (longword transfer) figure 10.20 xy conversion flowchart using offset addition in repeat transfer mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 330 of 1340 rej09b0499-0200 (3) offset subtraction when setting the negative value in dofr, the offset value must be 2's complement. the 2's complement is obtained by the following formula. 2's complement of offset = 1 + ~offset (~: bit inversion) example: 2's complement of h'0001ffff = h'fffe0000 + h'00000001 = h'fffe0001 the value of 2's complement can be obtained by the neg.l instruction. 10.5.7 register during dma transfer the dmac registers are updated by a dma transfer . the value to be updated differs according to the other settings and transfer state. the registers to be updated are dsar, ddar, dtcr, bits bkszh and bksz in dbsr, and the dte, act, errf, esif, and dtif bits in dmdr. (1) dma source address register when the transfer source address set in dsar is accessed, the contents of dsar are output and then are updated to the next address. the increment or decrement can be specified by bits sat1 and sat0 in dacr. when sat1 and sat0 = b'00, the address is fixed. when sat1 and sat0 = b'01, the address is added with the offset. when sat1 and sat0 = b'10, the address is incremented. when sat1 and sat0 = b'11, the address is decremented. the size of incremen t or decrement depends on the data access size. the data access size is specified by bits dtsz 1 and dtsz0 in dmdr. when dtsz1 and dtsz0 = b'00, the data access size is byte and the addres s is incremented or d ecremented by 1. when dtsz1 and dtsz0 = b'01, the data access size is word and the addre ss is incremented or decremented by 2. when dtsz1 and dtsz0 = b'10, the data access size is longword and the address is incremented or decremented by 4. even if the acce ss data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. while data of one word or one longword is being read, the size of increment or decrement is changi ng according to the actual data access size, for example, +1 or +2 for byte or word data. after one word or one longword of data is read, the address when the read cycle is started is incremented or decrem ented by the value according to bits sat1 and sat0. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 331 of 1340 rej09b0499-0200 in block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is spec ified to the source address side, the source address returns to the transfer start address and is not affected by the address update. when the extended repeat area is specified to the source address side, operation follows the setting. the upper address bits are fixed an d is not affected by the address update. while data is being transferred, dsar must be accessed in longwords. if the upper word and lower word are read separately, incorrect data may be read from since the contents of dsar during the transfer may be updated regardless of the access by the cpu. moreover, dsar for the channel being transferred must not be written to. (2) dma destination address register when the transfer destination ad dress set in ddar is accessed, the contents of ddar are output and then are updated to the next address. the increment or decrement can be specified by bits dat1 and dat0 in dacr. when dat1 and dat0 = b'00, the address is fixed. when da t1 and dat0 = b'01, the address is added with the offset. when dat1 and dat0 = b'10, the ad dress is incremented. when dat1 and dat0 = b'11, the address is decremente d. the incrementing or decrem enting size depends on the data access size. the data access size is specified by bits dtsz 1 and dtsz0 in dmdr. when dtsz1 and dtsz0 = b'00, the data access size is byte and the addres s is incremented or d ecremented by 1. when dtsz1 and dtsz0 = b'01, the data access size is word and the addre ss is incremented or decremented by 2. when dtsz1 and dtsz0 = b'10, the data access size is longword and the address is incremente d or decremented by 4. even if the ac cess data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. while one word or one longword of data is being written, the incremen ting or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. af ter the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value accordi ng to bits sat1 and sat0. in block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start ad dress and is not affected by the address update. when the extended repeat area is specified to th e destination address side, operation follows the setting. the upper address bits are fixed an d is not affected by the address update. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 332 of 1340 rej09b0499-0200 while data is being transferred, ddar must be accessed in longwords. if the upper word and lower word are read separately, incorrect data may be read from since the contents of ddar during the transfer may be updated regardless of the access by the cpu. moreover, ddar for the channel being transferred must not be written to. (3) dma transfer count register (dtcr) a dma transfer decrements the contents of dtcr by the transferred bytes. when byte data is transferred, dtcr is decremented by 1. when word data is tran sferred, dtcr is decremented by 2. when longword data is transferred, dtcr is decremented by 4. however, when dtcr = 0, the contents of dtcr are not changed since the number of transfers is not counted. while data is being transferred, all the bits of dtcr may be changed. dtcr must be accessed in longwords. if the upper word and lower word are read separately, incorrect data may be read from since the contents of dtcr duri ng the transfer may be update d regardless of the access by the cpu. moreover, dtcr for the channel being transferred must not be written to. when a conflict occurs between the address upda te by dma transfer and write access by the cpu, the cpu has priority. when a conflict occurs between change from 1, 2, or 4 to 0 in dtcr and write access by the cpu (other than 0), the cpu ha s priority in writing to dtcr. however, the transfer is stopped. (4) dma block size register (dbsr) dbsr is enabled in block or repeat transfer mode. bits 31 to 16 in dbsr function as bkszh and bits 15 to 0 in dbsr function as bksz. the bkszh bits (16 bits) store the block size and repeat size and its value is not changed. the bksz bits (16 bits) function as a counter for the block size and repeat size and its value is decremented ever y transfer by 1. when the bksz value is to change from 1 to 0 by a dma transfer, 0 is not stored but the bkszh value is loaded into the bksz bits. since the upper 16 bits of dbsr are no t updated, dbsr can be accessed in words. dbsr for the channel being transferred must not be written to. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 333 of 1340 rej09b0499-0200 (5) dte bit in dmdr although the dte bit in dmdr enab les or disables data transfer by the cpu write access, it is automatically cleared to 0 according to the dma transfer state by the dmac. the conditions for clearing the dte bit by the dmac are as follows: ? when the total size of transfers is completed ? when a transfer is completed by a transfer size error interrupt ? when a transfer is completed by a repeat size end interrupt ? when a transfer is completed by an extended repeat area overflow interrupt ? when a transfer is stopped by an nmi interrupt ? when a transfer is stopped by and address error ? reset state ? hardware standby mode ? when a transfer is stopped by writing 0 to the dte bit writing to the registers for the channels when the corresponding dte bit is set to 1 is prohibited (except for the dte bit). when changing the regi ster settings after writing 0 to the dte bit, confirm that the dte bit has been cleared to 0. figure 10.21 show the procedure for changing the register settings for the channel being transferred. read dte bit write 0 to dte bit change register settings dte = 0? [1] [2] [3] [4] no yes changing register settings of channel during operation end of changing register settings [1] write 0 to the dte bit in dmdr. [2] read the dte bit. [3] confirm that dte = 0. dte = 1 indicates that dma is transferring. [4] write the desired values to the registers. figure 10.21 procedure for changing register setting fo r channel being transferred section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 334 of 1340 rej09b0499-0200 (6) act bit in dmdr the act bit in dmdr indicates whether the dmac is in the idle or active state. when dte = 0 or dte = 1 and the dmac is waiting for a transfer request, the act bit is 0. otherwise (the dmac is in the active state), the act bit is 1. when individual transfers are stopped by writing 0 and the transfer is not comple ted, the act bit retains 1. in block transfer mode, even if individual transfers are stopped by writing 0 to the dte bit, the 1- block size of transfers is not stopped. the act bit retains 1 from writing 0 to the dte bit to completion of a 1-bl ock size transfer. in burst mode, up to three times of dma transf er are performed from the cycle in which the dte bit is written to 0. the act bit retains 1 from writing 0 to the dte bit to completion of dma transfer. (7) errf bit in dmdr when an address error or an nmi interrupt o ccur, the dmac clears th e dte bits for all the channels to stop a transfer. in addition, it sets the errf bit in dmdr_0 to 1 to indicate that an address error or an nmi interrupt has occurred regardless of whether or not the dmac is in operation. however, when the dmac is in the module stop state, the errf bit is not set to 1 for address errors or the nmi. (8) esif bit in dmdr when an interrupt by an transfer size error, a re peat size end, or an extended repeat area overflow is requested, the esif bit in dmdr is set to 1. when both the esif and esie bits are set to 1, a transfer escape interrupt is re quested to the cpu or dtc. the esif bit is set to 1 when the act bit in dmdr is cleared to 0 to stop a transfer af ter the bus cycle of the interrupt source is completed. the esif bit is automatically cleared to 0 and a transfer request is clear ed if the transfer is resumed by setting the dte bit to 1 during interrupt handling. for details on interrupts, see section 10.8, interrupt sources. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 335 of 1340 rej09b0499-0200 (9) dtif bit in dmdr the dtif bit in dmdr is set to 1 after the total tr ansfer size of transfers is completed. when both the dtif and dtie bits in dmdr are set to 1, a transfer end interrupt by the transfer counter is requested to the cpu or dtc. the dtif bit is set to 1 when the act bit in dmdr is cleared to 0 to stop a transfer after the bus cycle is completed. the dtif bit is automatically cleared to 0 and a transfer request is clear ed if the transfer is resumed by setting the dte bit to 1 during interrupt handling. for details on interrupts, see section 10.8, interrupt sources. 10.5.8 priority of channels the channels of the dmac are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. table 10.6 shows the priority levels among the dmac channels. table 10.6 priority among dmac channels channel priority channel 0 channel 1 channel 2 high channel 3 low the channel having highest priority other than the channel being transferred is selected when a transfer is requested from other ch annels. the selected channel starts the transfer after the channel being transferred releases the bus. at this time, when a bus master other than the dmac requests the bus, the cycle for the bus master is inserted. in a burst transfer or a block tr ansfer, channels are not switched. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 336 of 1340 rej09b0499-0200 figure 10.22 shows a transfer example when multip le transfer requests from channels 0 to 2. channel 0 channel 1 bus released bus released channel 2 channel 0 transfer channel 1 transfer channel 2 transfer channel 0 channel 1 channel 2 wait wait request cleared request cleared request cleared request retained request retained request retained selected selected not selected address bus channel 0 channel 1 channel 2 b dmac operation figure 10.22 example of timing for channel priority section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 337 of 1340 rej09b0499-0200 10.5.9 dma basic bus cycle figure 10.23 shows an example of signal timing of a basic bus cycle. in figure 10.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. when the bus mastership is passed from the dmac to the cpu, data is read from the source address and it is written to the destination address. the bus is not released between the read and write cycles by other bus requests. dmac bus cycles follows the bus controller settings. cpu cycle dmac cycle (one word transfer) cpu cycle address bus b t 1 t 2 t 1 t 2 t 3 t 1 t 2 t 3 source address destination address rd lhwr llwr high figure 10.23 example of bus timing of dma transfer section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 338 of 1340 rej09b0499-0200 10.5.10 bus cycles in dual address mode (1) normal transfer mode (cycle stealing mode) in cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. one bus cy cle or more by the cpu or dtc are executed in the bus released cycles. in figure 10.24, the tend signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access spa ce in normal transfer mode by cycle stealing. dma read cycle dma write cycle address bus dma read cycle dma write cycle dma read cycle dma write cycle b rd lhwr , llwr tend bus released bus released bus released bus released last transfer cycle figure 10.24 example of transfer in no rmal transfer mode by cycle stealing in figures 10.25 and 10.26, the tend signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the 16-bit 2-state access sp ace in normal transfer mode by cycle stealing. in figure 10.25, the transfer source (dsar) is not aligned with a longword boundary and the transfer destination (ddar) is aligned with a longword boundary. in figure 10.26, the transfer so urce (dsar) is aligned with a longword boundary and the transfer destination (ddar) is not aligned with a longword boundary. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 339 of 1340 rej09b0499-0200 address bus dma word write cycle dma byte read cycle dma byte read cycle dma word read cycle dma word write cycle dma word write cycle dma byte read cycle dma byte read cycle dma word read cycle dma word write cycle b rd llwr lhwr tend bus released bus released bus released last transfer cycle 4m + 1 4m + 2 4m + 4 4n + 4 4n + 6 4n 4n +2 4m + 5 4m + 6 4m + 8 m and n are integers. figure 10.25 example of transfer in no rmal transfer mode by cycle stealing (transfer source dsar = odd add ress and source address increment) dma word read cycle dma byte write cycle dma word read cycle address bus dma byte write cycle dma byte write cycle dma word write cycle dma word read cycle dma byte write cycle dma word read cycle dma word write cycle b rd llwr lhwr tend bus released bus released bus released last transfer cycle 4m 4m + 2 4n + 5 4n + 2 4n + 4 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 m and n are integers. figure 10.26 example of transfer in no rmal transfer mode by cycle stealing (transfer destination ddar = odd address and dest ination address decrement) section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 340 of 1340 rej09b0499-0200 (2) normal transfer mode (burst mode) in burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. when a burst transfer star ts, a transfer request from a channel having priority is suspended until the burst transfer is completed. in figure 10.27, the tend signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access spa ce in normal transfer mode by burst access. dma read cycle dma read cycle dma write cycle address bus dma write cycle dma read cycle dma write cycle b rd lhwr , llwr tend bus released bus released last transfer cycle burst transfer figure 10.27 example of transfer in normal transfer mode by burst access section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 341 of 1340 rej09b0499-0200 (3) block transfer mode in block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. in figure 10.28, the tend signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access sp ace in block transfer mode. dma read cycle dma read cycle dma write cycle address bus dma write cycle dma read cycle dma read cycle dma write cycle dma write cycle b rd lhwr , llwr tend bus released bus released bus released last block transfer cycle block transfer figure 10.28 example of transfer in block transfer mode section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 342 of 1340 rej09b0499-0200 (4) activation timing by dreq falling edge figure 10.29 shows an example of norm al transfer mode activated by the dreq signal falling edge. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared and starts detecting a high level of the dreq signal for falling edge detection. if a high level of the dreq signal has been detected until completion of the dma write cycle, receiving the next transfer request resumes and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. request wait wait wait request duration of transfer request disabled duration of transfer request disabled min. of 3 cycles min. of 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started and sampling the dreq signal at the rising edge of the b signal is started to detect a high level of the dreq signal. [4][7] when a high level of the dreq signal has been detected, transfer request enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) figure 10.29 example of transfer in normal transfer mode activated by dreq falling edge section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 343 of 1340 rej09b0499-0200 figure 10.30 shows an example of bl ock transfer mode activated by the dreq signal falling edge. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared and starts detecting a high level of the dreq signal for falling edge detection. if a high level of the dreq signal has been detected until co mpletion of the dma write cycle, receiving the next transfer request resumes and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. request request duration of transfer request disabled duration of transfer request disabled min. of 3 cycles min. of 3 cycles bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started and sampling the dreq signal at the rising edge of the b signal is started to detect a high level of the dreq signal. [4][7] when a high level of the dreq signal has been detected, transfer request enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) 1-block transfer 1-block transfer wait wait wait transfer source transfer destination transfer destination transfer source read write read write figure 10.30 example of transfer in block transfer mode activated by dreq falling edge section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 344 of 1340 rej09b0499-0200 (5) activation timing by dreq low level figure 10.31 shows an example of norm al transfer mode activated by the dreq signal low level. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer re quest resumes after completion of the write cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. wait wait wait min. of 3 cycles min. of 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) request request duration of transfer request disabled duration of transfer request disabled figure 10.31 example of transfer in normal transfer mode activated by dreq low level section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 345 of 1340 rej09b0499-0200 figure 10.32 shows an example of bl ock transfer mode activated by the dreq signal low level. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer re quest resumes after completion of the write cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. wait wait wait min. of 3 cycles min. of 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) 1-block transfer 1-block transfer request request duration of transfer request disabled duration of transfer request disabled figure 10.32 example of transfer in block transfer mode activated by dreq low level section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 346 of 1340 rej09b0499-0200 (6) activation timing by dreq low level with nrd = 1 when the nrd bit in dmdr is set to 1, the ti ming of receiving the next transfer request is delayed for one cycle. figure 10.33 shows an example of norm al transfer mode activated by the dreq signal low level with nrd = 1. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer re quest resumes after completion of the write cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. duration of transfer request disabled transfer source transfer destination transfer destination transfer source bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed one cycle after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) request request min. of 3 cycles min. of 3 cycles duration of transfer request disabled which is extended by nrd duration of transfer request disabled which is extended by nrd duration of transfer request disabled figure 10.33 example of transfer in normal transfer mode activated by dreq low level with nrd = 1 section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 347 of 1340 rej09b0499-0200 10.5.11 bus cycles in single address mode (1) single address mode (read and cycle stealing) in single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is re leased temporarily. one bu s cycle or more by the cpu or dtc are executed in the bus released cycles. in figure 10.34, the tend signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access sp ace to the external device in single address mode (read). bus released bus released bus released dma read cycle dma read cycle dma read cycle dma read cycle b address bus bus released bus released last transfer cycle rd tend dack figure 10.34 example of transfer in single address mode (byte read) section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 348 of 1340 rej09b0499-0200 (2) single address mode (write and cycle stealing) in single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is re leased temporarily. one bu s cycle or more by the cpu or dtc are executed in the bus released cycles. in figure 10.35, the tend signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access sp ace to the external device in single address mode (write). bus released bus released dma write cycle b address bus bus released bus released last transfer cycle tend dack dma write cycle dma write cycle dma write cycle llwr bus released figure 10.35 example of transfer in single address mode (byte write) section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 349 of 1340 rej09b0499-0200 (3) activation timing by dreq falling edge figure 10.36 shows an example of si ngle address mode activated by the dreq signal falling edge. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared and starts detecting a high level of the dreq signal for falling edge detection. if a high level of the dreq signal has been detected until comple tion of the single cycle, receiving the next transfer request resumes and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. request wait wait wait request min. of 3 cycles min. of 3 cycles transfer source/ transfer destination single bus released bus released bus released dma single cycle dma single cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started and sampling the dreq signal at the rising edge of the b signal is started to detect a high level of the dreq signal. [4][7] when a high level of the dreq signal has been detected, transfer enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) transfer source/ transfer destination single dack duration of transfer request disabled duration of transfer request disabled figure 10.36 example of transfer in single address mode activated by dreq falling edge section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 350 of 1340 rej09b0499-0200 (4) activation timing by dreq low level figure 10.37 shows an example of norm al transfer mode activated by the dreq signal low level. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer re quest resumes after completion of the single cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. request wait wait wait request min. of 3 cycles min. of 3 cycles transfer source/ transfer destination single bus released bus released bus released dma single cycle dma single cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed after completion of the single cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) transfer source/ transfer destination single dack duration of transfer request disabled duration of transfer request disabled figure 10.37 example of transfer in single address mode activated by dreq low level section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 351 of 1340 rej09b0499-0200 (5) activation timing by dreq low level with nrd = 1 when the nrd bit in dmdr is set to 1, the tim ing of receiving the next transfer request is delayed for one cycle. figure 10.38 shows an example of si ngle address mode activated by the dreq signal low level with nrd = 1. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer request resumes after one cycle of the transfer request duration inserted by nrd = 1 on completion of the single cycle and then a low level of the dreq signal is detected. this operation is re peated until the tran sfer is completed. min. of 3 cycles min. of 3 cycles dma single cycle dma single cycle b dreq address bus channel [1] [2] [3] [4] [5] [6] [7] [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed one cycle after completion of the single cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) transfer source/ transfer destination bus released bus released transfer request enable resumed transfer request enable resumed transfer source/ transfer destination request request duration of transfer request disabled duration of transfer request disabled duration of transfer request disabled which is extended by nrd duration of transfer request disabled which is extended by nrd bus released figure 10.38 example of transfer in single address mode activated by dreq low level with nrd = 1 section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 352 of 1340 rej09b0499-0200 10.6 dma transfer end operations on completion of a transfer differ according to the transfer end condition. dma transfer completion is indicated that the dte an d act bits in dmdr are changed from 1 to 0. (1) transfer end by dtcr change from 1, 2, or 4, to 0 when dtcr is changed from 1, 2, or 4 to 0, a dma transfer for the channel is completed. the dte bit in dmdr is cleared to 0 and the dtif bit in dmdr is set to 1. at this time, when the dtie bit in dmdr is set to 1, a transfer end in terrupt by the transfer counter is requested. when the dtcr value is 0 before the transf er, the transfer is not stopped. (2) transfer end by transf er size error interrupt when the following conditions are satisfied while th e tseie bit in dmdr is set to 1, a transfer size error occurs and a dma transfer is terminated. at this time, the dte bit in dmdr is cleared to 0 and the esif bit in dmdr is set to 1. ? in normal transfer mode and repeat transfer mo de, when the next transfer is requested while a transfer is disabled du e to the dtcr value less than the data access size ? in block transfer mode, when the next transfer is requested while a transfer is disabled due to the dtcr value less than the block size when the tseie bit in dmdr is cleared to 0, da ta is transferred until the dtcr value reaches 0. a transfer size error is not ge nerated. operation in each transfer mode is shown below. ? in normal transfer mode and repeat transfer mode, when the dtcr value is less than the data access size, data is transferred in bytes ? in block transfer mode, when the dtcr value is less than the block size, the specified size of data in dtcr is transferred instead of transferring the block size of data. the transfer is performed in bytes. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 353 of 1340 rej09b0499-0200 (3) transfer end by repeat size end interrupt in repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the rptie bit in da cr is set to 1, a repeat size en d interrupt is requested. when the interrupt is requested to complete dma transf er, the dte bit in dmdr is cleared to 0 and the esif bit in dmdr is set to 1. under this condition, setting the dte bit to 1 resumes the transfer. in block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested. (4) transfer end by interrupt on extended repeat area overflow when an overflow on the extended repeat area oc curs while the extended repeat area is specified and the sarie or darie bit in dacr is set to 1, an interrupt by an extended repeat area overflow is requested. when the interrupt is re quested, the dma transfer is terminated, the dte bit in dmdr is cleared to 0, and the esif bit in dmdr is set to 1. in dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. in block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1- block transfer, the remaining data is transferred. the tr ansfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) transfer end by clearing dte bit in dmdr when the dte bit in dmdr is cleared to 0 by th e cpu, a transfer is completed after the current dma cycle and a dma cycle in which the tr ansfer request is accep ted are completed. in block transfer mode, a dma transfer is co mpleted after 1-block data is transferred. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 354 of 1340 rej09b0499-0200 (6) transfer end by nmi interrupt when an nmi interrupt is requested, the dte bits for all the channels are cleared to 0 and the errf bit in dmdr_0 is set to 1. when an nmi interrupt is requested during a dma transfer, the transfer is forced to st op. to perform dma transfer after an nmi interrupt is requested, clear the errf bit to 0 and then set the dte bits for the channels to 1. the transfer end timings after an nmi in terrupt is requested are shown below. (a) normal transfer mode and repeat transfer mode in dual address mode, a dma tran sfer is completed after completion of the write cycle for one transfer unit. in single address mode, a dma tr ansfer is completed after comp letion of the bus cycle for one transfer unit. (b) block transfer mode a dma transfer is forced to stop. since a 1-block size of transfers is not completed, operation is not guaranteed. in dual address mode, the write cy cle corresponding to the read cycl e is performed. this is similar in normal transfer mode. (7) transfer end by address error when an address error occurs, the dte bits for a ll the channels are cleared to 0 and the errf bit in dmdr_0 is set to 1. when an address error occurs during a dma tran sfer, the transfer is forced to stop. to perform a dma transfer after an address error occurs, clear the errf bit to 0 and then set the dte bits for the channels. the transfer end timing after an address error is the same as that after an nmi interrupt. (8) transfer end by hardware standby mode or reset the dmac is initialized by a reset and a transition to the hardware standby mode. a dma transfer is not guaranteed. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 355 of 1340 rej09b0499-0200 10.7 relationship among dmac and other bus masters 10.7.1 cpu priority control function over dmac the cpu priority control function over dmac can be used according to the cpu priority control register (cpupcr) setting. for details, see section 7.7, cpu priority control function over dtc, dmac, and exdmac. the priority level of the dmac is specified by bits dmap2 to dmap0 and can be specified for each channel. the priority level of the cpu is specified by bits cpup2 to cpup0. the value of bits cpup2 to cpup0 is updated according to th e exception handling priority. if the cpu priority control is enabled by the cp upce bit in cpupcr, when the cpu has priority over the dmac, a transfer request for the correspond ing channel is masked and the transfer is not activated. when another channel has priority over or the same as the cpu, a transfer request is received regardless of the priority between ch annels and the transfer is activated. the transfer request masked by the cpu priority control function is suspended. when the transfer channel is given priority over the cpu by changing priority levels of the cpu or channel, the transfer request is received and the transfer is resumed. writing 0 to the dte bit clears the suspended transfer request. when the cpupce bit is cleared to 0, it is regarded as the lowest priority. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 356 of 1340 rej09b0499-0200 10.7.2 bus arbitration among dmac and other bus masters when dma transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. the dmac can release the bus temporarily to pass the bus to other bus masters. the consecutive dma transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. the read and write cycles of a dma transfer are not separated. external bus release and on-chip bus master (cpu, dtc, or exdmac) cycles are no t inserted between the read and write cycles of a dma transfer. in block transfer mode and an auto request tr ansfer by burst access, bus cycles of the dma transfer are consecutively performed. for this duration, since the dmac has priority over the cpu and dtc, accesses to the external space is suspended (the ibccs b it in the bus control register 2 (bcr2) is cleared to 0). when the bus is passed to another channel or an au to request transfer by cy cle stealing, bus cycles of the dmac and on-chip bus mast er are performed alternatively. when the arbitration function among the dmac and on-chip bus masters is enabled by setting the ibccs bit in bcr2, the bus is used alternatively except the bus cycles which are not separated. for details, see section 9, bus controller (bsc). a conflict may occur between external space access of the dmac, and the exdmac cycle or external bus release cycle. even if a burst or block transfer is performed by the dmac, the transfer is stopped tempor arily and the exdmac cycl e or external bus release cycle is inserted by the bsc according to the external bus priori ty (when the cpu external access and the dtc external access do not have priority over a dmac transfer, the tran sfers are not operated until the dmac releases the bus). in dual address mode, the dmac releases the ex ternal bus after the exte rnal space write cycle. since the read and write cy cles are not separated, the bus is not released. an internal space (on-chip me mory and internal i/o register s) access of the dmac, and the exdmac cycle or external bus release cy cle may be performed at the same time. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 357 of 1340 rej09b0499-0200 10.8 interrupt sources the dmac interrupt sources are a transfer end in terrupt by the transfer counter and a transfer escape end interrupt which is generated when a tran sfer is terminated befo re the transfer counter reaches 0. table 10.7 shows in terrupt sources and priority. table 10.7 interrupt sources and priority abbr. interrupt sources priority dmtend0 transfer end interrupt by channel 0 transfer counter high dmtend1 transfer end interrupt by channel 1 transfer counter dmtend2 transfer end interrupt by channel 2 transfer counter dmtend3 transfer end interrupt by channel 3 transfer counter dmeend0 interrupt by channel 0 transfer size error interrupt by channel 0 repeat size end interrupt by channel 0 extended repeat area overflow on source address interrupt by channel 0 extended repeat area overflow on destination address dmeend1 interrupt by channel 1 transfer size error interrupt by channel 1 repeat size end interrupt by channel 1 extended repeat area overflow on source address interrupt by channel 1 extended repeat area overflow on destination address dmeend2 interrupt by channel 2 transfer size error interrupt by channel 2 repeat size end interrupt by channel 2 extended repeat area overflow on source address interrupt by channel 2 extended repeat area overflow on destination address dmeend3 interrupt by channel 3 transfer size error interrupt by channel 3 repeat size end interrupt by channel 3 extended repeat area overflow on source address interrupt by channel 3 extended repeat area overflow on destination address low each interrupt is enabled or disabled by the dtie and esie bits in dmdr for the corresponding channel. a dmtend interrupt is generated by the combination of the dtif and dtie bits in dmdr. a dmeend interrupt is generated by the combination of the esif and esie bits in dmdr. the dmeend interrupt sources are not distinguished. the priority among channels is decided by the interrupt controller and it is shown in table 10.7. for details, see section 7, interrupt controller. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 358 of 1340 rej09b0499-0200 each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. a transfer end interrupt by the transfer counter, a transf er size error interrupt, a repeat size end interrupt, an interrupt by an extended rep eat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the dtie bit in dmdr, the tseie bit in dmdr , the rptie bit in dacr, sarie bit in dacr, and the darie bit in dacr, respectively. a transfer end interrupt by the transfer counter is generated when the dtif bit in dmdr is set to 1. the dtif bit is set to 1 when dtcr becomes 0 by a transfer while the dtie bit in dmdr is set to 1. an interrupt other than the transf er end interrupt by the transfer counter is generated when the esif bit in dmdr is set to 1. the esif bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. a transfer size error interrupt is generated when the next transfer cannot be performed because the dtcr value is less than the data access size, mean ing that the data access size of transfers cannot be performed. in block transfer mode, the block size is compared with the dtcr value for transfer error decision. a repeat size end interrupt is generated when the ne xt transfer is requested after completion of the repeat size of transfers in repeat transfer mode. even when the rep eat area is not specified in the address register, the transfer can be stopped periodi cally according to the repeat size. at this time, when a transfer end interrupt by the transfer co unter is generated, the esif bit is set to 1. an interrupt by an extended re peat area overflow on the sour ce and destination addresses is generated when the address exceeds the extended re peat area (overflow). at this time, when a transfer end interrupt by the transfer counter, the esif bit is set to 1. figure 10.39 is a block diagram of interrupts and interrupt flags. to clear an interrupt, clear the dtif or esif bit in dmdr to 0 in the interrup t handling routine or continue the transfer by setting the dte bit in dmdr after setting the register. figure 10.40 shows procedure to resume the transfer by clearing an interrupt. section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 359 of 1340 rej09b0499-0200 tsie bit dmac is activated in transfer size error state rptie bit dmac is activated after bksz bits are changed from 1 to 0 sarie bit extended repeat area overflow occurs in source address darie bit extended repeat area overflow occurs in destination address dtie bit dtif bit transfer end interrupt [setting condition] when dtcr becomes 0 and transfer ends setting condition is satisfied esie bit esif bit transfer escape end interrupt figure 10.39 interrupt and interrupt sources transfer end interrupt handling routine consecutive transfer processing registers are specified dte bit is set to 1 interrupt handling routine ends (rte instruction executed) transfer resume processing end transfer resumed after interrupt handling routine dtif and esif bits are cleared to 0 interrupt handling routine ends dte bit is set to 1 registers are specified transfer resume processing end [1] [2] [3] [4] [5] [6] [7] [1] specify the values in the registers such as transfer counter and address register. [2] set the dte bit in dmdr to 1 to resume dma operation. setting the dte bit to 1 automatically clears the dtif or esif bit in dmdr to 0 and an interrupt source is cleared. [3] end the interrupt handling routine by the rte instruction. [4] read that the dtif or the esif bit in dmdr = 1 and then write 0 to the bit. [5] complete the interrupt handling routine and clear the interrupt mask. [6] specify the values in the registers such as transfer counter and address register. [7] set the dte bit to 1 to resume dma operation. figure 10.40 procedure example of resumi ng transfer by clea ring interrupt source section 10 dma controller (dmac) rev. 2.00 oct. 20, 2009 page 360 of 1340 rej09b0499-0200 10.9 usage notes 1. dmac register access during operation except for clearing the dte bit in dmdr, the settings for channels being transferred (including waiting state) must not be changed. the register settings must be changed during the transfer proh ibited state. 2. settings of module stop function the dmac operation can be enabled or disabled by the module stop control register. the dmac is enabled by the initial value. setting bit mstpa13 in mstpcra stops the clock supplied to the dmac and the dmac enters the module stop state. however, when a transfer for a channel is enabled or when an interrupt is being requested, bit mstpa13 cannot be set to 1. clear the dte bit to 0, clear the dtif or dtie bit in dmdr to 0, and then set bit mstpa13. when the clock is stopped, the dmac regist ers cannot be accessed. however, the following register settings are valid in the module stop stat e. disable them before entering the module stop state, if necessary. ? tende bit in dmdr is 1 (the tend signal output enabled) ? dacke bit in dmdr is 1 (the dack signal output enabled) 3. activation by dreq falling edge the dreq falling edge detection is synchronized with the dmac internal operation. a. activation request waiting state: waiting for detecting the dreq low level. a transition to 2. is made. b. transfer waiting state: waiting for a dmac transfer. a transiti on to 3. is made. c. transfer prohibited state: waiting for detecting the dreq high level. a transition to 1. is made. after a dmac transfer enabled, a transition to 1. is made. therefore, the dreq signal is sampled by low level detection at the first activation after a dmac transfer enabled. 4. acceptation of activation source at the beginning of an activation source reception, a low level is detected regardless of the setting of dreq falling edge or low level detection. therefore, if the dreq signal is driven low before setting dmdr, the low level is received as a transfer request. when the dmac is activated, clear the dreq signal of the previous transfer. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 361 of 1340 rej09b0499-0200 section 11 exdma controller (exdmac) this lsi has an on-chip four-channel external bus transfer dma controller (exdmac). the exdmac can carry out high-speed data transfer , in place of the cpu, to and from external devices and external memory. also , the exdmac allows external bu s transfer in parallel with the internal cpu operation when there is no external bus request from a controller other than the exdmac. 11.1 features ? up to 4-gbyte address space accessible ? selection of byte, word, or l ongword transfer data length ? total transfer size of up to 4 gbytes (4,294,967,295 bytes) selection of free-running mode (wit h no total transf er size specified) ? selection of auto-requests or extern al requests for activating the exdmac auto-request: activation from the cpu (cycle st eal mode or burst mode can be selected.) external request: low level sensing or falling edge sensing for the edreq signal can be selected. only channel 0 or 1 can accept external requests. ? selection of dual address mode or single address mode dual address mode: both the tran sfer source and destination addres ses are specified to transfer data. single address mode: the edack signal is used to access the tr ansfer source or destination peripheral device and the address of the other device is specified to transfer data. only channel 0 or 1 can be sel ected for single address mode. ? normal, repeat, block, or cluster transfer (onl y for the exdmac) can be selected as transfer mode normal transfer mode: one byte, one word, or on e longword data is tr ansferred at a single transfer request repeat transfer mode: one byte, one word, or one longword data is transferred at a single transfer request repeat size of data is transferred an d then a transfer address returns to the transfer start address up to 64-kbyte transfers can be set as repeat size (65,536 bytes/words/longwords) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 362 of 1340 rej09b0499-0200 block transfer mode: one block data is transferred at a single transfer request up to 64-kbyte data can be set as block size (65,536 bytes/words/longwords) cluster transfer mode: one cluster data is transferred at a single transfer request up to 32-byte data can be set as cluster size ? selection of extended repeat area function (to transfer data such as ring buffer data by fixing the upper bit value in the tran sfer address register and repe ating the address values in a specified range) for the extended repeat area, 1 bit (2 bytes) to 27 bits (128 mbytes) can be set independently for the transfer source or destination. ? selection of address update methods: increment/decrement by 1, 2 or 4, fixed, or offset addition when offset addition is used to update addresses, the mid-addresses can be skipped during data transfer. ? transfer of word or longword data to addresses beyond each data boundary data can be divided into an optimal data size (byte or word) according to addresses when transferring data. ? two kinds of interrupts requested to the cpu transfer end interrupt: requested after the number of data set by the transfer counter has been completely transferred transfer escape end interrupt: requested when th e remaining transfer size is smaller than the size set for a single transfer request, after a rep eat-size transfer is completed, or when an extended repeat area overflow occurs. ? acceptance of a transfer re quest can be reported to an external device via the edrak pin (only for the exdmac). ? operation of exdmac, connected to a dedicated bus, in parallel with a bu s master such as the cpu, dtc, or dmac (only for the exdmac). ? module stop state can be set. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 363 of 1340 rej09b0499-0200 figure 11.1 shows a block diagram of the exdmac. edreqm edackm etendm edrakm edmdr_n edacr_n edofr_n edsar_n eddar_n edtcr_n edbsr_n clsbr1 clsbr2 clsbr0 clsbr7 . . . external pins control unit interrupt request signals to cpu for individual channels internal address bus internal data bus data buffer address buffer processor processor module data bus edsar_n: eddar_n: edofr_n: edtcr_n: edbsr_n: edmdr_n: edacr_n: clsbr0 to clsbr7: exdma source address register exdma destination address register exdma offset register exdma transfer count register exdma block size register exdma mode control register exdma address control register cluster buffer registers 0 to 7 edreqm : edackm : etendm : edrakm : (n: 0 to 3) (m:0 or 1) exdma transfer request exdma transfer acknowledge exdma transfer end edreq acceptance acknowledge [legend] figure 11.1 block diagram of exdmac section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 364 of 1340 rej09b0499-0200 11.2 input/output pins table 11.1 shows the exdmac pin configuration. table 11.1 pin configuration channel name a bbr. i/o function exdma transfer request 0 edreq0 input channel 0 external request exdma transfer acknowledge 0 edack0 output channel 0 single address transfer acknowledge exdma transfer end 0 etend0 output channel 0 transfer end 0 edreq0 acceptance acknowledge edrak0 output notification to external device of channel 0 external request acceptance and start of execution exdma transfer request 1 edreq1 input channel 1 external request exdma transfer acknowledge 1 edack1 output channel 1 single address transfer acknowledge exdma transfer end 1 etend1 output channel 1 transfer end 1 edreq1 acceptance acknowledge edrak1 output notification to external device of channel 1 external request acceptance and start of execution section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 365 of 1340 rej09b0499-0200 11.3 registers descriptions the exdmac has the following registers. channel 0 ? exdma source address register_0 (edsar_0) ? exdma destination address register_0 (eddar_0) ? exdma offset register_0 (edofr_0) ? exdma transfer count register_0 (edtcr_0) ? exdma block size register_0 (edbsr_0) ? exdma mode control register_0 (edmdr_0) ? exdma address control register_0 (edacr_0) channel 1 ? exdma source address register_1 (edsar_1) ? exdma destination address register_1 (eddar_1) ? exdma offset register_1 (edofr_1) ? exdma transfer count register_1 (edtcr_1) ? exdma block size register_1 (edbsr_1) ? exdma mode control register_1 (edmdr_1) ? exdma address control register_1 (edacr_1) channel 2 ? exdma source address register_2 (edsar_2) ? exdma destination address register_2 (eddar_2) ? exdma offset register_2 (edofr_2) ? exdma transfer count register_2 (edtcr_2) ? exdma block size register_2 (edbsr_2) ? exdma mode control register_2 (edmdr_2) ? exdma address control register_2 (edacr_2) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 366 of 1340 rej09b0499-0200 channel 3 ? exdma source address register_3 (edsar_3) ? exdma destination address register_3 (eddar_3) ? exdma offset register_3 (edofr_3) ? exdma transfer count register_3 (edtcr_3) ? exdma block size register_3 (edbsr_3) ? exdma mode control register_3 (edmdr_3) ? exdma address control register_3 (edacr_3) common register ? cluster buffer registers 0 to 7 (clsbr0 to clsbr7) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 367 of 1340 rej09b0499-0200 11.3.1 exdma source address register (edsar) edsar is a 32-bit readable/writable register that specifies the transfer s ource address. an address update function is provided that updates the register contents to the next transfer source address each time transfer proces sing is performed. in single addres s mode, the edsar value is ignored when the address specified by eddar is transferred as a destination address (dirs = 1 in edacr). edsar can be read at all times by the cpu. when reading edsar for a channel on which exdma transfer processing is in progress, a longword-size read must be executed. do not write to edsar for a channel on which exdma transfer is in progress. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 368 of 1340 rej09b0499-0200 11.3.2 exdma destination address register (eddar) eddar is a 32-bit readable/writable register that specifies the transfer de stination address. an address update function is provided that updates the register contents to the next transfer destination address each time tran sfer processing is performed. in single address mode, the eddar value is ignored when the address specified by edsar is transferred as a source address (dirs = 0 in edacr). eddar can be read at all times by the cpu. when reading eddar for a channel on which exdma transfer processing is in progress, a longword-size read must be executed. do not write to eddar for a channel on which exdma transfer is in progress. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 369 of 1340 rej09b0499-0200 11.3.3 exdma offset register (edofr) edofr is a 32-bit readable/writable register that sets the offset value when offset addition is selected for updating source or destination addresse s. this register can be set independently for each channel, but the same offset value must be used for the source and destination addresses on the same channel. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 370 of 1340 rej09b0499-0200 11.3.4 exdma transfer count register (edtcr) edtcr is a 32-bit readable/writable register that sp ecifies the size of data to be transferred (total transfer size). when edtcr is set to h'00000001, the total tr ansfer size is 1 byte. when edtcr is set to h'00000000, the total transfer size is not specified and the transfer counter is halted (free-running mode). in this case, no transfer end interrupt by the transfer coun ter is generated. when edtcr is set to h'ffffffff, up to 4 gbytes (4,294,967,295 byt es) of the total transfer size is set. when the exdma is active, edtcr indicates the remaining transfer size. the value according to the data access size (byte: ? 1, word: ? 2, longword: ? 4) is decremented each time of a data transfer. edtcr can be read at all times by the cpu. when reading edtcr for a channel on which exdma transfer processing is in progress, a longword-size read must be executed. do not write to edtcr for a channel on which exdma transfer is in progress. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 371 of 1340 rej09b0499-0200 11.3.5 exdma block size register (edbsr) edbsr sets the repeat size, block size, or cluster size. edbsr is enabled in repeat transfer, block transfer, and cluster transfer modes. edbsr is disabled in normal transfer mode. when bkszh and bksz are set to h'0001 in cl uster transfer mode (dual address mode), the exdmac operates in block transfer mode (dual address mode). 31 bkszh31 0 r/w 30 bkszh30 0 r/w 29 bkszh29 0 r/w 28 bkszh28 0 r/w 27 bkszh27 0 r/w 24 bkszh24 0 r/w 26 bkszh26 0 r/w 25 bkszh25 0 r/w bit bit name initial value r/w 23 bkszh23 0 r/w 22 bkszh22 0 r/w 21 bkszh21 0 r/w 20 bkszh20 0 r/w 19 bkszh19 0 r/w 16 bkszh16 0 r/w 18 bkszh18 0 r/w 17 bkszh17 0 r/w bit bit name initial value r/w 15 bksz15 0 r/w 14 bksz14 0 r/w 13 bksz13 0 r/w 12 bksz12 0 r/w 11 bksz11 0 r/w 8 bksz8 0 r/w 10 bksz10 0 r/w 9 bksz9 0 r/w bit bit name initial value r/w 7 bksz7 0 r/w 6 bksz6 0 r/w 5 bksz5 0 r/w 4 bksz4 0 r/w 3 bksz3 0 r/w 0 bksz0 0 r/w 2 bksz2 0 r/w 1 bksz1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 31 to 16 bkszh31 to bkszh16 all 0 r/w sets the repeat size, block size, or cluster size. when these bits are set to h'0001, one byte-, one word-, or one longword-size is set. when these bits are set to h'0000, the maximum values are set (see table 11.2). these bits are always fixed during an exdma operation. 15 to 0 bksz15 to bksz0 all 0 r/w in an exdma operation, the remaining repeat size, block size, or cluster size is indicated. the value is decremented by one each time of a data transfer. when the remaining size becomes zero, the bkszh value is loaded. set the same initial value as for the bkszh bit when writing. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 372 of 1340 rej09b0499-0200 table 11.2 data access size, en able bit, and allowable size mode data access size bkszh enable bit bksz enable bit allowable size (in bytes) byte 1 to 65,536 word 2 to 131,072 repeat transfer mode block transfer mode longword 31 to 16 15 to 0 4 to 262,144 byte 20 to 16 4 to 0 1 to 32 word 19 to 16 3 to 0 2 to 32 cluster transfer mode longword 18 to 16 2 to 0 4 to 32 11.3.6 exdma mode control register (edmdr) edmdr controls exdmac operations. ? edmdr_0 31 dte 0 r/w 30 edacke 0 r/w 29 etende 0 r/w 28 edrake 0 r/w 27 edreqs 0 r/w 24 ? 0 r 26 nrd 0 r/w 25 ? 0 r bit bit name initial value r/w 23 act 0 r 22 ? 0 r 21 ? 0 r 20 ? 0 r 19 errf 0 r/(w) * 16 dtif 0 r/(w) * 18 ? 0 r 17 esif 0 r/(w) * bit bit name initial value r/w 15 dtsz1 0 r/w 14 dtsz0 0 r/w 13 mds1 0 r/w 12 mds0 0 r/w 11 tseie 0 r/w 8 dtie 0 r/w 10 ? 0 r 9 esie 0 r/w bit bit name initial value r/w 7 dtf1 0 r/w 6 dtf0 0 r/w 5 ? 0 r/w 4 ? 0 r 3 ? 0 r 0 edmap0 0 r/w 2 edmap2 0 r/w 1 edmap1 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit after having been read as 1, to clear the flag. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 373 of 1340 rej09b0499-0200 ? edmdr_1 to edmdr_3 31 dte 0 r/w 30 edacke 0 r/w 29 etende 0 r/w 28 edrake 0 r/w 27 dreqs 0 r/w 24 ? 0 r 26 nrd 0 r/w 25 ? 0 r bit bit name initial value r/w 23 act 0 r 22 ? 0 r 21 ? 0 r 20 ? 0 r 19 ? 0 r 16 dtif 0 r/(w) * 18 ? 0 r 17 esif 0 r/(w) * bit bit name initial value r/w 15 dtsz1 0 r/w 14 dtsz0 0 r/w 13 mds1 0 r/w 12 mds0 0 r/w 11 tseie 0 r/w 8 dtie 0 r/w 10 ? 0 r 9 esie 0 r/w bit bit name initial value r/w 7 dtf1 0 r/w 6 dtf0 0 r/w 5 ? 0 r/w 4 ? 0 r 3 ? 0 r 0 edmap0 0 r/w 2 edmap2 0 r/w 1 edmap1 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit after having been read as 1, to clear the flag. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 374 of 1340 rej09b0499-0200 bit bit name initial value r/w description 31 dte 0 r/w data transfer enable enables or disables data tr ansfer on the corresponding channel. when this bit is set to 1, this indicates that an exdma operation is in progress. when auto-request mode is specified, transfer processing begins when this bit is set to 1. with external requests, transfer processing begins when a transfer request is issued after this bit has been set to 1. when this bit is cleared to 0 during an exdma operation, transfer is halted. if this bit is cleared to 0 during an exdma operation in block transfer mode, this bit is cleared to 0 on completion of the currently executing one-block transfer. when this bit is cleared to 0 during an exdma operation in cluster transfer mode, this bit is cleared to 0 on completion of the currently executing one-cluster transfer. if an external source that ends (aborts) transfer occurs, this bit is automatically cleared to 0 and transfer is terminated. do not change the operating mode, transfer method, or other parameters while this bit is set to 1. 0: data transfer disabled 1: data transfer enabled (during an exdma operation) [clearing conditions] ? when transfer of the total transfer size specified ends ? when operation is halted by a repeat size end interrupt ? when operation is halted by an extended repeat area overflow interrupt ? when operation is halted by a transfer size error interrupt ? when 0 is written to terminate transfer in block transfer mode, the value written is effective after one-block transfer ends. in cluster transfer mode, the value written is effective after one-cluster transfer ends. ? when an address error or nmi interrupt occurs ? reset, hardware standby mode section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 375 of 1340 rej09b0499-0200 bit bit name initial value r/w description 30 edacke 0 r/w edack pin output enable in single address mode, enables or disables output from the edack pin. in dual address mode, the specification by this bit is ignored. this bit should be set to 0 for edmdr_2 or edmdr_3. 0: edack pin output disabled 1: edack pin output enabled 29 etende 0 r/w etend pin output enable enables or disables output from the etend pin. this bit should be set to 0 for edmdr_2 or edmdr_3. 0: etend pin output disabled 1: etend pin output enabled 28 edrake 0 r/w edrak pin output enable enables or disables output from the edrak pin. this bit should be set to 0 for edmdr_2 or edmdr_3. 0: edrak pin output disabled 1: edrak pin output enabled 27 edreqs 0 r/w edreq select selects whether a low level or the falling edge of the edreq signal used in external request mode is detected. this bit should be set to 0 for edmdr_2 or edmdr_3. 0: low-level detection 1: falling edge detection (the first transfer is detected on a low level after a transfer is enabled.) 26 nrd 0 r/w next request delay selects the timing of the next transfer request to be accepted. 0: next transfer request starts to be accepted after transfer of the bus cycle in progress ends. 1: next transfer request starts to be accepted after one cycle of b from the completion of the bus cycle in progress. 25, 24 ? all 0 r reserved they are always read as 0 and cannot be modified. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 376 of 1340 rej09b0499-0200 bit bit name initial value r/w description 23 act 0 r active state indicates the operation st ate of the corresponding channel. 0: transfer request wait stat e or transfer disabled state (dte = 0) 1: active state 22 to 20 ? all 0 r reserved they are always read as 0 and cannot be modified. 19 errf 0 r/(w) * system error flag flag that indicates the occurrence of an address error or nmi interrupt. this bit is only enabled in edmdr_0. when this bit is set to 1, write to the dte bit for all channels is disabled. this bit is reserved in edmdr_1 to edmdr_3. they are always read as 0 and cannot be modified. 0: address error or nmi interrupt is not generated 1: address error or nmi interrupt is generated [clearing condition] ? writing 0 to errf after reading errf = 1 [setting condition] ? when an address error or nmi interrupt occurred however, when an address error or an nmi interrupt has been generated in exdmac module stop mode, this bit is not set to 1. 18 ? 0 r reserved they are always read as 0 and cannot be modified. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 377 of 1340 rej09b0499-0200 bit bit name initial value r/w description 17 esif 0 r/(w) * transfer escape interrupt flag flag indicating that a transfer escape end interrupt request has occurred before the transfer counter becomes 0 and transfer escape has ended. 0: transfer escape end interrupt request is not generated 1: transfer escape end interrupt request is generated [clearing conditions] ? writing 1 to the dte bit ? writing 0 to esif while reading esif = 1 [setting conditions] ? transfer size error interrupt request is generated ? repeat size end interrupt request is generated ? extended repeat area overflow end interrupt request is generated 16 dtif 0 r/(w) * data transfer interrupt flag flag indicating that a transfer end interrupt request has occurred by the transfer counter. 0: transfer end interrupt request is not generated by the transfer counter 1: transfer end interrupt request is generated by the transfer counter [clearing conditions] ? writing 1 to the dte bit ? writing 0 to dtif while reading dtif = 1 [setting condition] ? when edtcr becomes 0 and transfer has ended 15 14 dtsz1 dtsz0 0 0 r/w r/w data access size 1 and 0 selects the data access size. 00: byte-size (8 bits) 01: word-size (16 bits) 10: longword-size (32 bits) 11: setting prohibited section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 378 of 1340 rej09b0499-0200 bit bit name initial value r/w description 13 12 mds1 mds0 0 0 r/w r/w transfer mode select 1 and 0 selects the transfer mode. 00: normal transfer mode 01: block transfer mode 10: repeat transfer mode 11: cluster transfer mode 11 tseie 0 r/w transfer size error interrupt enable enables or disables a transfer size error interrupt request. when this bit is set to 1 and the transfer counter value becomes smaller than the data access size for one transfer request by exdmac transfer, the dte bit is cleared to 0 by the next transfer request. at the same time, the esif bit is set to 1 to indicate that a transfer size error interrupt request is generated. when cluster transfer read/write address mode is specified, this bit should be set to 1. transfer size error interrupt request occurs in the following conditions: ? in normal transfer and repeat transfer modes, the total transfer size set in edtcr is smaller than the data access size ? in block transfer mode, the total transfer size set in edtcr is smaller than the block size ? in cluster transfer mode, the total transfer size set in edtcr is smaller than the cluster size 0: transfer size error interrupt request disabled 1: transfer size error interrupt request enabled 10 ? 0 r reserved they are always read as 0 and cannot be modified. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 379 of 1340 rej09b0499-0200 bit bit name initial value r/w description 9 esie 0 r/w transfer escape interrupt enable enables or disables a transfer escape end interrupt request occurred during exdma transfer. when this bit is set to 1, and the esif bit is set to 1, a transfer escape end interrupt is requested to the cpu or dtc. the transfer escape end interrupt request is canceled by clearing this bit or the esif bit to 0. 0: transfer escape interrupt request disabled 1: transfer escape interrupt request enabled 8 dtie 0 r/w data transfer interrupt enable enables or disables a transfer end interrupt request by the transfer counter. when this bit is set to 1 and the dtif bit is set to 1, a transfer end interrupt is requested to the cpu or dtc. the transfer end interrupt request is canceled by clearing this bit or the dtif bit to 0. 0: transfer end interrupt request disabled 1: transfer end interrupt request enabled 7 6 dtf1 dtf0 0 0 r/w r/w data transfer factor 1 and 0 selects a source to activa te exdmac. for external requests, a sampling method is selected by the edreqs bit. external requests should not be selected for edmdr_2 or edmdr_3. 00: auto-request (cycle steal mode) 01: auto-request (burst mode) 10: setting prohibited 11: external request 5 ? 0 r/w reserved the initial value should not be changed. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 380 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4, 3 ? all 0 r reserved they are always read as 0 and cannot be modified. 2 1 0 edmap2 edmap1 edmap0 0 0 0 r/w r/w r/w exdma priority levels 2 to 0 selects the exdmac priority level when using the cpu priority control function over dtc and exdmac. when the exdmac priority level is lower than the cpu priority level, exdmac masks the acceptance of transfer source and waits until the cpu priority level becomes low. the priority level can be set independently for each channel. this bit is enabled when the cpupce bit in cpupcr is 1. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) note: * only 0 can be written to these bits after 1 is read to clear the flag. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 381 of 1340 rej09b0499-0200 11.3.7 exdma address control register (edacr) edacr sets the operating modes and transfer methods. 31 ams 0 r/w 30 dirs 0 r/w 29 ? 0 r 28 ? 0 r 27 ? 0 r 24 ars0 0 r/w 26 rptie 0 r/w 25 ars1 0 r/w bit bit name initial value r/w 23 ? 0 r 22 ? 0 r 21 sat1 0 r/w 20 sat0 0 r/w 19 ? 0 r 16 dat0 0 r/w 18 ? 0 r 17 dat1 0 r/w bit bit name initial value r/w 15 sarie 0 r/w 14 ? 0 r 13 ? 0 r 12 sara4 0 r/w 11 sara3 0 r/w 8 sara0 0 r/w 10 sara2 0 r/w 9 sara1 0 r/w bit bit name initial value r/w 7 darie 0 r/w 6 ? 0 r 5 ? 0 r 4 dara4 0 r/w 3 dara3 0 r/w 0 dara0 0 r/w 2 dara2 0 r/w 1 dara1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 31 ams 0 r/w address mode select selects single address mode or dual address mode. when single address mode is selected, edack pin is valid due to the edacke bit setting in edmdr. 0: dual address mode 1: single address mode 30 dirs 0 r/w single address direction select specifies the data transfer direction in single address mode. in dual address mode, t he specification by this bit is ignored. in cluster transfer mode, the internal cluster buffer will be the source or destination in place of the external device with dack . 0: edsar transferred as a source address 1: eddar transferred as a destination address section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 382 of 1340 rej09b0499-0200 bit bit name initial value r/w description 29 to 27 ? all 0 r reserved they are always read as 0 and cannot be modified. 26 rptie 0 r/w repeat size end interrupt enable enables or disables a repeat size end interrupt request. when this bit is set to 1 and the next transfer source is generated at the end of a repe at-size transfer in repeat transfer mode, the dte bit in edmdr is cleared to 0. at the same time, the esif bit in edmdr is set to 1 to indicate that a repeat size end interrupt is requested. even if the repeat area is not specified (ars1, ars0 = b'10), the repeat size end in terrupt can be requested at the end of a repeat-size transfer. when this bit is set to 1 and the next transfer source is generated at the end of a bloc k- or cluster-size transfer in block transfer or cluster transfer mode, the dte bit in edmdr is cleared to 0. at the same time, the esif bit in edmdr is set to 1 to indi cate that the repeat size end interrupt is requested. 0: repeat size end interrupt request disabled 1: repeat size end interrupt request enabled 25 24 ars1 ars0 0 0 r/w r/w area select 1 and 0 select the block area or repeat area in block transfer, repeat transfer or cluster transfer mode. 00: block area/repeat area on the source address side 01: block area/repeat area on the destination address side 10: block area/repeat area not specified 11: setting prohibited 23, 22 ? all 0 r reserved they are always read as 0 and cannot be modified. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 383 of 1340 rej09b0499-0200 bit bit name initial value r/w description 21 20 sat1 sat0 0 0 r/w r/w source address update mode 1 and 0 these bits specify increm enting/decrementing of the transfer source address (edsar). when the transfer source is not specified in edsar in single address mode, the specification by these bits is ignored. 00: fixed 01: offset added 10: incremented (+1, +2, or +4 according to the data access size) 11: decremented ( ? 1, ? 2, or ? 4 according to the data access size) 19, 18 ? all 0 r reserved they are always read as 0 and cannot be modified. 17 16 dat1 dat0 0 0 r/w r/w destination address update mode 1 and 0 these bits specify increm enting/decrementing of the transfer destination address (eddar). when the transfer source is not specified in eddar in single address mode, the specificat ion by these bits is ignored. 00: fixed 01: offset added 10: incremented (+1, +2, or +4 according to the data access size) 11: decremented ( ? 1, ? 2, or ? 4 according to the data access size) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 384 of 1340 rej09b0499-0200 bit bit name initial value r/w description 15 sarie 0 r/w source address extended repeat area overflow interrupt enable enables or disables the source address extended repeat area overflow interrupt request. when this bit is set to 1, in the event of source address extended repeat area overflow, the dte bit is cleared to 0 in edmdr. at the same ti me, the esif bit is set to 1 in edmdr to indicate that the source address extended repeat area overflow interrupt is requested. when used together with block transfer mode, an interrupt is requested at the end of a block-size transfer. if the dte bit is set to 1 in edmdr for the channel on which transfer is terminated by an interrupt, transfer can be resumed from the state in which it ended. if a source address extended repeat area is not designated, the specification by this bit is ignored. 0: source address extended repeat area overflow interrupt request disabled 1: source address extended repeat area overflow interrupt request enabled 14, 13 ? all 0 r reserved they are always read as 0 and cannot be modified. 12 11 10 9 8 sara4 sara3 sara2 sara1 sara0 0 0 0 0 0 r/w r/w r/w r/w r/w source address extended repeat area these bits specify the source address (edsar) extended repeat area. t he extended repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. an extended repeat area size of 4 bytes to 128 mbytes can be specified. the setting interval is a power-of-two number of bytes. when extended repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the extended repeat area in the case of address incrementing, or the last address of the extended repeat area in the case of address decrementing. if sarie bit is set to 1, an interrupt can be requested when an extended repeat area overflow occurs. table 11.3 shows the settings and ranges of the extended repeat area. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 385 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 darie 0 r/w destination address extended repeat area overflow interrupt enable enables or disables a destination address extended repeat area overflow interrupt request. when this bit is set to 1, in the event of destination address extended repeat area overflow, the dte bit in edmdr is cleared to 0. at the same time, the esif bit in edmdr is set to 1 to indicate that a destination address extended repeat area overflow interrupt is requested. when used together with block transfer mode, an interrupt is requested at the end of a block-size transfer. if dte bit is set to 1 in edmdr for the channel on which transfer is terminated by an interrupt, transfer can be resumed from the state in which it ended. if a destination address extended repeat area is not designated, the specification by this bit is ignored. 0: destination address extended repeat area overflow interrupt request disabled 1: destination address extended repeat area overflow interrupt request enabled 6, 5 ? all 0 r reserved they are always read as 0 and cannot be modified. 4 3 2 1 0 dara4 dara3 dara2 dara1 dara0 0 0 0 0 0 r/w r/w r/w r/w r/w destination address extended repeat area these bits specify the destination address (eddar) extended repeat area. the extended repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. an extended repeat area size of 4 bytes to 128 mbytes can be specified. the setting interval is a power-of-two number of bytes. when extended repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the extended repeat area in the case of address incrementing, or the last address of the extended repeat area in the case of address decrementing. if the darie bit is set to 1, an interrupt can be requested when an extended repeat area overflow occurs. table 11.3 shows the settings and ranges of the extended repeat area. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 386 of 1340 rej09b0499-0200 table 11.3 settings and ranges of extended repeat area value of sara4 to sara0/ dara4 to dara0 range of extended repeat area 00000 not designated as extended repeat area 00001 lower 1 bit (2-byte area) designated as extended repeat area 00010 lower 2 bit (4-byte area) designated as extended repeat area 00011 lower 3 bit (8-byte area) designated as extended repeat area 00100 lower 4 bit (16-byte area) designated as extended repeat area 00101 lower 5 bit (32-byte area) designated as extended repeat area 00110 lower 6 bit (64-byte area) designated as extended repeat area 00111 lower 7 bit (128-byte area) designated as extended repeat area 01000 lower 8 bit (256-byte area) designated as extended repeat area 01001 lower 9 bit (512-byte area) designated as extended repeat area 01010 lower 10 bit (1-kbyte area) de signated as extended repeat area 01011 lower 11 bit (2-kbyte area) de signated as extended repeat area 01100 lower 12 bit (4-kbyte area) de signated as extended repeat area 01101 lower 13 bit (8-kbyte area) de signated as extended repeat area 01110 lower 14 bit (16-kbyte area) designated as extended repeat area 01111 lower 15 bit (32-kbyte area) designated as extended repeat area 10000 lower 16 bit (64-kbyte area) designated as extended repeat area 10001 lower 17 bit (128-kbyte area) designated as extended repeat area 10010 lower 18 bit (256-kbyte area) designated as extended repeat area 10011 lower 19 bit (512-kbyte area) designated as extended repeat area 10100 lower 20 bit (1-mbyte area) de signated as extended repeat area 10101 lower 21 bit (2-mbyte area) de signated as extended repeat area 10110 lower 22 bit (4-mbyte area) de signated as extended repeat area 10111 lower 23 bit (8-mbyte area) de signated as extended repeat area 11000 lower 24 bit (16-mbyte area) designated as extended repeat area 11001 lower 25 bit (32-mbyte area) designated as extended repeat area 11010 lower 26 bit (64-mbyte area) designated as extended repeat area 11011 lower 27 bit (128-mbyte area) designated as extended repeat area 111xx setting prohibited [legend] x: don't care section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 387 of 1340 rej09b0499-0200 11.3.8 cluster buffer registers 0 to 7 (clsbr0 to clsbr7) clsbr0 to clsbr7 are 32-bit readable/writable regi sters that store the tran sfer data. the transfer data is stored in order from clsbr0 to clsbr7 in cluster transfer mode. the data stored in cluster transfer mode or by the cpu write operation is held until the next cluster transfer or cpu write operation is performed. when reading the data stored in cluster transfer mode by the cpu, check the completion of cluster transfer and then perfor m only a cluster-size read specified for the cluster transfer. data with another size is undefined. in cluster transfer mode, the sa me clsbr is used for all channels. when the cpu write operation to clsbr conflicts with cluster tr ansfer, the contents of transferre d data are not guaranteed. when cluster transfer read/write addr ess mode is specified and if another channel is set for cluster transfer, the transferred data may be overwritten. 31 undefined r/w 30 undefined r/w 29 undefined r/w 28 undefined r/w 27 undefined r/w 24 undefined r/w 26 undefined r/w 25 undefined r/w bit bit name initial value r/w 23 undefined r/w 22 undefined r/w 21 undefined r/w 20 undefined r/w 19 undefined r/w 16 undefined r/w 18 undefined r/w 17 undefined r/w bit bit name initial value r/w 15 undefined r/w 14 undefined r/w 13 undefined r/w 12 undefined r/w 11 undefined r/w 8 undefined r/w 10 undefined r/w 9 undefined r/w bit bit name initial value r/w 7 undefined r/w 6 undefined r/w 5 undefined r/w 4 undefined r/w 3 undefined r/w 0 undefined r/w 2 undefined r/w 1 undefined r/w bit bit name initial value r/w section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 388 of 1340 rej09b0499-0200 11.4 transfer modes 11.4.1 ordinary modes the ordinary modes of exdmac are summarized in table 11.4. the transfer mode can be set independently for each channel. table 11.4 ordinary modes address register address mode transfer mode activation source common function source destination dual address mode ? normal transfer mode ? repeat transfer mode ? block transfer mode (repeat size/ block size = 1 to 65,536 bytes/ word/longword) ? auto-request (activated by the cpu) ? external request * ? total transfer size: 1 to 4 gbytes, or no specification ? offset addition ? extended repeat area function edsar eddar single address mode * ? direct data transfer to/from external devices using edack pin instead of source or dest ination address register ? above transfer mode can be specified in addition to address register setting ? one transfer possible in one bus cycle (transfer mode variations are the same as in dual address mode.) edsar/ edack edack / eddar note ? only channel 0 or 1 can be selected. when the activation source is an auto-request, cycle steal mode or burst mode can be selected. when the total transfer size is not specified (edtcr = h'00000000), the transfer counter is halted and the transfer count is not rest ricted, allowing co ntinuous transfer. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 389 of 1340 rej09b0499-0200 11.4.2 cluster transfer modes table 11.5 shows cluster transfer modes. cluster transfer mode can be set independently for each channel. the cluster buffer is common to all channels. table 11.5 cluster transfer mode address mode activation source common function transfer source cluster buffer function transfer destination cluster transfer dual address mode edsar read from the transfer source and written to the transfer destination eddar cluster transfer read address mode (dirs = 0) edsar read from the transfer source ? cluster transfer write address mode (dirs = 1) ? auto-request (activated by the cpu) ? external request * ? cluster size one access size (byte/word/longword) to 32 bytes ? total transfer size 1 to 4 gbytes, or no specification ? offset addition ? extended repeat area function ? written to the transfer destination eddar note * only channel 0 or 1 can be selected. in cluster transfer mode, the specified cluster size is transferre d in response to a single transfer request. the cluster size can be from one access si ze (byte, word, or longword) to 32 bytes. within a cluster, a cluster-size transfer is performed in burst transfer mode. with a cluster-size access in cluster transfer mode (dual address mode), block transfer mode (dual address mode) is used. with auto-requests, cycle steal mode is set. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 390 of 1340 rej09b0499-0200 11.5 mode operation 11.5.1 address modes (1) dual address mode in dual address mode, the transf er source address is set in edsa r, and the transfer destination address is set in eddar. one tran sfer operation is executed in two bus cycles. (when the data bus width is smaller than the data access size or wh en the address to be accessed is not at the data boundary of the data access size, the bus cycle is divided, resulting more than two bus cycles.) in a transfer operation, the data on the transfer so urce address is read in the first bus cycle, and is written to the transfer destination address in the next bus cycle. these consecutive read and write cycles are i ndivisible: another bus cycle (external access by another bus master, refresh cycle, or external bu s release cycle) does no t occur between these two cycles. etend pin output can be enabled or disabled by means of the etende bit in edmdr. etend is output for two consecutive bus cycles. when an id le cycle is inserted before the bus cycle, the etend signal is also output in the idle cycle. the edack signal is not output. figure 11.2 shows an example of the timing in dual address mode and figure 11.3 shows the dual address mode operation. address bus b rd wr etend exdma read cycle exdma write cycle edsar eddar figure 11.2 example of timing in dual address mode section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 391 of 1340 rej09b0499-0200 transfer address t a address b a address update setting the source address incremented the destination adderss is fixed address t b figure 11.3 dual address mode operation (2) single address mode in single address mode, the edack pin is used instead of edsar or eddar to transfer data directly between an external device and external memory. one transfer oper ation is executed in one bus cycle. only channel 0 or 1 can be selected for single address mode. in this mode, the data bus width must be the same as the data access size. for details on the data bus width, see s ection 9, bus controller (bsc). in this mode, the exdmac accesses the transfer sour ce or transfer destinat ion external device by outputting the strobe signal ( edack ) for the external device with dack , and at the same time accesses the other external device in the transfer by outputting an address. in this way, exdma transfer can be executed in one bu s cycle. in the example of transf er between external memory and an external device with dack shown in figure 11.4, data is output to the data bus by the external device and written to external me mory in the same bus cycle. the transfer direction, that is whether the external device with dack is the transfer source or transfer destination, can be speci fied with the dirs bit in edacr. transfer is performed from the external memory (edsar) to the external device with dack when dirs = 0, and from the external device with dack to the external memory (eddar) when dirs = 1. the setting in the source or destination address register no t used in the transfer is ignored. the edack pin output is valid by the setting of edacke bit in edmdr when single address mode is selected. the edack pin output is active-low. etend pin output can be enabled or disabled by means of the etende bit in edmdr. etend is output for one bus cycle. when an idle cycle is inserted before the bus cycle, the etend signal is also output in the idle cycle. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 392 of 1340 rej09b0499-0200 figure 11.5 shows an example of the timing in single address mode and figure 11.6 shows the single address mode operation. lsi data flow external address bus external data bus exdmac edack edreq external memory external device with dack figure 11.4 data flow in single address mode section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 393 of 1340 rej09b0499-0200 exdma cycle edsar address for external memory space rd signal to external memory space data output by external memory address bus b rd wr edack etend data bus exdma cycle eddar address for external memory space wr signal to external memory space b address bus transfer from external memory to external device with dack rd wr edack etend data bus data output from external device with dac k transfer from external device with dack to external memory high high figure 11.5 example of timing in single address mode address t address b edac k transfer figure 11.6 single address mode operation section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 394 of 1340 rej09b0499-0200 11.5.2 transfer modes (1) normal transfer mode in normal transfer mode , transfer of one data access size unit is processed in response to one transfer request. the total transfer size of up to 4 gbytes can be set by edtcr. edbsr is invalid in normal transfer mode. the etend signal is output only for the last exdma transfer. the edrak signal is output each time a transfer request is accepted an d transfer processing is started. figure 11.7 shows examples of transfer timing in normal transfer mode and figure 11.8 shows the normal transfer mode opera tion in dual address mode. read write read write exdma transfer cycle last exdma transfer cycle bus cycle transfer conditions: dual address mode, auto-request mode transfer conditions: single address mode, external request mode etend edreq edack exdma exdma bus cycle edrak figure 11.7 examples of timing in normal transfer mode transfer total transfer size (edtcr) address t a address b a address t b address b b figure 11.8 normal transfer mode operation section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 395 of 1340 rej09b0499-0200 (2) repeat transfer mode in repeat transfer mode, transf er of one data access size unit is processed in response to one transfer request. the total transfer size of up to 4 gbytes can be set by edtcr. the repeat size of up to 64 kbytes data access size can be set by edbsr. the ars1 and ars0 bits in edacr specify the rep eat area on the source address or destination address side. the address sp ecified for the repeat area is restored to the transfer start address at the end of a repeat-size transfer. this operation contin ues until transfer of to tal transfer size set in edtcr ends. edtcr specified with h'00000000 is assumed as free-running mode and the repeat transfer continues until the dte bit in edmdr is cleared to 0. at the end of a repeat-size transfer, the exdma transfer is halted tempor arily and a repeat size end interrupt is requested to the cpu or dtc. wh en the rptie bit in edacr is set to 1 and the next transfer request is generated at the end of a repeat-size transfer, the es if bit in edmdr is set to 1 and the dte bit in edmdr is cleared to 0 to terminate the transfer. at this time, an interrupt is requested to the cpu or dtc when the esie bit in edmdr is set to 1. the timing of exdma transfer including the etend or edrak output is the same as for normal transfer mode. figure 11.9 shows the repeat transfer mode operation in dual address mode. the operation without specifying a repeat area on the source or de stination address side is the same as for the normal transfer mode operation shown in figure 11.8. in this case, a repeat size end interrupt can also be generated at the end of a repeat-size transfer. transfer address t a address t b address b b address b a operation with the repeat area specified on the source address side total transfer size (edtcr) repeat size (bkszh data access size) figure 11.9 repeat transfer mode operation section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 396 of 1340 rej09b0499-0200 (3) block transfer mode in block transfer mode, transfer of one block size unit is processed in response to one transfer request. the total transfer size of up to 4 gbytes can be set by edtcr. the block size of up to 64 kbytes data access size can be set by edbsr. a transfer request from another channel is held pending during one block transfer. when one- block transfer is completed, the bus master ship is released for another bus master. a block area can be specified by the ars1 or ars0 bit in edacr on the source or destination address side. the address specified for the block area is restored to the transfer start address each time one-block transfer completes. when no repeat area is specified on the source and destination address sides, the address is not restored to the transfer star t address and the operation proceeds to the next sequence. a repeat size end interrupt can be generated. the etend signal is output for each block transfer in the exdma transfer cycle in which the block ends. the edrak signal is output once for one transfer request (for transfer of one block). caution is required when setting the extended repeat area overflow interrupt in block transfer mode. for details, see section 11.5.5 , extended repeat area function. figure 11.10 shows an example of exdma transfer timing in block transfer mode. the transfer conditions are as follows: address mode: single address mode data access size: in bytes one block size: 3 bytes section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 397 of 1340 rej09b0499-0200 figure 11.11 shows the block transfer mode operation in single address mode and figure 11.12 shows the block transfer mode operation in dual address mode. cpu cpu exdmac exdmac exdmac cpu bus cycle etend edreq cpu cycle not generated one-block transfer cycle edrak figure 11.10 example of block transfer mode transfer address t address b edac k block bkszh data access size figure 11.11 block transfer mode operation in single address mode (with block area specified) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 398 of 1340 rej09b0499-0200 transfer address t a address b a address t b address b b nth block second block first block nth block second block first block bkszh data access size total transfer size (edtcr) figure 11.12 block transfer mode operation in dual address mode (without block area specified) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 399 of 1340 rej09b0499-0200 11.5.3 activation sources the exdmac is activated by an auto request or an external request. this activation source is selected by the dtf1 or dtf0 bit in edmdr. (1) activation by auto-request the transfer request signal is automatically generated in exdmac with auto-request activation when no transfer request signal is generated fr om external or periph eral modules, incase of transfer among memory or between memory and peripheral modules that cannot generate the transfer request signal. the tran sfer starts when the dte bit in edmdr is set to 1 with auto- request activation. the bus mode can be selected from cycle steal mode and burst mode with auto- request activation. (2) activation by external request transfer is started by the transfer request signal ( edreq ) from the external device for activation by an external request. when the exdma transfer is enabled (dte = 1), the exdma transfer starts by edreq input. only channel 0 or 1 can be select ed for activation by an external request. the transfer request signal is accepted by the edreq pin. the edreqs bit in edmdr selects whether the edreq is detected by falling edge sensing or low level sensing. when the edrake bit in edmdr is set to 1, th e signal notifying transfer request acceptance is output from the edrak pin. the edrak signal is accepted for one external request and is output when transfer processing starts. when specifying an external requ est as an activation source, set the ddr bit to 0 and the icr bit to 1 on the corresponding pin in advance. for details, see section 13, i/o ports. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 400 of 1340 rej09b0499-0200 11.5.4 bus mode there are two bus modes: cycl e steal mode and burst mode. for auto-request activation, either cycle steal mode or burst mode can be selected by the dtf0 bit in edmdr. when the activation source is an external request, cycle steal mode is used. (1) cycle steal mode in cycle steal mode, the exdmac releases the bu s mastership at the end of each transfer of a transfer unit (byte, word, longword, one block size, or one cluster size). if there is a subsequent transfer request, the exdmac takes back the bu s mastership, performs another transfer-unit transfer, and then releases the bu s mastership again at the end of the transfer. this procedure is repeated until the transfer end condition is satisfied. if a transfer request occurs in another channel during exdma transfer, the bus mastership is temporarily released for another bus master, then transfer is performed on the channel for which the transfer request was issued. fo r details on the operation when th ere are transfer requests for a number of channels, see section 11.5.8, channel priority order. figure 11.13 shows an example of the timing in cycle steal mode. the transfer conditions are as follows: ? address mode: single address mode ? sampling method on the edreq pin: low level sensing ? cpu internal bus master is operating in external space cpu cpu cpu exdmac cpu exdmac edreq edrak bus cycle bus mastership returned temporarily to cpu figure 11.13 example of ti ming in cycle steal mode section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 401 of 1340 rej09b0499-0200 (2) burst mode in burst mode, once the exdmac acquires the bu s mastership, it continues transferring data, without releasing the bus mastership, until the tran sfer end condition is sa tisfied. in burst mode, once transfer is started it is not interrupted even if there is a transfer request for another channel with higher priority. when the burst mode chan nel finishes its transfer, it releases the bus mastership in the next cycle in the same way as in cycle steal mode. however, when the ebccs bit in bcr2 of the bus controller is set to 1, the exdmac can temporarily release the bus mastership for another bus master when an exte rnal access request is generated from another bus master. in block transfer mode and cluster transfer mode, the setting of burst mode is invalid (one-block or one-cluster transfer is processed in the same way as in burst mode). the exdmac always operates in cycle steal mode. when the dte bit is cleared to 0 in edmdr, exdma transfer is halted. however, exdma transfer is executed fo r all transfer requests generated within the exdmac until the dte bit is cleared to 0. if a transfer size error interrupt, a rep eat size end interrupt, or extended repeat area overflow interrupt is generated, the dte bit is cleared to 0 and transfer is terminated. figure 11.14 shows an example of the timing in burst mode. cpu cpu cpu cpu exdmac exdmac exdmac bus cycle cpu cycle not generated figure 11.14 example of timing in burst mode 11.5.5 extended repeat area function the exdmac has a function for designating an exte nded repeat area for source addresses and/or destination addresses. when an extended repeat area is designated, the address register values repeat within the range specified as the extended repeat area. normally, wh en a ring buffer is involved in a transfer, an operation is required to restore the address register value to the buffer start address each time the addre ss register value becomes the last address in the buffer (i.e. when ring buffer address overflow occurs). however, if the extended repeat area function is used, the operation that restores the a ddress register value to the buffer start address is processed automatically within the exdmac. the extended repeat area function can be set independently for the source address register (edsar) and the destination address register (eddar). section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 402 of 1340 rej09b0499-0200 the source address extended rep eat area is specified by bits sara4 to sara0 in edacr, and the destination address extended repeat area by bits dara 4 to dara0 in edacr. the size of each extended repeat area can be specified independently. when the address register value is the last addres s in the extended repeat area and extended repeat area overflow occurs, exdma transfer can be te mporarily halted and an extended repeat area overflow interrupt request can be generated for the cpu. if the sarie bit in edacr is set to 1, and the edsar extended repeat area overflows, the es if bit is set to 1 and the dte bit cleared to 0 in edmdr, and transfer is terminated. if the esie bit is set to 1 in edmdr, an extended repeat area overflow interrupt is requested to the cpu. if the darie bit in edacr is set to 1, the above applies to the destination address register. if th e dte bit in edmdr is set to 1 during interrupt generation, transfer is resumed. figure 11.15 illustrates the operation of the extended repeat area function. external memory when lower 3 bits (8-byte area) of edsar are designated as extended repeat area (sara4 to sara0 = b'00011) repeat extended repeat area overflow interrupt can be requested range of edsar values h'23fffe h'23ffff h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240008 h'240009 h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 ... ... figure 11.15 example of extended repeat area function operation section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 403 of 1340 rej09b0499-0200 caution is required when the extended repeat area overflow interrupt is used together with block transfer mode. if transfer is alwa ys terminated when extended repeat area overflow occurs in block transfer mode, the block size must be a power of two, or alternativ ely, the address register value must be set so that the end of a block coincide s with the end of the extended repeat area range. if extended repeat area overflow occurs during a block-size transfer in block transfer mode, the extended repeat area overflow interrupt request is held pending until the end of the block, and transfer overrun will occur. the same caution is required when the extended re peat area overflow inte rrupt is used together with cluster transfer mode. figure 11.16 shows an example in which block tran sfer mode is used toge ther with the extended repeat area function. external memory range of edsar values first block transfer second block transfer h'23fffe h'23ffff h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240008 h'240009 h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240000 h'240001 h'240002 h'240003 h'240004 h'240000 h'240001 h'240005 h'240006 h'240007 interrupt requested block transfer in progress when lower 3 bits (8-byte area) of edsar are designated as extended repeat area (sara4 to sara0 = 3), and block size of 5 (bits 23 to 16 in edtcr = 5) is set in block transfer mode. ... ... figure 11.16 example of extended repeat area function operation in block transfer mode section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 404 of 1340 rej09b0499-0200 11.5.6 address update function using offset there are the following update me thods for transfer destination and source addresses: fixed, increment/decrement by 1, 2 or 4, and offset addi tion. with the offset addition method, the offset specified by the offset register (edofr) is added each time the exdmac performs a data- access-size transfer. this function allows the mid- addresses being skipped during data transfer. figure 11.17 shows the address update methods. 0 + offset 1, 2, or 4 address not updated value, that corresponds to data access size, incremented, decremented to/from the address (successive addresses) (a) fixed (b) increment/decrement by 1, 2 or 4 (c) offset addition external memory external memory external memory offset value added to the address (insuccessive addresses) figure 11.17 address update method for the fixed method (a), the same address is always indicated without the transfer destination or source address being updated. for the method of in crement/decremen t by 1, 2 or 4 (b), the value corresponding to the data access size is incremented or decremented to or from the transfer destin ation or source address each time the data is transferred. a byte, word, or longword can be specifi ed for the data access size. the value used for increment or decrement of an addres s is 1 for a byte-size , 2 for a word-size , and 4 for a longword-size transfer. this function allows continuous address transfer of exdmac. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 405 of 1340 rej09b0499-0200 for the offset addition method (c), address opera tion is not performed based on the data access size. the exdmac adds the value set by edofr to the transfer destination or source address for each time the data is transferred. the exdmac sets the offset value in edof r and operates using edsar or eddar. the exdmac can only add the offset value, but subtr action of the offset value is also possible by setting a negative value in edofr. specify a twos complement for a negative offset value. (1) basic transfer using offset figure 11.18 shows the basic operation of transfer using an offset. data 1 offset value address a1 transfer address a2 = address a1 + offset address b1 address b2 = address b1 + 4 address b3 = address b2 + 4 address b4 = address b3 + 4 address b5 = address b4 + 4 address a3 = address a2 + offset address a4 = address a3 + offset address a5 = address a4 + offset offset value offset value offset value transfer source: offset added transfer destination: incremented by 4 (with a longword-size selected) data 1 data 2 data 3 data 4 data 5 : : : : data 2 data 3 data 4 data 5 figure 11.18 address update function using offset section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 406 of 1340 rej09b0499-0200 in figure 11.18, the offset addition method is set for updating the transfer source address, and the method of increment/decrement 1, 2 or 4 is set for updating the transfer destination address. for updating the second and subsequent transfer source addresses, the data of the address for which the offset value is added to the previous transfer address is read. this data is written to the successive area on the transfer destination. (2) example of xy conversion using offset figure 11.19 shows the xy conversion by combining the repeat transfer mode and offset addition. data 1 data 2 data 3 data 4 data 5 data 11 data 12 data 16 data 16 data 15 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 5 data 9 data 13 data 2 data 11 data 15 data 12 data 8 data 4 data 7 data 3 data 14 data 10 data 6 first cycle 1st transfer second cycle 2nd transfer third cycle 3rd transfer first cycle first cycle second cycle third cycle fourth cycle data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 5 data 9 data 13 data 12 data 2 data 11 data 15 data 16 data 8 data 4 data 7 data 3 data 14 data 10 data 6 transfer transfer interrupt requested interrupt requested address restored interrupt requested address restored transfer source address overwritten by cpu transfer source address overwritten by cpu offset value offset value offset value figure 11.19 xy conversion by combining repeat transfer mode and offset addition in figure 11.19, the source addres s side is set as a repeat area in edacr and the offset addition is set in edacr. the offset value is the address that corresponds to 4 data access size (example: for a longword-size transfer, h'00000010 is sp ecified in edofr). the repeat size is 4 data access size (example: for a lo ngword-size transfer, 4 4 = 16 bytes are specified as a repeat size). the increment by 1, 2 or 4 is set for the transfer destination. the rptie bit in edacr is set to 1 to generate a repeat size end interrupt requ est at the end of a repeat-size transfer. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 407 of 1340 rej09b0499-0200 when transfer starts, the offset value is added to the transfer source address and the data is transferred. the data is aligned in the order of transfer in the transfer destination. after up to data 4 is transferred, the exdmac assumes that a re peat-size transfer completed, and restores the transfer source address to the transfer start address (address of transfer source data 1). at the same time, a repeat size end interrupt is requested. this interrupt request aborts th e transfer te mporarily. overwrite the edsar value to the data 5 address by accessing th e i/o register vi a the cpu. (for longword transfer, add 4 to the address of data 1.) when the dte bit in edmdr is set to 1, transfer is resumed from the state in which the transfer is aborted. the transfer source data is xy- converted and transferred to th e transfer destination by re peating the above processing. figure 11.20 shows the xy conversion flow. : user side :exdmac side start set address and transfer count set repeat transfer mode set dte bit to 1 transfer request accepted data transfer transfer counter and repeat size decremented enable repeat cancel interrupt set transfer source address + 4 transfer source address restored end of repeat size interrupt requested transfer count = 0 repeat size = 0 end no no ye s ye s (for longword transfer) figure 11.20 flow of xy conversion combining repeat transfer mode and offset addition section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 408 of 1340 rej09b0499-0200 (3) offset subtractio n specification to set a negative value in edofr, specify a twos complement as an offset value. a twos complement is derived by the following expression: [twos complement expression for negative offset value] = ? [offset value] + 1 ( ? : bit reverse) example: twos complement expression of h'0001ffff = h'fffe0000 + h'00000001 = h'fffe0001 a twos complement can be derived by the neg.l instruction of the cpu. 11.5.7 registers during exdma transfer operation exdmac register values are updated as exdma transfer processing is performed. the updated values depend on various settings and the transf er status. the following registers and bits are updated: edsar, eddar, edtcr, bits bkszh and bksz in edbsr, and bits dte, act, errf, esif and dtif in edmdr. (1) exdma source address register (edsar) when the edsar address is accessed as the transfer sour ce, the edsar value is output, and then edsar is updated with the address to be accessed next. bits sat1 and sat0 in edacr specify increm enting or decrementing. the address is fixed when sat1 and sat0 = b 00, incremented by offset regist er value when sat1 and sat0 = b 01, incremented when sat1 and sat0 = b 10, and decremented when sat1 and sat0 = b 11. (the increment or decrement value is determined by the data access size.) the dtsz1 and dtsz0 bits in edmdr set the data access size. when dtsz1 and dtsz0 = b 00, the data is byte-size and the address is in cremented or decremented by 1. when dtsz1 and dtsz0 = b 01, the data is word-size an d the address is in cremented or decremented by 2. when dtsz1and dtsz0 = b 10, the data is longword-size and the address is incremented or decremented by 4. when a word-size or longword-si ze is specified but the source address is not at the word or longword boundary, the data is divided into bytes or words for reading. when a word or longword is divided for reading, the address is incremented or decremented by 1 or 2 according to an actual byte-or word-size read. after a wo rd-size or longword-size read, the address is incremented or decremented to or from the read start address according to the setting of sat1 and sat0. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 409 of 1340 rej09b0499-0200 when a block area (repeat area) is set for the sour ce address in block transfer mode (or repeat transfer mode), the source address is restored to the transfer start address at the end of block-size (repeat-size) transfer and is no t affected by ad dress updating. when an extended repeat area is set for the source addres s, the operation conforms to that setting. the upper addresses set for the extended repeat area is fixed, and is not affected by address updating. when edsar is read during a transfer operation, a longword access must be used. during a transfer operation, ed sar may be updated without regard to accesses from the cpu, and the correct values may not be read if the upper and lower words are read separately. do not write to edsar for a channel on which a tr ansfer operation is in progress. (2) exdma destination address register (eddar) when the eddar address is accessed as the transf er destination, the ed dar value is output, and then eddar is updated with the address to be accessed next. bits dat1 and dat0 in edacr specify incremen ting or decrementing. the address is fixed when dat1 and dat0 = b 00, incremented by offset register value when dat1 and dat0 = b 01, incremented when dat1 and dat0 = b 10, and decremented when dat1 and dat0 = b 11. (the increment or decrement value is determined by the data access size.) the dtsz1 and dtsz0 bits in edmdr set the data access size. when dtsz1 and dtsz0 = b 00, the data is byte-size and the address is in cremented or decremented by 1. when dtsz1 and dtsz0 = b 01, the data is word-size an d the address is in cremented or decremented by 2. when dtsz1 and dtsz0 = b 10, the data is longword-size and the address is incremented or decremented by 4. when a word-size or longword-s ize is specified but the destination address is not at the word or longword boundary, the data is divided into bytes or words for writing. when a word or a longword is divided for writing, the ad dress is incremented or decremented by 1 or 2 according to an actual byte- or word-size written. after a word-size or lo ngword-size write, the address is incremente d or decremented to or from the write start address according to the setting of sat1 and sat0. when a block area (repeat area) is set for the destin ation address in block transfer mode (or repeat transfer mode), the destination addr ess is restored to the transfer start address at the end of block- size (repeat-size) transfer and is not affected by address updating. when an extended repeat area is set for the des tination address, the operation conforms to that setting. the upper addresses set for the extended repeat area is fixed, and is not affected by address updating. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 410 of 1340 rej09b0499-0200 when eddar is read during a transfer operation, a longword access must be used. during a transfer operation, eddar may be updated without regard to accesses from the cpu, and the correct values may not be read if the upper and lower words are read separately. do not write to eddar for a channel on which a tran sfer operation is in progress. (3) exdma transfer count register (edtcr) when an exdma transfer is performed, the value in edtcr is decremented by the number of bytes transferred. when a byte is transferred, th e value is decremented by 1; when a word is transferred, the value is decremented by 2; when a longword is transferred, the value is decremented by 4. however, when the edtcr va lue is 0, tran sfers are not counted and the edtcr value does not change. all of the bits of edtcr may change, so when edtcr is read by the cpu during exdma transfer, a longword access must be used. during a transfer operation, edtcr may be updated without regard to accesses from th e cpu, and the correct values may not be read if the upper and lower words are read separately. do not write to edtcr for a channel on which a transfer operation is in progress. if there is conflict between an ad dress update associated with exdma transfer and a write by the cpu, the cpu write has priority. in the event of conflict between an edtcr update from 1, 2, or 4 to 0 and a write (of a nonzero value) by the cpu, the cpu write value has pr iority as the edtcr value, but transfer is terminated. (4) exdma block size register (edbsr) edbsr is valid in block transfer or repeat transfer mode. edbsr31 and edbsr16 are used as bkszh and edbsr15 and edbsr0 for bksz. the 16 bits of bkszh holds a block size and repeat size and their values do not change. the 16 bits of bksz functions as a block size or repeat size counter, the value of which is decremented by 1 when one data transfer is performed. when the bksz value is determined as 0 during exdma transfer, the exdmac does not store 0 in bksz and stores the bkszh value. the upper 16 bits of edbsr is neve r updated, allowing a word-size access. do not write to edbsr for a channel on wh ich a transfer operation is in progress. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 411 of 1340 rej09b0499-0200 (5) dte bit in edmdr the dte bit in edmdr is written to by the cpu to control enabling and disabling of data transfer, but may be cleared to 0 automatically by the exdmac due to the exdma transfer status. conditions for dte bit clearing by th e exdmac include the following: ? when the specified total transfer size is completely transferred ? a transfer size error in terrupt is requested, and transfer ends ? a repeat size end interrupt is requested, and transfer ends ? when an extended repeat area overflow in terrupt is requested, and transfer ends ? when an nmi interrupt is generated, and transfer halts ? when an address error is generated, and transfer halts ? a reset ? hardware standby mode ? when 0 is written to the dte bit, and transfer halts writes (except to the dte bit) are prohibited to re gisters of a channel for which the dte bit is set to 1. when changing register settings after a 0-write to the dte bit, it is necessary to confirm that the dte bit has been cleared to 0. figure 11.21 shows the procedure for changing register settings in an operating channel. [1] write 0 to the dte bit in edmdr [2] read dte bit. [3] confirm that dte bit = 0. if dte bit = 1, this indicates that exdma transfer is in progress. [4] write the required set values to the registers. read dte bit write 0 to dte bit change register settings dte bit = 0 [1] [2] [3] [4] no yes changing register settings in operating channel register setting changes completed figure 11.21 procedure fo r changing register settings in operating channel section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 412 of 1340 rej09b0499-0200 (6) act bit in edmdr the act bit in edmdr indicates whether the exdm ac is in standby or active state. when dte = 0 and dte = 1 (transfer request wait status) are specified, the act bit is set to 0. in another case (exdmac in the active state), the act bit is set to 1. the act bit is held to 1 during exdma transfer even if 0 is written to the dte bit to halt transfer. in block transfer mode, a block-size transfer is not halted even if 0 is written to the dte bit to halt transfer. the act bit is held to 1 until a block- size transfer completes af ter 0 is written to the dte bit. in burst mode, transfer is halted after up to three times of exdma transfers are performed since the bus cycle in which 0 is written to the dte bit has been processed. the act bit is held to 1 between termination of the last exdm a cycle and 0-write in the dte bit. (7) errf bit in edmdr this bit specifies termination of transfer by exdmac clearing the dte bit to 0 for all channels if an address error or nmi interrupt is generated. the exdmac also sets 1 to the errf bit of edmdr_0 regardless of the exdmac operation to indicate that an address error or nmi interrupt is generated. however, when an address error or an nmi interrupt has been generated in exdmac module stop mode, the errf bit is not set to 1. (8) esif bit in edmdr the esif bit in edmdr is set to 1 when a transfer size interrupt, repeat si ze end interrupt, or an extended repeat area overflow interrupt is requeste d. when the esif bit is set to 1 and the esie bit in edmdr is set to 1, a transfer escape interrupt is requested to the cpu or dtc. the timing that the esif bit is set to 1 is when the exdma transfer bus cycle (the source of an interrupt request) terminates, the act bit in edmd r is set to 0, and transfer is terminated. when the dte bit is set to 1 to resume transfer during interrupt processing, the esif bit is automatically cleared to 0 to cancel the interrupt request. for details on interrupts, see section 11.9, interrupt sources. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 413 of 1340 rej09b0499-0200 (9) dtif bit in edmdr the dtif bit in edmdr is set to 1 after the data of total transfer size is transferred completely by exdma transfer. when the dtif bit is set to 1 and the dtie bit in edmdr is set to 1, a transfer end interrupt by the tran sfer counter is requested to the cpu or dtc. the timing that the dtif bit is set to 1 is when the exdma transfer bus cycle is terminated, the act bit in edmdr is set to 0, and the transfer is terminated. when the dte bit is set to 1 to resume transfer during interrupt processing, the dtif bit is automatically cleared to 0 to cancel the interrupt request. for details on interrupts, see section 11.9, interrupt sources. 11.5.8 channel priority order the priority order of the exdmac channels is: channel 0 > channel 1 > channel 2 > channel 3. table 11.6 shows the exdmac channel priority order. table 11.6 exdmac ch annel priority order channel channel priority channel 0 channel 1 channel 2 channel 3 high low if transfer requests occur simultaneously for a number of channels, the highest-priority channel according to the priority order is selected for transfer. transfer starts after the channel in progress releases the bus. if a bus request is issued from another bus master other than exdmac during a transfer operation, another bu s master cycle is initiated. channels are not switched during burst transfer, a block-size transfer in block transfer mode or a cluster-size transfer in cluster transfer mode. figure 11.22 shows an example of the transfer timing when transfer requests occur simultaneously for channels 0, 1, and 2. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 414 of 1340 rej09b0499-0200 channel 0 channel 1 channel 2 channel 0 transfer channel 1 transfer channel 2 transfer channel 0 channel 1 channel 2 idle idle request cleared request cleared request cleared request held request held request held selected selected not selected address bus channel 0 channel 1 channel 2 b exdmac control figure 11.22 example of channel priority timing 11.5.9 basic bus cycles an example of the basic bus cycl e timing is shown in figure 11.23. in this example, word-size transfer is performed from 16-b it, 2-state access space to 8-bit, 3- state access space. when the bus mastership is transferred from the cpu to the exdmac, a source address read and destination address write are performe d. the bus is not released in resp onse to another bus request, etc., between these read and write operations. as like cpu cycles, exdmac cycles conform to the bus controller settings. cpu cycle exdmac cycle (one word transfer) cpu cycle address bus b t 1 t 2 t 1 t 2 t 3 t 1 t 2 t 3 source address destination address rd lhwr llwr high figure 11.23 example of exdma transfer bus timing section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 415 of 1340 rej09b0499-0200 11.5.10 bus cycles in dual address mode (1) normal transfer mode (cycle steal mode) in cycle steal mode, the bus is released after on e byte, word, or longword has been transferred. while the bus is released, one cpu, dmac, or dtc bus cycle is initiated. figure 11.24 shows an example of transfer when etend output is enabled, and word-size, normal transfer mode (cycle steal mode) is performe d from external 16-bit, 2-state access space to external 16-bit, 2-state access space. exdma read exdma write address bus exdma read exdma write exdma read exdma write b rd lhwr , llwr etend bus release last transfer cycle bus release bus release bus release figure 11.24 example of normal transfer mode (cycle steal mode) transfer figures 11.25 and 11.26 show examples of tr ansfer when etend output is enabled, and longword-size, normal tran sfer mode (cycle steal mode) is perf ormed from external 16-bit, 2-state access space to external 16 -bit, 2-state access space. in figure 11.25, the transfer so urce (sar) address is not at a lo ngword boundary and the transfer destination (dar) address is at the longword boundary. in figure 11.26, the transfer so urce (sar) address is at the longword boundary and the transfer destination (dar) address is not at the longword boundary. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 416 of 1340 rej09b0499-0200 exdma byte read cycle exdma byte read cycle exdma word read cycle exdma word write cycle exdma word write cycle exdma byte read cycle exdma byte read cycle exdma word read cycle exdma word write cycle exdma word write cycle address bus b rd llwr lhwr tend bus released bus released bus released last transfer cycle m and n are integers. 4m + 1 4m + 2 4m + 4 4n + 4 4n + 6 4n 4n + 2 4m + 5 4m + 6 4m + 8 figure 11.25 example of normal transfer mode (cycle steal mode) transfer (transfer source edsar = odd addre ss, source address incremented) exdma word read cycle exdma word read cycle exdma byte write cycle exdma byte write cycle exdma byte write cycle exdma word write cycle exdma word read cycle exdma word read cycle exdma byte write cycle exdma word write cycle address bus b rd llwr lhwr etend bus released bus released bus released last transfer cycle m and n are integers. 4n + 5 4m + 2 4m 4n + 6 4n + 8 4n + 4 4m + 4 4m + 6 4n + 1 4n + 2 figure 11.26 example of normal transfer mode (cycle steal mode) transfer (transfer destinatio n eddar = odd address, dest ination addres s decremented) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 417 of 1340 rej09b0499-0200 (2) normal transfer mode (burst mode) in burst mode, one-byte, one-word, or one-longword transfer is executed continuously until the transfer end condition is satisfied. once burst transfer starts, requests from other channels, even of higher priority, are held pending until burst transfer ends. figure 11.27 shows an example of transfer when etend output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-b it, 2-state access space to external 16- bit, 2-state access space. exdma write address bus exdma write exdma read b rd lhwr , llwr etend bus release bus release last transfer cycle burst transfer exdma read exdma read exdma write figure 11.27 example of normal tr ansfer mode (burst mode) transfer section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 418 of 1340 rej09b0499-0200 (3) block transfer mode in block transfer mode, one block is transferred in response to one transfer request, and after the transfer, the bus is released. figure 11.28 shows an example of transfer when etend output is enabled, and word-size, block transfer mode is performed from external 16-bit, 2-state access sp ace to external 16-bit, 2-state access space. exdma read exdma read exdma write address bus exdma write exdma read exdma read exdma write exdma write b rd lhwr , llwr etend bus release bus release bus release last block transfer cycle block transfer figure 11.28 example of block transfer mode transfer section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 419 of 1340 rej09b0499-0200 (4) edreq pin falling edge activation timing figure 11.29 shows an example of normal transfer mode transfer activated by the edreq pin falling edge. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared, and edreq pin high level sampling for edge sensing is started. if edreq pin high level sampling is completed by the end of the exdma write cycle, acceptance resumes after the en d of the write cycle, and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. request request request clearance period request clearance period minimum 3 cycles minimum 3 cycles write bus release bus release bus release exdma read exdma write exdma read exdma write b edreq address bus exdma control channel [1] [2] [3] [4] [5] [6] [7] acceptance resumed acceptance resumed [1] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in exdmac. [3], [6] exdma cycle starts; edreq pin high level sampling is started at rise of b . [4], [7] when edreq pin high level has been sampled, acceptance is resumed after completion of write cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) idle idle idle transfer source transfer destination transfer destination transfer source read read write figure 11.29 example of normal transfer mode transfer activated by edreq pin falling edge section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 420 of 1340 rej09b0499-0200 figure 11.30 shows an example of block transfer mode transfer activated by the edreq pin falling edge. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared, and edreq pin high level sampling for edge sensing is started. if edreq pin high level sampling is completed by the end of the exdma write cycle, acceptance resumes after the en d of the write cycle, and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. idle idle idle minimum 3 cycles minimum 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus release bus release bus release b edreq address bus exdma control channel [1] [2] [3] [4] [5] [6] [7] acceptance resumed acceptance resumed [1] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in exdmac. [3], [6] exdma cycle starts; edreq pin high level sampling is started at rise of b . [4], [7] when edreq pin high level has been sampled, acceptance is resumed after completion of write cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) one block transfer one block transfer request request request clearance period request clearance period exdma read exdma read exdma write exdma write figure 11.30 example of block transfer mode transfer activated by edreq pin falling edge section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 421 of 1340 rej09b0499-0200 (5) edreq pin low level activation timing figure 11.31 shows an example of normal transfer mode transfer activated by the edreq pin low level. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared. after the end of the write cycle, acceptance resumes and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. idle idle idle minimum 3 cycles minimum 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus release bus release bus release exdma read exdma write exdma read exdma write b edreq address bus exdma control channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in exdmac. [3], [6] exdma cycle starts. [4], [7] acceptance is resumed after completion of write cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) request request duration of transfer request disabled duration of transfer request disabled figure 11.31 example of normal transfer mode transfer activated by edreq pin low level section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 422 of 1340 rej09b0499-0200 figure 11.32 shows an example of block transfer mode transfer activated by the edreq pin low level. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared. after the end of the write cycle, acceptance resumes and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. idle idle idle minimum 3 cycles minimum 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus release bus release bus release exdma read exdma write exdma read exdma write b edreq address bus exdma control channel [1] [2] [3] [4] [5] [6] [7] acceptance resumed acceptance resumed [1] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in exdmac. [3], [6] exdma cycle starts. [4], [7] acceptance is resumed after completion of write cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) one block transfer one block transfer request request request clearance period request clearance period figure 11.32 example of block transfer mode transfer activated by edreq pin low level section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 423 of 1340 rej09b0499-0200 (6) edreq pin low level activation timing with nrd = 1 specified when the nrd bit is set to 1 in edmdr, the accept ance timing of the next transfer request can be delayed one cycle later. figure 11.33 shows an example of normal transfer mode transfer activated by the edreq pin low level with nrd = 1 specified. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared. after the end of the write cycle, acceptance resumes when one cycle of the request clearance period specified by nrd = 1 expires and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. request clearance period transfer source transfer destination transfer destination transfer source bus release bus release bus release exdma read exdma write exdma read exdma write b edreq address bus channel [1] [2] [3] [4] [5] [6] [7] acceptance resumed acceptance resumed [1] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in exdmac. [3], [6] exdma cycle starts. [4], [7] acceptance is resumed after completion of write cycle plus one cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) request request minimum 3 cycles minimum 3 cycles request clearance period extended request clearance period specified by nrd extended request clearance period specified by nrd figure 11.33 example of normal transfer mode transfer activated by edreq pin low level with nrd = 1 specified section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 424 of 1340 rej09b0499-0200 11.5.11 bus cycles in single address mode (1) single address mode (read in cycle steal mode) in single address mode, the bus is released after one byte, word, or longword has been transferred in response to one transfer request. while the bus is released, one or more cpu, dmac, or dtc bus cycles are initiated. figure 11.34 shows an example of transfer when etend output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2- state access space to an external device. bus released bus release bus release exdma read exdma read exdma read exdma read b address bus bus release bus release last transfer cycle rd etend edack figure 11.34 example of single address mode (byte read) transfer section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 425 of 1340 rej09b0499-0200 (2) single address mode (write in cycle steal mode) in single address mode, the bus is released after one byte, word, or longword has been transferred in response to one transfer request. while the bu s is released, one or more cpu, dmac, or dtc bus cycles are initiated. figure 11.35 shows an example of transfer when etend output is enabled, and byte-size, single address mode transfer (wr ite) is performed from an external de vice to external 8-bit, 2-state access space. bus release bus release exdma write b address bus bus release bus release last transfer cycle etend edack exdma write exdma write exdma write llwr bus release figure 11.35 example of single address mode (byte write) transfer section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 426 of 1340 rej09b0499-0200 (3) edreq pin falling edge activation timing figure 11.36 shows an example of single address mode transfer activated by the edreq pin falling edge. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared, and edreq pin high level sampling for edge sensing is started. if edreq pin high level sampling is completed by the end of the exdma single cycle, acceptance resumes after the en d of the single cycle, and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. request idle idle idle request minimum 3 cycles minimum 3 cycles transfer source/ transfer destination single bus release bus release bus release exdma single exdma single b edreq address bus exdma control channel [1] [2] [3] [4] [5] [6] [7] acceptance resumed acceptance resumed [1] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in exdmac. [3], [6] exdma cycle starts; edreq pin high level sampling is started at rise of b . [4], [7] when edreq pin high level has been sampled, acceptance is resumed after completion of write cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) transfer source/ transfer destination single edack request clearance period request clearance period figure 11.36 example of single address mode transfer activated by edreq pin falling edge section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 427 of 1340 rej09b0499-0200 (4) edreq pin low level activation timing figure 11.37 shows an example of single address mode transfer activated by the edreq pin low level. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared. afte r the end of the single cycle, acceptance resumes and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. request idle idle idle request minimum 3 cycles minimum 3 cycles transfer source/ transfer destination single bus release bus release bus release exdma single exdma single b edreq address bus exdma control channel [1] [2] [3] [4] [5] [6] [7] acceptance resumed acceptance resumed [1] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in exdmac. [3], [6] exdma cycle starts. [4], [7] acceptance is resumed after completion of single cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) transfer source/ transfer destination single edack request clearance period request clearance period figure 11.37 example of single address mode transfer activated by edreq pin low level section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 428 of 1340 rej09b0499-0200 (5) edreq pin low level activation timing with nrd = 1 specified when the nrd bit is set to 1 in edmdr, the accept ance timing of the next transfer request can be delayed one cycle later. figure 11.38 shows an example of single address mode transfer activated by the edreq pin low level with nrd = 1 specified. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared. afte r the end of the single cycle, acceptance resumes when one cycle of the request clearance period specified by nrd = 1 expires and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. minimum 3 cycles minimum 3 cycles exdma single exdma single b edreq address bus channel [1] [2] [3] [4] [5] [6] [7] [1] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. [2], [5] request is cleared at end of next bus cycle, and activation is started in exdmac. [3], [6] exdma cycle starts. [4], [7] acceptance is resumed after completion of write cycle plus one cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) bus release bus release acceptance resumed acceptance resumed request request request clearance period request clearance period bus release extended request clearance period specified by nrd extended request clearance period specified by nrd transfer source/ transfer destination transfer source/ transfer destination figure 11.38 example of single address mode transfer activated by edreq pin low level with nrd = 1 specified section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 429 of 1340 rej09b0499-0200 11.5.12 operation timing in each mode this section describes examples of operation timi ng in each mode. the cpu external bus cycle is shown as an example of conflict with another bus master. (1) auto-request/normal transfer mode/cycle steal mode with auto-request (in cycle steal mode), when the dte bit is set to 1 in edmdr, an exdma transfer cycle is started a minimum of three cycles later. if there is a transfer request for another channel of higher priority, the tran sfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. transfer on the original channel is resumed on completion of the higher-priority channel transfer. figures 11.39 and 11.40 show operation timing examples for various conditions. 3 cycles bus release exdma write exdma read exdma write exdma read 0 1 0 b bus cycle cpu operation etend dte bit 3 cycles exdma write exdma read bus release bus release bus release dte 1 write internal bus space cycles 3 cycles last transfer cycle figure 11.39 auto-request/normal transfer mode/cycle steal mode (no conflict/dual address mode) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 430 of 1340 rej09b0499-0200 b edack bus cycle etend cpu cycle exdma single transfer cycle exdma single transfer cycle exdma single transfer cycle external space external space external space external space cpu cycle cpu cycle cpu cycle one bus cycle last transfer cycle cpu operation figure 11.40 auto-request/normal transfer mode/cycle steal mode (cpu cycles/single address mode) (2) auto-request/normal transfer mode/burst mode with auto-request (in burst mode), when the dte bit is set to 1 in edmdr, an exdma transfer cycle is started a minimum of three cycles later. once transfer is st arted, it continues (as a burst) until the transfer end condition is satisfied. transfer requests for other channels are held pending until the end of transfer on the current channel. figures 11.41 to 11.43 show operation timing examples for various conditions. cpu cycle cpu cycle cpu cycle exdmac read exdmac write exdmac read exdmac write exdmac read exdmac write repeated external space external space external space 1 b bus cycle cpu operation etend dte bit last transfer cycle 0 figure 11.41 auto-request/normal transfer mode/burst mode (cpu cycles/dual address mode) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 431 of 1340 rej09b0499-0200 b bus cycle edack of current channel etend of current channel transfer request of another channel edreq last transfer cycle bus release exdmac single transfer cycle exdmac single transfer cycle exdmac single transfer cycle exdmac cycle of another channel bus release figure 11.42 auto-request/normal transfer mode/burst mode (conflict with another cha nnel/single address mode) exdma internal space internal space exdma cpu exdma cpu exdma exdma bus cycle cpu operation external space external space figure 11.43 external bus master cycle steal function (a uto-request/normal transfer mode/burst mode with cpu cycles /single address mode/ebccs = 1) (3) external request/normal tran sfer mode/cycle steal mode in external request mode, an ex dma transfer cycle is started a minimum of three cycles after a transfer request is accepted. the next transfer re quest is accepted after th e end of a one-transfer- unit exdma cycle. for external bus space cpu cycles , at least one bus cycle is generated before the next exdma cycle. if a transfer request is generated for another channel, an exdma cycle for the other channel is generated before the next exdma cycle. the edreq pin sensing timing is different for low level sensing and falling edge sensing. the same applies to transfer request acceptance and transfer start timing. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 432 of 1340 rej09b0499-0200 figures 11.44 to 11.47 show operation timing examples for various conditions. 3 cycles last transfer cycle b edreq edrak bus cycle etend dte bit bus release bus release exdma read exdma write bus release exdma read exdma write 0 1 figure 11.44 external request/normal transfer mode/cycle steal mode (no conflict/dual address mode/low level sensing) one bus cycle last transfer cycle b edreq edrak bus cycle etend edack cpu operation cpu cycle cpu cycle exdmac single transfer cycle cpu cycle cpu cycle exdmac single transfer cycle external space external space external space external space figure 11.45 external request/normal transfer mode/cycle steal mode (cpu cycles/single address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 433 of 1340 rej09b0499-0200 b edreq edrak edack start of transfer by internal edge confirmation start of transfer by internal edge confirmation start of transfer by internal edge confirmation bus release exdmac single transfer cycle exdmac single transfer cycle edreq acceptance internal processing state cpu operation start of high level sensing start of high level sensing start of high level sensing bus release bus release exdmac single transfer cycle figure 11.46 external request/normal transfer mode/cycle steal mode (no conflict/single address mode/falling edge sensing) 3 cycles b edrak of another channel bus release exdmac transfer cycle exdma read exdma write exdma read exdma write transfer cycles of another channel edreq of another channel edreq of current channel edrak of current channel bus cycle figure 11.47 external request/normal transfer mode/cycle steal mode (conflict with another channel/dual address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 434 of 1340 rej09b0499-0200 (4) external request/block tran sfer mode/cycle steal mode in block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. the timing of the start of the next block transfer is the same as in normal transfer mode. if a transfer request is generated for another channel, an exdma cycle for the other channel is generated before the next block transfer. the edreq pin sensing timing is different for low level sensing and falling edge sensing. the same applies to transfer request acceptance and transfer start timing. figures 11.48 to 11.52 show operation timing examples for various conditions. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 435 of 1340 rej09b0499-0200 bus release bus release exdma read exdma write exdma read exdma write exdma read exdma write bus release exdma read exdma write repeated exdma read exdma write repeated last block 3 cycles last transfer cycle end of block b edreq edrak bus cycle etend dte bit 1 0 one block size transfer period figure 11.48 external request/bloc k transfer mode/cycle steal mode (no conflict/dual address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 436 of 1340 rej09b0499-0200 bus release bus release exdma single transfer cycle exdma single transfer cycle exdma single transfer cycle exdma single transfer cycle exdma single transfer cycle bus release last block 3 cycles last transfer cycle end of block one block size transfer period b edreq edrak bus cycle edack etend repeated repeated figure 11.49 external request/bloc k transfer mode/cycle steal mode (no conflict/single address mo de/falling edge sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 437 of 1340 rej09b0499-0200 b edreq edrak bus cycle etend edack external space external space cpu cycle cpu operation cpu cycle exdma single transfer cycle exdma single transfer cycle exdma single transfer cycle exdma single transfer cycle cpu cycle repeated repeated cpu cycle external space external space one block size transfer period one block size transfer period end of block bus cycle last block figure 11.50 external request/bloc k transfer mode/cycle steal mode (cpu cycles/single address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 438 of 1340 rej09b0499-0200 edreq edrak edreq of another channel edrak of another channel bus cycle etend exdma read exdma write exdma read exdma write exdma read exdma write exdma read exdma write bus release exdma cycle of another channel b repeated repeated one block size transfer period one block size transfer period end of block last block figure 11.51 external request/bloc k transfer mode/cycle steal mode (conflict with another channel/dual address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 439 of 1340 rej09b0499-0200 bus cycle last block b edreq edrak bus cycle etend edack external space external space external space external space cpu cycle cpu cycle cpu operation cpu cycle cpu cycle exdma single transfer cycle exdma single transfer cycle exdma single transfer cycle exdma single transfer cycle repeated repeated one block size transfer period one block size transfer period end of block figure 11.52 external request/bloc k transfer mode/cycle steal mode (cpu cycles/ebccs = 1/single address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 440 of 1340 rej09b0499-0200 11.6 operation in cluster transfer mode in cluster transfer mode, transfer is performed by the consecutive read and wr ite operations of 1 to 32 bytes using the cluster buffer. a part of the cluster transfer mode function differs from the ordinary transfer mode functions (normal transfer, repeat transfer, and block transfer modes). 11.6.1 address mode (1) cluster transfer dual address mode (ams = 0) in this mode, both the transfer source and destin ation addresses are specifi ed for transfer in the exdmac internal registers. the transfer source address is set in the source address register (edsar), and the transfer destina tion address is set in the destinat ion address register (eddar). the transfer is processed by pe rforming the consecutive read of a cluster-size from the transfer source address and then the consecu tive write of that data to the tr ansfer destination address. one data access size to 32 bytes can be specified as a cluster size. when one data access size is specified as a cluster size, block transfer mode (dual address mode) is used. the cycles in a cluster-size transfer are indivisi ble: another bus cycle (e xternal access by another bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer. etend pin output can be enabled or disabled by means of the etende bit in edmdr. etend is output for the last write cycle. the edack signal is not output. figure 11.53 shows the data flow in the cluster transfer mode (dual address mode), figure 11.54 shows an example of the timing in cluster transfer dual address mode, and figure 11.55 shows the cluster transfer dual address mode operation. consecutive read consecutive write lsi cluster buffer edsar access read read read read one cluster size one cluster size eddar acces write write write write transfer destination: external device transfer source: external memory figure 11.53 data flow in cluster transfer dual address mode section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 441 of 1340 rej09b0499-0200 exdma write cycle exdma read cycle b eddar eddar eddar edsar edsar edsar address bus rd wr etend figure 11.54 timing in clus ter transfer dual address mode first cluster cluster size: bkszh data accsess size first cluster second cluster second cluster nth cluster nth cluster transfer address b a address t a address t b address b b figure 11.55 cluster transfer dual address mode operation when a word or longword is specified as a data access size but the source or destination address is not at the word or longword boundary, use the appropriate da ta access size for efficient data transfer. in an example shown in figure 11.56, a longword-size transfer is performed with 4-longword specified as a cluster size in the cluster transfer dual address mode from the lower two bits of b'11 to b'10. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 442 of 1340 rej09b0499-0200 the cluster size is decremented regardless of the read or write operation in the consecutive write sequences. cluster buffer transfer source memory transfer destination memory msb h'aa0000 long word long word long word word byte byte h'aa0004 h'aa0008 h'aa000c h'aa0010 lsb 1 2 3 4 2 3 4 1 2 3 4 5 5 6 6 h'bb0000 long word long word long word word word h'bb0004 h'bb0008 h'bb000c h'bb0010 clsbr0 clsbr1 clsbr2 clsbr3 clsbr4 clsbr5 clsbr6 clsbr7 figure 11.56 odd address transfer (2) cluster transfer read address mode (ams = 1, dirs = 0) in this mode, the transfer sour ce address is specified in the so urce address register (edsar) and data is read from the transfer source and transfer red to the cluster buffer. in this mode, the tseie bit in the mode control register (edmdr) must be set to 1. two data access size to 32 bytes can be specifie d as a cluster size for the consecutive read operation. the cycles in a cluster-size transfer are indivisi ble: another bus cycle (e xternal access by another bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer. etend pin output can be enabled or disabled by means of the etende bit in edmdr. etend is output for the last read cycle. when an idle cycle is inserted before the last read cycle, the etend signal is also output in the idle cycle. in this mode, the edacke bit in edmdr must be set to 0 to disable the edack pin output. figure 11.57 shows the data flow in the cluster transfer read address mo de (from the external memory to the cluster buffer), and figure 11.58 show s an example of the timing in cluster transfer read address mode. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 443 of 1340 rej09b0499-0200 cpu lsi transfer source external memory register read address bus edsar access external data bus cluster buffer figure 11.57 data flow in cluster transfer read address mode ( from external memory to cluster buffer) address bus b exdma read cycle rd wr etend edsar edsar edsar high figure 11.58 timing in clust er transfer read address mode (from external memory to cluster buffer) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 444 of 1340 rej09b0499-0200 (3) cluster transfer write address mode (ams = 1, dirs = 1) in this mode, the transfer destination address is specified in the destin ation address register (eddar) and data in the cluster butter is written to the transfer destination. in this mode, the tseie bit in the mode control register (edmdr) must be set to 1. one data access size to 32 bytes can be specifi ed as a cluster size for the consecutive write operation. when one data access size is specified as a cluster size, the cluster transfer write address mode is used. the cycles in a cluster-size transfer are indivisi ble: another bus cycle (e xternal access by another bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer. etend pin output can be enabled or disabled by means of the etende bit in edmdr. etend is output for the last write cycle. when an idle cycle is inserted before the last write cycle, the etend signal is also output in the idle cycle. in this mode, the edacke bit in edmcr must be set to 0 to disable the edack pin output. figure 11.59 shows the data flow in the cluste r transfer write address mode (from the cluster buffer to the external memory), and figure 11.60 shows an example of the timing in cluster transfer write address mode. lsi transfer destination external memory address bus eddar access external data bus cluster buffer when initializing an area by the specified data, write the specified data from cluster buffer 0 into a register sequentially. then, specify the buffer size written in the register as a cluster size and the area to be initialized as dar, and then execute transfer in this mode. figure 11.59 data flow in cluster transfer write address mode (from cluster buffer to external memory) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 445 of 1340 rej09b0499-0200 address bus b exdma write cycle rd wr etend eddar eddar eddar high figure 11.60 timing in clust er transfer write address mode (from cluster buffer to external memory) 11.6.2 setting of address update mode the cluster transfer mode transfer is restricted by the address update mode function. there are the following four address update me thods: increment, decrement, fixed, and offset addition. when the address increment method is specified an d if the specified addre ss is not at the address boundary for the data access size (odd address fo r a word-size transfer, address beyond the 4n boundary for a longword-size transfer), the bus cycle is divided for transfer until the address becomes at the address boundary. when the address matches the bound ary, transfer is processed in units of data access sizes. at the end of transfer , the bus cycle is divide d again to transfer the remaining data in cluster transfer mode. with address decrement, fixed, or offset additi on method, specify the addr ess, that matches the address boundary for the data access size, in edsar and ed dar. when specify ing the address, that is not at the address bound ary for the data access size, in edsar and eddar, fix the lower bit to 0 (lower one bit for a word-size transfer, an d lower two bits for a longword-size transfer) in the address register so that the tr ansfer is processed in units of data access sizes. the block transfer mode must be used for transfer of data by dividing the bus cycle according to the address boundary. when the edtcr value is smaller than the cluster size, a transfer size erro r occurs. in this case, when the tseie bit in edmdr is cleared to 0, the cluster transfer mode is switched to the block transfer mode to process the remaining data. with the decrement, fixed, or offset addition method, transfer is performed without fixing the lower bit to 0. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 446 of 1340 rej09b0499-0200 11.6.3 caution for combining with extended repeat area function as with the block transfer mode, the address register value must be set in cluster transfer mode, so that the end of the cluster size coincides with the end of th e extended repeat area range. when an extended repeat area over flow occurs during a cluster-size transfer in the cluster transfer mode, the extended repeat area overflow interrupt request is held pending until the end of a cluster-size transfer, and tr ansfer overrun will occur. 11.6.4 bus cycles in cluster transfer dual address mode (1) cluster transfer mode in cluster transfer mode, a cluste r-size transfer is processed in response to one transfer request. in an example shown in figure 11.61, the etend pin output is enabled, and word-size transfer is performed with 4-byte cluster size in cluster tran sfer mode from the exte rnal 16-bit, 2-state access space to the external 16 -bit, 2-state access space. exdma read exdma read exdma write exdma write bus release b address bus lhwr , llwr etend rd figure 11.61 example of cl uster transfer mode transfer section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 447 of 1340 rej09b0499-0200 (2) edreq pin falling edge activation timing figure 11.62 shows an example of cluster transfer mode transfer activated by the edreq pin falling edge. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared, and edreq pin high level sampling for edge sensing is started. if edreq pin high level sampling is completed by the end of the last cluster write cycle, acceptance resumes after th e end of the write cycle, and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. bus release one cluster transfer b edreq address bus channel exdma control transfer destination request [1] [1] [2] [5] [3] [6] [4] [7] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. request is cleared at end of next bus cycle, and activation is started in exdmac. exdma cycle starts; edreq pin high level sampling is started at rise of b . when edreq pin high level has been sampled, acceptance is resumed after completion of write cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) [2] [3] [4] [5] [6] [7] request transfer source transfer destination consecutive write minimum 3 cycles request clearance period minimum 3 cycles request clearance period transfer source consecutive read bus release one cluster transfer consecutive write consecutive read figure 11.62 example of cluster transfer mode transfer activated by edreq pin falling edge section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 448 of 1340 rej09b0499-0200 (3) edreq pin low level activation timing figure 11.63 shows an example of cluster transfer mode transfer activated by the edreq pin low level. edreq pin sampling is performed in each cy cle starting at the next rise of b after the end of the dte bit write cycle. when a low level is sampled at the edreq pin while acceptance of a transfer request via the edreq pin is possible, the request is held within the exdmac. then when activation is initiated within the exdmac, the request is cleared. at the end of the last cluster write cycle, acceptance resumes and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. when nrd bit = 0 in edmdr, accep tance resumes at the end of th e last cluster write cycle and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. when nrd bit = 1 in edmdr, accepta nce resumes after one cycle from the end of the last cluster write cycle, and edreq pin low level sampling is performed again. this sequence of operations is repeated until the end of the transfer. bus release bus release one cluster transfer one cluster transfer b edreq address bus channel exdma control [1] [1] [2] [5] [3] [6] [4] [7] acceptance after transfer enabling; edreq pin low level is sampled at rise of b , and request is held. request is cleared at the end of next bus cycle, and activation is started in exdmac. exdma cycle stars. acceptance is resumed after completion of write cycle. (as in [1], edreq pin low level is sampled at rise of b , and request is held.) [2] [3] [4] [5] [6] [7] transfer source transfer source transfer destination transfer destination consecutive read consecutive read consecutive write consecutive write request clearance period request clearance period request request minimum 3 cycles minimum 3 cycles figure 11.63 example of cluster transfer mode transfer activated by edreq pin low level section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 449 of 1340 rej09b0499-0200 11.6.5 operation timing in cluster transfer mode this section describes examples of operation timi ng in cluster transfer mode. the cpu external bus cycle is shown as an example of conflict with another bus master. (1) auto-request/cluster transfer mode/cycle steal mode with auto-request (in cycle steal mode), when the dte bit is set to 1 in edmdr, a continuous exdma transfer cycle is started a minimum of three cycles later. if there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. transfer on the original channel is resumed on completion of the higher-priority channel transfer. the cluster transfer mode (read address mode and write address mode) can not be used with the cluster transfer mode (dual address mode) among more than one channel at the same time. when using the cluster transfer mode (read address mode and write address mode), do not set the cluster transfer mode for another channel. figures 11.64 to 11.66 show operation timing examples for various conditions. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 450 of 1340 rej09b0499-0200 0 1 0 b etend dte bit bus cycle 3 cycles 3 cycles 3 cycles bus release bus release bus release consecutive exdma read consecutive exdma read consecutive exdma read consecutive exdma write consecutive exdma write consecutive exdma write one cluster transfer one cluster transfer last cluster cycle cpu operation dte = 1 write internal bus space cycles figure 11.64 auto-request/cluster transfer mode/cycle steal mode (no confict/dual address mode) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 451 of 1340 rej09b0499-0200 b etend dte bit 0 1 0 bus cycle cpu cycle cpu cycle cpu cycle cpu cycle consecutive exdma read consecutive exdma read consecutive exdma read consecutive exdma write consecutive exdma write consecutive exdma write one cluster transfer one cluster transfer last cluster cycle cpu operation dte = 1 write external space external space external space external space figure 11.65 auto-request/cluster transfer mode/cycle steal mode (cpu cycles/dual address mode) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 452 of 1340 rej09b0499-0200 b bus cycle consecutive exdma read consecutive exdma read consecutive exdma read consecutive exdma write consecutive exdma write consecutive exdma write bus release exdma single transfer cycle of another channel with higher priority one cluster transfer one cluster transfer last cluster transfer transfer request from another channel ( edreq ) figure 11.66 auto-request/cluster transfer mode/cycle steal mode (conflict with another ch annel/dual address mode) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 453 of 1340 rej09b0499-0200 (2) external request/cluster tran sfer mode/cycle steal mode with external requests, a cluster-size transfer is performed continuously. the start timing of the next cluster transfer is the same as for normal transfer mode. if a transfer request is generated for another channel, an exdma cycle for the other channel is generated before the next cluster transfer. the cluster transfer mode (read address mode and write address mode) can not be used with the cluster transfer mode (dual address mode) among more than one channel at the same time. when using the cluster transfer mode (read address mode and write address mode), do not set the cluster transfer mode for another channel. the edreq pin sensing timing is different for low level sensing and falling edge sensing. the same applies to transfer request acceptance and transfer start timing. figures 11.67 to 11.69 show operation timing examples for various conditions. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 454 of 1340 rej09b0499-0200 edreq edrak dte bit etend 0 1 bus cycle b bus release bus release exdma read exdma read exdma read exdma read exdma write exdma write exdma write exdma write one cluster transfer consecutive read consecutive read consecutive write consecutive write 3 cycles last cluster figure 11.67 external request/clus ter transfer mode/cycle steal mode (no conflict/dual address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 455 of 1340 rej09b0499-0200 edreq edrak bus cycle cpu cycle exdma read exdma write one cluster size transfer period cpu cycle cpu cycle cpu cycle exdma read exdma write cpu operation external space external space external space cpu cycle b figure 11.68 external request/clus ter transfer mode/cycle steal mode (cpu cycles/dual address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 456 of 1340 rej09b0499-0200 edreq edrak etend bus cycle cpu cycle consecutive exdma read consecutive exdma write exdma cycle of another channel one cluster size transfer period one cluster size transfer period (last cluster transfer) edreq of another channel edrak of another channel cpu cycle consecutive exdma read consecutive exdma write b figure 11.69 external request/clus ter transfer mode/cycle steal mode (conflict with another channel/dual address mode/low level sensing) section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 457 of 1340 rej09b0499-0200 11.7 ending exdma transfer the operation for ending exdma transfer depe nds on the transfer end conditions. when exdma transfer ends, the dte bit and the act b it in edmdr change from 1 to 0, indicating that exdma transfer has ended. (1) transfer end by edtcr change from 1, 2, or 4 to 0 when the value of edtcr changes from 1, 2, or 4 to 0, exdma transfer ends on the corresponding channel. the dte bit in edmdr is cleared to 0, and the dtif bit in edmdr is set to 1. if the dtie bit in edmdr is set to 1 at this time, a transfer end interrupt request is generated by the transfer counter. exdma transf er does not end if the edtcr value has been 0 since before the start of transfer. (2) transfer end by transf er size error interrupt when the following conditions are satisfied while the tseie bit in edmdr is set to 1, a transfer size error occurs and an exdma transfer is term inated. at this time, the dte bit in edmdr is cleared to 0 and the esif bit in edmdr is set to 1. ? in normal transfer mode and repeat transfer mo de, when the next transfer is requested while a transfer is disabled du e to the edtcr value less than the data access size. ? in block transfer mode, when the next transfer is requested while a transfer is disabled due to the edtcr value less than the block size. ? in cluster transfer mode, when the next transfer is requested while a transfer is disabled due to the edtcr value less than the cluster size. when the tseie bit in edmdr is cleared to 0, da ta is transferred until the edtcr value reaches 0. a transfer size error is not generated. operation in each transfer mode is described below. ? in normal transfer mode and repeat mode, when the edtcr value is less than the data access size, data is transferred in bytes. ? in block transfer mode, when the edtcr value is less than the block size, the specified size of data in edtcr is transferred instead of transferring the block size of data. when the edtcr value is less than the data access si ze, data is transferred in bytes. ? in cluster transfer mode, when the edtcr value is less than the cluster size, the specified size of data in edtcr is transferred instead of transferring the cluster size of data. when the edtcr value is less than the data access size, data is tran sferred in bytes. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 458 of 1340 rej09b0499-0200 (3) transfer end by repeat size end interrupt in repeat transfer mode, when th e rptie bit in edacr is set to 1 and the next transfer request is generated on completion of a repeat-size transfer, a repeat size end interrupt request is generated. the interrupt request terminates exdma transfer, the dte bit in edmdr is cleared to 0, and the esif bit in edmdr is set to 1 at the same time. if the dte bit is set to 1 in this state, transfer resumes. in block transfer or cluster transfer mode, a rep eat size end interrupt request can be generated. in block transfer mode, if the next transfer request is generated at the end of a block-size transfer, a repeat size end interrupt request is generated. in cluster transfer mode, if the next transfer request is generated at the end of a cluster-size transfer, a repeat size end interrupt request is generated. (4) transfer end by extended repeat area overflow interrupt if an address overflows the extended repeat area when an extended repeat area specification has been made and the sarie or darie bit in edacr is set to 1, an extended repeat area overflow interrupt is requested. the interrupt request te rminates exdma transfer , the dte bit in edmdr is cleared to 0, and the esif bit in edmdr is set to 1 at the same time. in dual address mode, if an extended repeat area overflow interrupt is requested during a read cycle, the following write cycle processing is still executed. in block transfer mode, if an ex tended repeat area overflow interrup t is requested during transfer of a block, transfer continues to the end of the block. transfer end by means of an extended repeat area overflow interrupt occurs between block-size transfers. in cluster transfer mode, if an extended repeat area overflow interr upt is requested during transfer of a cluster, transfer continues to the end of the cluster. transfer end by means of an extended repeat area overflow interrupt occurs between cluster-size transfers. (5) transfer end by 0-write to dte bit in edmdr when 0 is written to the dte bit in edmdr by th e cpu, etc., tran sfer ends afte r completion of the exdma cycle in which transfer is in pr ogress or a transfer request was accepted. in block transfer mode, exdma transfer ends after completion of one-block-size transfer in progress. in cluster transfer mode, exdma transfer ends after completion of one-cluster-size transfer in progress. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 459 of 1340 rej09b0499-0200 (6) transfer end by nmi interrupt if an nmi interrupt occurs, the exdmac clears th e dte bit to 0 in all channels and sets the errf bit in edmdr_0 to 1. exdma transfer is aborted when an nmi interrupt is generated during exdma transfer. to perform exdma transf er after an nmi interr upt occurs, clear the errf bit to 0 and then set the dte bit to 1 in all channels. the following explains the transfer end timing in each mode after an nmi interrupt is detected. (a) normal transfer mode and repeat transfer mode in dual address mode, exdma transfer ends at the end of the exdma transfer write cycle in units of transfers. in single address mode, exdma transfer ends at the end of the exdma transfer bus cycle in units of transfers. (b) block transfer mode a block size exdma transfer is aborted. a block size transfer is not co rrectly executed, thus matching between the actual transfer and the transfer request is not guaranteed. in dual address mode, a write cycle corresponding to a read cycle is executed as well as in the normal transfer mode. (c) cluster transfer mode a cluster size exdma transfer is abor ted. if transfer is aborted in a read cycle, the read data is not guaranteed. if transfer is aborted in a write cycle, the data not transferred is not guaranteed. matching between the transfer counter and the addres s register is not guaran teed since the transfer processing cannot be controlled. (7) transfer end by address error if an address error occurs, the ex dmac clears the dte bit to 0 in all channels, and set the errf bit in edmdr_0 to 1. an address error during ex dma transfer forcibly te rminates the transfer. to perform exdma transfer after an address error occurs, clear the errf bit to 0 and then set the dte bit to 1 in each channel. the transfer end timing after address error detect ion is the same as for the one when an nmi interrupt occurs. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 460 of 1340 rej09b0499-0200 (8) transfer end by hardware standby mode and reset input the exdmac is initialized in hardware standby mode and by a reset. exdma transfer is not guaranteed in these cases. 11.8 relationship among exdmac and other bus masters 11.8.1 cpu priority control function over exdmac the exdmac priority level control function can be used for the cpu by setting the cpu priority control register (cpupcr). for details, see section 7.7, cpu priority control function over dtc, dmac, and exdmac. the exdmac priority level can be set independently for each channel by the edmap2 to edmap0 bits in edmdr. the cpu priority level, which corresponds to the priority level of exception handling, can be set by updating the values of the cpup2 to cpup0 bits in cpupcr with the interrupt mask bit values. when the cpupce bit in cpupcr is set to 1 to enable the cpu priority level control and the exdmac priority level is lower than the cpu priority level, the tr ansfer request of the corresponding channel is masked and the channel activation is disabled. when the priority level of another channel is the same or higher than the cpu priority level, the transfer request for another channel is accepted and transfer is enabled re gardless of the priority levels of channels. the cpu priority level control function holds pending the transfer so urce, which masked the transfer request. when the cpu priority level b ecomes lower than the channel priority level by updating one of them, the transfer request is accepte d and transfer starts. the transfer request held pending is cleared by writing 0 to the dte bit. when the cpupce bit is cleared to 0, the lowest cpu priority level is assumed. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 461 of 1340 rej09b0499-0200 11.8.2 bus arbitration with another bus master a cycle of another bus master may (or not) be inserted among consecut ive exdma transfer bus cycles. the exdmac bus mastership can be set so that it is released an d transferred to another bus master. some of the consecutive exdma transfer bus cycles may be indivisible due to the transfer mode specification, may be consecutive bus cycles fo r high-speed access due to the transfer mode specification, or may be consecutive bus cycles because another bus master does not request the bus mastership. these consecutive exdma read and write cycles ar e indivisible: external bus release cycle or external space access cycle by in ternal bus master (cpu, dtc, dmac) does not occur between a read cycle and a write cycle. in cluster transfer mode, the transfer cycle in one cluster is indivisible. in block transfer mode and auto-request burst mode , the exdma transfer bus cycles continues. in this period, the bus priority level of the internal bus master is lower than the exdmac so that the external space access is held pe nding (when ebccs = 0 in the bu s control register 2 (bcr2)). when switching to another channel, or in the auto-request cycle steal mo de, the exdma transfer cycles and internal bus master cy cles are alternatively executed. wh en the internal bus master is not issuing an external space access cycle, th e exdma transfer bus cycles are continuously executed in the allowable range. when the ebccs bit in bcr2 is set to 1 to enable the arbitration function between the exdmac and the internal bus master, the bus mastership is released, except for indi visible bus cycles, and transferred between the exdmac and the internal bus master alternatively. for details, see section 9, bus controller (bsc). section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 462 of 1340 rej09b0499-0200 11.9 interrupt sources exdmac interrupt sources are a tr ansfer end by the transfer coun ter, and an escape end interrupt which is caused by the transfer counter not becoming 0. table 11.7 shows the interrupt sources and their priority order. table 11.7 interrupt sou rces and priority order interrupt interrupt source interrupt priority exdmtend0 transfer end indicated by channel 0 transfer counter exdmtend1 transfer end indicated by channel 1 transfer counter exdmtend2 transfer end indicated by channel 2 transfer counter exdmtend3 transfer end indicated by channel 3 transfer counter exdmeend0 channel 0 transfer size error channel 0 repeat size end channel 0 source address extended repeat area overflow channel 0 destination address extended repeat area overflow exdmeend1 channel 1 transfer size error channel 1 repeat size end channel 1 source address extended repeat area overflow channel 1 destination address extended repeat area overflow exdmeend2 channel 2 transfer size error channel 2 repeat size end channel 2 source address extended repeat area overflow channel 2 destination address extended repeat area overflow exdmeend3 channel 3 transfer size error channel 3 repeat size end channel 3 source address extended repeat area overflow channel 3 destination address extended repeat area overflow high low interrupt source can be enabled or disabled by setting the dtie and esie bits in edmdr for the relevant channels. the dtie bit can be combined with the dtif bit in edmdr to generate an exdmtend interrupt. the esie bit can be combined with the esif bit in edmdr to generate an exdmeend interrupt. interrupt sources in exdmeend are not identified as common interrupts. the interrupt priority order among channels is determined by the interrupt controller as shown in table 11.7. for detains see section 7, interrupt controller. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 463 of 1340 rej09b0499-0200 interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. the transfer counter's transfer end interrupt is enabled or disabled by means of the dtie bit in edmdr, the tran sfer size error interr upt by means of the tseie bit in edmdr, the repeat size end inte rrupt by means of the rptie bit in edacr, the source address extended repeat area overflow interrupt by means of the sarie bit in edacr, and the destination address extended repeat area overflow interrupt by means of the dar ie bit in edacr. the transfer end interrupt by the transfer counter occurs when the dtie bit in edmdr is set to 1, the edtcr becomes 0 by transfer, and then the dtif bit in edmdr is set to 1. interrupts other than the transfer end interrup t by the transfer counter occurs when the corresponding interrupt enable bit is set to 1, the condition for that interrupt is satisfied, and then the esif bit in edmdr is set to 1. the transfer size error interrupt occurs when the edtcr value is smaller than the data access size and a data-access-size transfer for one request cannot be performed for a transfer request. in block transfer mode, the block size is co mpared to the edtcr value to dete rmine a transfer size error. in cluster transfer mode, the cluster size is comp ared to the edtcr value to determine a transfer size error. the repeat size end interrupt occurs when the next transfer request is generated after the end of a repeat size transfer in repeat tran sfer mode. when the repeat area is not set in the address register, transfer can be aborted pe riodically based on the set repeat size value. if the transfer end interrupt by the transfer counter oc curs at the same time, the esif bit is set to 1. the source/destination address ex tended repeat area overflow interr upt occurs when the addresses overflow the specified extended repeat area. if the transfer end inte rrupt by the tr ansfer counter occurs at the same time, the esif bit is set to 1. figure 11.70 shows the block diagram of various interrupts and their interrupt flags. the transfer end interrupt can be cleared eith er by clearing the dtif or esif bit to 0 in edmdr within the interrupt handling routine, or by re-setting the ad dress registers and then setting the dte bit to 1 in edmdr to perform transfer c ontinuation processing. an exampl e of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 11.71. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 464 of 1340 rej09b0499-0200 tseie bit activation source occurred in the transfer size error state rptie bit activation source occurred after bksz changed from 1 to 0 sarie bit source address extended repeat area overflow occurred darie bit destination address extended repeat area overflow occurred dtie bit dtif bit transfer end interrupt condition to set dtif bit to 1: dtcr is set to 0 and transfer ends. esie bit esif bit condition to set esif bit to 1 transfer escape end interrupt figure 11.70 interrupt s and interrupt sources [1] [2] [3] [4] [5] [6] [7] transfer end interrupt of exception handling routine transfer continuation processing change register settings write 1 to dte bit end of interrupt handling routine (rte instruction execution) end of transfer restart processing transfer restart after end of interrupt handling routine clear dtif or esif bit to 0 end of interrupt handling routine [1] write set values to the registers (transfer counter, address registers, etc.) [2] write 1 to the dte bit in edmdr to restart exdma operation. when 1 is written to the dte bit, the dtif or esif bit in edmdr is automatically cleared to 0 and the interrupt source is cleared. [3] the interrupt handling routine is ended with an rte instruction, etc. [4] write 0 to the dtif or esif bit in edmdr by first reading 1 from it. [5] after the interrupt handling routine is ended with an rte instruction, etc., interrupt masking is cleared. [6] write set values to the registers (transfer counter, address registers, etc.). [7] write 1 to the dte bit in edmdr to restart exdma operation. change register settings write 1 to dte bit end of transfer restart processing figure 11.71 procedure for clearing transfer end interr upt and restarting transfer section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 465 of 1340 rej09b0499-0200 11.10 usage notes (1) exdmac register access during operation except for clearing the dte bit to 0 in edmdr, settings should not be changed for a channel in operation (including the transfer standby state). transfer must be disabled before changing a setting for an operational channel. (2) module stop state the exdmac operation can be enabled or disabled by the module stop control register. the initial value is "enabled". when the mstpa14 bit is set to 1 in mstpcra, the exdmac clock stops and the exdmac enters the module stop state. however, 1 cannot be written to the mstpa14 bit when any of the exdmac's channels is enabled for transfer, or when an interrupt is being requested. before setting the mstpa14 bit, first clear the dte bit in edmdr to 0, then clear the dtif or dtie bit in edmdr to 0. when the exdmac clock stops, exdmac register s can no longer be accessed. the following exdmac register settings remain valid in the module stop state, and so should be disabled, if necessary, before making the module stop transition. ? etende = 1 in edmdr ( etend pin enable) ? edrake = 1 in edmdr ( edrak pin enable) ? edacke = 1 in edmdr ( edack pin enable) (3) edreq pin falling edge activation falling edge sensing on the edreq pin is performed in synchronization with exdmac internal operations, as indicated below. 1. activation request standby state: waits for low level sensing on edreq pin, then goes to [2]. 2. transfer standby state: waits for exdmac data transfer to become possible, then goes to [3]. 3. activation request disabled state: waits for high level sensing on edreq pin, then goes to [1]. after exdmac transfer is enabled, the exdmac goes to state [1], so low level sensing is used for the initial activation after transfer is enabled. section 11 exdma controller (exdmac) rev. 2.00 oct. 20, 2009 page 466 of 1340 rej09b0499-0200 (4) activation source acceptance at the start of activation source acceptance, low leve l sensing is used for both falling edge sensing and low level sensing on the c therefore, a request is accepted in the case of a low level at the edreq pin that occurs before execution of the edmdr write for setting the transfer-enabled state. at exdmac activation, low level on the edreq pin must not remain at the end of the previous transfer. (5) conflict in cluster transfer in cluster transfer mode, the same cluster buffer is used for all channels. when more than one cluster transfer conflicts, the cluster buffer register holds the value of the last cluster transfer. when the transfer between the tr ansfer source/destinat ion and the cluster buffer conflicts with another cluster transfer, the transferred data in the cluster buffer may be overwritten by another channel cluster transfer. th erefore, in the cluster transfer mode (single address mode), do not set the cluster transfer mode for any other channels. (6) cluster transfer mode and endian in cluster transfer mode, only a tr ansfer to the areas in the big en dian format is supported. when cluster transfer mode is specified, do not specif y the areas in the little endian format for edsar and eddar. for details on the endian, see section 9, bus controller (bsc). section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 467 of 1340 rej09b0499-0200 section 12 data transfer controller (dtc) this lsi includes a data transfer controller (dtc). the dtc can be activated to transfer data by an interrupt request. 12.1 features ? transfer possible over any number of channels: multiple data transfer enabled for one activation source (chain transfer) chain transfer specifiable after data transfer (when the counter is 0) ? three transfer modes normal/repeat/block tran sfer modes selectable transfer source and destination addresses ca n be selected from increment/decrement/fixed ? short address mode or full address mode selectable ? short address mode transfer information is located on a 3-longword boundary the transfer source and destination addresses can be specified by 24 bits to select a 16- mbyte address space directly ? full address mode transfer information is located on a 4-longword boundary the transfer source and destination addresses can be specified by 32 bits to select a 4- gbyte address space directly ? size of data for data transfer can be specified as byte, word, or longword the bus cycle is divided if an odd address is specified for a word or longword transfer. the bus cycle is divided if address 4n + 2 is specified for a longword transfer. ? a cpu interrupt can be requested for the interrupt that activated the dtc a cpu interrupt can be requested af ter one data transfer completion a cpu interrupt can be requested after the specified data transfer completion ? read skip of th e transfer information specifiable ? writeback skip executed for the fixed tr ansfer source and destination addresses ? module stop state specifiable section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 468 of 1340 rej09b0499-0200 figure 12.1 shows a block diagram of the dtc. th e dtc transfer informati on can be allocated to the data area*. when the transf er information is allocated to the on-chip ram, a 32-bit bus connects the dtc to the on-chip ram, enabling 32-bit/1-state reading and writing of the dtc transfer information. note: * when the transfer inform ation is stored in the on-chip ram, the rame bit in syscr must be set to 1. bus interface bus controller dtccr interrupt controller ack req dtcvbr dtc dtc internal bus peripheral bus internal bus (32 bits) external bus cpu interrupt request interrupt source clear request 8 register control activation control interrupt control on-chip rom on-chip ram mra mrb sar dar cra crb on-chip peripheral module external memory external device (memory mapped) dtc activation request vector number mra, mrb: sar: dar: cra, crb: dtcera to dtcerf: dtccr: dtcvbr: dtc mode registers a, b dtc source address register dtc destination address register dtc transfer count registers a, b dtc enable registers a to f dtc control register dtc vector base register [legend] dtcera to dtcerf figure 12.1 block diagram of dtc section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 469 of 1340 rej09b0499-0200 12.2 register descriptions dtc has the following registers. ? dtc mode register a (mra) ? dtc mode register b (mrb) ? dtc source address register (sar) ? dtc destination address register (dar) ? dtc transfer count register a (cra) ? dtc transfer count register b (crb) these six registers mra, mrb, sar, dar, cra , and crb cannot be directly accessed by the cpu. the contents of these registers are stored in the data area as transf er information. when a dtc activation request occurs, the dtc reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer informati on, and transfers data. after the data transfer, it write s a set of updated transfer info rmation back to the data area. ? dtc enable registers a to f (dtcera to dtcerf) ? dtc control register (dtccr) ? dtc vector base register (dtcvbr) section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 470 of 1340 rej09b0499-0200 12.2.1 dtc mode register a (mra) mra selects dtc operating mode. mra cann ot be accessed directly by the cpu. bit bit name initial value r/w 7 md1 undefined ? 6 md0 undefined ? 5 sz1 undefined ? 4 sz0 undefined ? 3 sm1 undefined ? 2 sm0 undefined ? 1 ? undefined ? 0 ? undefined ? bit bit name initial value r/w description 7 6 md1 md0 undefined undefined ? ? dtc mode 1 and 0 specify dtc transfer mode. 00: normal mode 01: repeat mode 10: block transfer mode 11: setting prohibited 5 4 sz1 sz0 undefined undefined ? ? dtc data transfer size 1 and 0 specify the size of data to be transferred. 00: byte-size transfer 01: word-size transfer 10: longword-size transfer 11: setting prohibited 3 2 sm1 sm0 undefined undefined ? ? source address mode 1 and 0 specify an sar operation after a data transfer. 0x: sar is fixed (sar writeback is skipped) 10: sar is incremented after a transfer (by +1 when sz1 and sz0 = b'00; by +2 when sz1 and sz0 = b'01; by +4 when sz1 and sz0 = b'10) 11: sar is decremented after a transfer (by ?1 when sz1 and sz0 = b'00; by ?2 when sz1 and sz0 = b'01; by ?4 when sz1 and sz0 = b'10) 1, 0 ? undefined ? reserved the write value should always be 0. [legend] x: don't care section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 471 of 1340 rej09b0499-0200 12.2.2 dtc mode register b (mrb) mrb selects dtc operating mode. mrb cann ot be accessed directly by the cpu. bit bit name initial value r/w 7 chne undefined ? 6 chns undefined ? 5 disel undefined ? 4 dts undefined ? 3 dm1 undefined ? 2 dm0 undefined ? 1 ? undefined ? 0 ? undefined ? bit bit name initial value r/w description 7 chne undefined ? dtc chain transfer enable specifies the chain transfer . for details, see section 12.5.7, chain transfer. the chain transfer condition is selected by the chns bit. 0: disables the chain transfer 1: enables the chain transfer 6 chns undefined ? dtc chain transfer select specifies the chain transfer condition. if the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or dtcer is not cleared. 0: chain transfer every time 1: chain transfer only when transfer counter = 0 5 disel undefined ? dtc interrupt select when this bit is set to 1, a cpu interrupt request is generated every time after a data transfer ends. when this bit is set to 0, a cpu interrupt request is only generated when the specifi ed number of data transfer ends. 4 dts undefined ? dtc transfer mode select specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: specifies the destination as repeat or block area 1: specifies the source as repeat or block area section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 472 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 2 dm1 dm0 undefined undefined ? ? destination address mode 1 and 0 specify a dar operation after a data transfer. 0x: dar is fixed (dar writeback is skipped) 10: dar is incremented after a transfer (by +1 when sz1 and sz0 = b'00; by +2 when sz1 and sz0 = b'01; by +4 when sz1 and sz0 = b'10) 11: sar is decremented after a transfer (by ?1 when sz1 and sz0 = b'00; by ?2 when sz1 and sz0 = b'01; by ?4 when sz1 and sz0 = b'10) 1, 0 ? undefined ? reserved the write value should always be 0. [legend] x: don't care 12.2.3 dtc source address register (sar) sar is a 32-bit register that designates the source address of data to be transferred by the dtc. in full address mode, 32 bits of sar are valid. in short address mode, the lower 24 bits of sar is valid and bits 31 to 24 are ignored. at this time, the upper eight bits are fi lled with the value of bit 23. if a word or longword access is performed while an odd address is speci fied in sar or if a longword access is performed while address 4n + 2 is specified in sar, th e bus cycle is divided into multiple cycles to transfer data. for de tails, see section 12.5.1, bus cycle division. sar cannot be accessed dire ctly from the cpu. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 473 of 1340 rej09b0499-0200 12.2.4 dtc destination address register (dar) dar is a 32-bit register that designates the destination address of data to be transferred by the dtc. in full address mode, 32 bits of dar are valid. in short address mode, the lower 24 bits of dar is valid and bits 31 to 24 are ignored. at this time, the upper eight bits are fi lled with the value of bit 23. if a word or longword access is performed while an odd address is speci fied in dar or if a longword access is performed while address 4n + 2 is specified in dar, th e bus cycle is divided into multiple cycles to transfer data. for deta ils, see section 12.5.1, bus cycle division. dar cannot be accessed directly from the cpu. 12.2.5 dtc transfer count register a (cra) cra is a 16-bit register that desi gnates the number of times data is to be transferred by the dtc. in normal transfer mode, cra functions as a 16-bit transfer counter (1 to 65,536). it is decremented by 1 every time data is transferred, and bit dtcen (n = 15 to 0) corresponding to the activation source is cleared and th en an interrupt is requested to the cpu when the count reaches h'0000. the transfer count is 1 when cra = h'0001, 65,535 when cra = h'ffff, and 65,536 when cra = h'0000. in repeat transfer mode, cra is divided into two parts: the upper eight bits (crah) and the lower eight bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent to cral when the count reaches h'00. the transfer count is 1 when crah = cral = h'01, 255 when crah = cral = h'ff, and 256 when crah = cral = h'00. in block transfer mode, cra is divided into two parts: the upper eight bits (crah) and the lower eight bits (cral). crah holds the block size while cral functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). cral is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of crah are sent to cral when the count reaches h'00. the block si ze is 1 byte (word or longwor d) when crah = cral =h'01, 255 bytes (words or longwords) when crah = cral = h'ff, and 256 bytes (words or longwords) when crah = cral =h'00. cra cannot be accessed directly from the cpu. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 474 of 1340 rej09b0499-0200 12.2.6 dtc transfer count register b (crb) crb is a 16-bit register that designates the number of times data is to be tr ansferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and bit dtcen (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the cpu when the count reaches h'0000. the transfer count is 1 when crb = h'0001, 65,535 when crb = h'ffff, and 65,536 when crb = h'0000. crb is not available in normal and repeat modes and cannot be accessed directly by the cpu. 12.2.7 dtc enable registers a to f (dtcera to dtcerf) dtcer, which is comprised of eight registers, dt cera to dtcerf, is a register that specifies dtc activation interrupt sources. the corresponden ce between interrupt sources and dtce bits is shown in table 12.1. use bit manipulation instructions such as bset and bclr to read or write a dtce bit. if all interrupts are masked, multiple ac tivation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. bit bit name initial value r/w 15 dtce15 0 r/w 14 dtce14 0 r/w 13 dtce13 0 r/w 12 dtce12 0 r/w 11 dtce11 0 r/w 10 dtce10 0 r/w 9 dtce9 0 r/w 8 dtce8 0 r/w bit bit name initial value r/w 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w 0 dtce0 0 r/w section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 475 of 1340 rej09b0499-0200 bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dtce15 dtce14 dtce13 dtce12 dtce11 dtce10 dtce9 dtce8 dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dtc activation enable 15 to 0 setting this bit to 1 specifies a relevant interrupt source to a dtc activation source. [clearing conditions] ? when writing 0 to the bit to be cleared after reading 1 ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended these bits are not cleared when the disel bit is 0 and the specified number of transfers have not ended 12.2.8 dtc control register (dtccr) dtccr specifies transfer information read skip. bit bit name initial value r/w note: * only 0 can be written to clear the flag. 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 rrs 0 r/w 3 rchne 0 r/w 2 ? 0 r 1 ? 0 r 0 err 0 r/(w) * bit bit name initial value r/w description 7 to 5 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 476 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 rrs 0 r/w dtc transfer information read skip enable controls the vector address read and transfer information read. a dtc vector number is always compared with the vector number for the previous activation. if the vector numbers match and this bit is set to 1, the dtc data tr ansfer is started without reading a vector address and transfer information. if the previous dtc activation is a chain transfer, the vector address read and transfer information read are always performed. 0: transfer read skip is not performed. 1: transfer read skip is performed when the vector numbers match. 3 rchne 0 r/w chain transfer enable after dtc repeat transfer enables/disables the chain transfer while transfer counter (cral) is 0 in repeat transfer mode. in repeat transfer mode, the crah value is written to cral when cral is 0. accordingly, chain transfer may not occur when cral is 0. if this bit is set to 1, the chain transfer is enabled when crah is written to cral. 0: disables the chain transfer after repeat transfer 1: enables the chain transf er after repeat transfer 2, 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 err 0 r/(w) * transfer stop flag indicates that an address error or an nmi interrupt occurs. if an address error or an nmi interrupt occurs, the dtc stops. 0: no interrupt occurs 1: an interrupt occurs [clearing condition] ? when writing 0 after reading 1 note: * only 0 can be written to clear this flag. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 477 of 1340 rej09b0499-0200 12.2.9 dtc vector base register (dtcvbr) dtcvbr is a 32-bit register that specifies the base address for v ector table address calculation. bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. the initial value of dtcvbr is h'00000000. bit bit name initial value r/w 31 0 r 30 0 r 29 0 r 28 0 r 27 0 r/w 26 0 r/w 25 0 r/w 24 0 r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 18 0 r/w 17 0 r/w 16 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r 12.3 activation sources the dtc is activated by an interrupt request. th e interrupt source is sel ected by dtcer. a dtc activation source can be selected by setting the corresponding bit in dtcer; the cpu interrupt source can be selected by clearing the corresponding bit in dtcer. at the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding dtce r bit is cleared. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 478 of 1340 rej09b0499-0200 12.4 location of transfer informat ion and dtc vector table locate the transfer information in the data area. the start address of transfer information should be located at the address that is a multiple of four (4n). otherwise, the lower two bits are ignored during access ([1:0] = b'00.) tran sfer information can be located in either short address mode (three longwords) or full address mode (four longwords). the dtcmd bit in syscr specifies either short address mode (dtcmd = 1) or fu ll address mode (dtcmd = 0). for details, see section 3.2.2, system control register (syscr). transfer information located in the data area is shown in figure 12.2 the dtc reads the start address of transfer informatio n from the vector ta ble according to the activation source, and then reads the transfer info rmation from the start addr ess. figure 12.3 shows correspondences between th e dtc vector address and transfer information. start address 4 bytes 1 0 mra sar mrb dar cra crb mra sar mrb dar cra crb mra mrb reserved (0 write) mra mrb reserved (0 write) sar dar cra crb cra crb sar dar 3 2 transfer information in short address mode chain transfer transfer information for one transfer (3 longwords) transfer information for the 2nd transfer in chain transfer (3 longwords) lower addresses lower addresses transfer information in full address mode transfer information for one transfer (4 longwords) transfer information for the 2nd transfer in chain transfer (4 longwords) start address 4 bytes 1 03 2 chain transfer figure 12.2 transfer in formation on data area section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 479 of 1340 rej09b0499-0200 transfer information (1) start address transfer information (2) start address transfer information (n) start address vector table upper: dtcvbr lower: h'400 + vector number 4 dtc vector address +4 +4n transfer information (1) 4 bytes transfer information (2) transfer information (n) : : : : : : figure 12.3 correspondence between dtc vector address and transfer information section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 480 of 1340 rej09b0499-0200 table 12.1 shows correspondence between the dtc activation source and vector address. table 12.1 interrupt sou rces, dtc vector addresses, and corresponding dtces origin of activation source activation source vector number dtc vector address offset dtce * priority irq0 64 h'500 dtcea15 irq1 65 h'504 dtcea14 irq2 66 h'508 dtcea13 irq3 67 h'50c dtcea12 irq4 68 h'510 dtcea11 irq5 69 h'514 dtcea10 irq6 70 h'518 dtcea9 irq7 71 h'51c dtcea8 irq8 72 h'520 dtcea7 irq9 73 h'524 dtcea6 irq10 74 h'528 dtcea5 external pin irq11 75 h'52c dtcea4 a/d_0 adi0 (a/d_0 conversion end) 86 h'558 dtceb15 tgi0a 88 h'560 dtceb13 tgi0b 89 h'564 dtceb12 tgi0c 90 h'568 dtceb11 tpu_0 tgi0d 91 h'56c dtceb10 tgi1a 93 h'574 dtceb9 tpu_1 tgi1b 94 h'578 dtceb8 tgi2a 97 h'584 dtceb7 high tpu_2 tgi2b 98 h'588 dtceb6 low section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 481 of 1340 rej09b0499-0200 origin of activation source activation source vector number dtc vector address offset dtce * priority tgi3a 101 h'594 dtceb5 high tgi3b 102 h'598 dtceb4 tgi3c 103 h'59c dtceb3 tpu_3 tgi3d 104 h'5a0 dtceb2 tgi4a 106 h'5a8 dtceb1 tpu_4 tgi4b 107 h'5ac dtceb0 tgi5a 110 h'5b8 dtcec15 tpu_5 tgi5b 111 h'5bc dtcec14 cmi0a 116 h'5d0 dtcec13 tmr_0 cmi0b 117 h'5d4 dtcec12 cmi1a 119 h'5dc dtcec11 tmr_1 cmi1b 120 h'5e0 dtcec10 cmi2a 122 h'5e8 dtcec9 tmr_2 cmi2b 123 h'5ec dtcec8 cmi3a 125 h'5f4 dtcec7 tmr_3 cmi3b 126 h'5f8 dtcec6 dmtend0 128 h'600 dtcec5 dmtend1 129 h'604 dtcec4 dmtend2 130 h'608 dtcec3 dmac dmtend3 131 h'60c dtcec2 exdmtend0 132 h'610 dtcec1 exdmtend1 133 h'614 dtcec0 exdmtend2 134 h'618 dtcec15 exdmac exdmtend3 135 h'61c dtcec14 dmeend0 136 h'620 dtced13 dmeend1 137 h'624 dtced12 dmeend2 138 h'628 dtced11 dmac dmeend3 139 h'62c dtced10 exdmeend0 140 h'630 dtcecd9 exdmeend1 141 h'634 dtcecd8 exdmeend2 142 h'638 dtced7 exdmac exdmeend3 143 h'63c dtced6 low section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 482 of 1340 rej09b0499-0200 origin of activation source activation source vector number dtc vector address offset dtce * priority rxi0 145 h'644 dtced5 sci_0 txi0 146 h'648 dtced4 rxi1 149 h'654 dtced3 sci_1 txi1 150 h'658 dtced2 rxi2 153 h'664 dtced1 sci_2 txi2 154 h'668 dtced0 rxi4 161 h'684 dtcee13 sci_4 txi4 162 h'688 dtcee12 tgi6a 164 h'690 dtcee11 tgi6b 165 h'694 dtcee10 tgi6c 166 h'698 dtcee9 tpu_6 tgi6d 167 h'69c dtcee8 tgi7a 169 h'6a4 dtcee7 tpu_7 tgi7b 170 h'6a8 dtcee6 tgi8a 173 h'6b4 dtcee5 tpu_8 tgi8b 174 h'6b8 dtcee4 tgi9a 177 h'6c4 dtcee3 tgi9b 178 h'6c8 dtcee2 tgi9c 179 h'6cc dtcee1 tpu_9 tgi9d 180 h'6d0 dtcee0 tgi10a 182 h'6d8 dtcef15 tgi10b 183 h'6dc dtcef14 tpu_10 tgi10v 186 h'6e8 dtcef11 tgi11a 188 h' 6f0 dtcef10 high tpu_11 tgi11b 189 h'6f4 dtcef9 low note: * the dtce bits with no corresponding interru pt are reserved, and the write value should always be 0. to leave software standby mode or all-module-clock-stop mode with an interrupt, write 0 to the corresponding dtce bit. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 483 of 1340 rej09b0499-0200 12.5 operation the dtc stores transfer information in the data area. when activated, the dtc reads transfer information that is stored in the data area an d transfers data on the basis of that transfer information. after the data transfer, it writes upda ted transfer information back to the data area. since transfer information is in the data area, it is possible to transfer data over any required number of channels. there are three transfer modes: normal, repeat, and block. the dtc specifies the source ad dress and destination address in sar and dar, respectively. after a transfer, sar and dar are incremented, decremented, or fixed independently. table 12.2 shows the dtc transfer modes. table 12.2 dtc transfer modes transfer mode size of data transferred at one transfer request memory address increment or decrement transfer count normal 1 byte/word/longword increment ed/decremented by 1, 2, or 4, or fixed 1 to 65536 repeat * 1 1 byte/word/longword incremented /decremented by 1, 2, or 4, or fixed 1 to 256 * 3 block * 2 block size specified by crah (1 to 256 bytes/words/longwords) incremented/decremented by 1, 2, or 4, or fixed 1 to 65536 notes: 1. either source or destinat ion is specified to repeat area. 2. either source or destinati on is specified to block area. 3. after transfer of the specified transfer co unt, initial state is recovered to continue the operation. setting the chne bit in mrb to 1 makes it possi ble to perform a number of transfers with a single activation (chain transfer). setting the chns bit in mrb to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. figure 12.4 shows a flowchart of dtc operation, and table 12.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 484 of 1340 rej09b0499-0200 start match & rrs = 1 not match | rrs = 0 next transfer read transfer information transfer data update transfer information update the start address of transfer information write transfer information chne = 1 transfer counter = 0 or disel = 1 clear activation source flag end chns = 0 transfer counter = 0 disel = 1 clear dtcer/request an interrupt to the cpu no no no no no yes yes yes yes yes vector number comparison read dtc vector figure 12.4 flowchart of dtc operation section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 485 of 1340 rej09b0499-0200 table 12.3 chain transfer conditions 1st transfer 2nd transfer chne chns disel transfer counter * 1 chne chns disel transfer counter * 1 dtc transfer 0 ? 0 not 0 ? ? ? ? ends at 1st transfer 0 ? 0 0 * 2 ? ? ? ? ends at 1st transfer 0 ? 1 ? ? ? ? interrupt request to cpu 0 ? 0 not 0 ends at 2nd transfer 0 ? 0 0 * 2 ends at 2nd transfer 1 0 ? ? 0 ? 1 ? interrupt request to cpu 1 1 0 not 0 ? ? ? ends at 1st transfer 0 ? 0 not 0 ends at 2nd transfer 0 ? 0 0 * 2 ends at 2nd transfer 1 1 ? 0 * 2 0 ? 1 interrupt request to cpu 1 1 1 not 0 ? ? ? ? ends at 1st transfer interrupt request to cpu notes: 1. cra in normal mode transfer, cral in repeat transfer mode, or crb in block transfer mode 2. when the contents of the crah is wr itten to the cral in repeat transfer mode 12.5.1 bus cycle division when the transfer data size is wo rd and the sar and dar values ar e not a multiple of 2, the bus cycle is divided and the transfer data is read from or written to in bytes. table 12.4 shows the relationship among, sar, dar, transfer data size, bus cycle divisions, and access data size. figure 12.5 shows th e bus cycle division example. table 12.4 number of bus cy cle divisions and access size specified data size sar and dar values byte (b) word (w) longword (lw) address 4n 1 (b) 1 (w) 1 (lw) address 2n + 1 1 (b) 2 (b-b) 3 (b-w-b) address 4n + 2 1 (b) 1 (w) 2 (w-w) section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 486 of 1340 rej09b0499-0200 clock address dtc activation request dtc request bbw r w clock address dtc activation request dtc request ww l r w clock address dtc activation request dtc request bbl w r w [example 1: when an odd address and even address are specified in sar and dar, respectively, and when the data size of transfe r is specified as word] [example 2: when an odd address and address 4n are specified in sar and dar, respectively, and when the data size of transfer is specified as longword] [example 3: when address 4n + 2 and address 4n are specified in sar and dar, respectively, and when the data size of transfer is specified as longword] vector read transfer information read data transfer transfer information write vector read transfer information read data transfer transfer information write vector read transfer information read data transfer transfer information write figure 12.5 bus cycle division example section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 487 of 1340 rej09b0499-0200 12.5.2 transfer information read skip function by setting the rrs bit of dtccr, the vector addr ess read and transfer information read can be skipped. the current dtc vector number is always compared with the vector number of previous activation. if the vector number s match when rrs = 1, a dtc data transfer is performed without reading the vector address and tran sfer information. if the previous activation is a chain transfer, the vector address read and transf er information read are always performed. figure 12.6 shows the transfer information read skip timing. to modify the vector table and tr ansfer information, temporarily cl ear the rrs bit to 0, modify the vector table and transfer information, and then set the rrs bit to 1 again. when the rrs bit is cleared to 0, the stored vector number is dele ted, and the updated vect or table and transfer information are read at the next activation. clock vector read note: transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while rrs = 1. (1) (2) transfer information read data transfer transfer information write address dtc activation request dtc request transfer information read skip r w data transfer transfer information write r w figure 12.6 transfer info rmation read skip timing section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 488 of 1340 rej09b0499-0200 12.5.3 transfer information writeback skip function by specifying bit sm1 in mra and bit dm1 in mrb to the fixed address mode, a part of transfer information will not be written back. this function is performed regardless of short or full address mode. table 12.5 shows the transfer information writeback skip condition and writeback skipped registers. note that the cra and crb are always written back regardless of the short or full address mode. in addition in fu ll address mode, the writeback of the mra and mrb are always skipped. table 12.5 transfer information writebac k skip condition and writeback skipped registers sm1 dm1 sar dar 0 0 skipped skipped 0 1 skipped written back 1 0 written back skipped 1 1 written back written back 12.5.4 normal transfer mode in normal transfer mode, one operation transfers one byte, one word, or one longword of data. from 1 to 65,536 transfers can be specified. the transfer source and destination addresses can be specified as incremented, decremented, or fixed. when the specified number of transfers ends, an interrupt can be requested to the cpu. table 12.6 lists the register function in normal transfer mode. figure 12.7 shows the memory map in normal transfer mode. table 12.6 register function in normal transfer mode register function written back value sar source address incremented/decremented/fixed * dar destination address incremented/decremented/fixed * cra transfer count a cra ? 1 crb transfer count b not updated note: * transfer information writeback is skipped. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 489 of 1340 rej09b0499-0200 sar transfer source data area dar transfer transfer destination data area figure 12.7 memory map in normal transfer mode 12.5.5 repeat transfer mode in repeat transfer mode, one operation transfers one byte, one word, or one longword of data. by the dts bit in mrb, either the source or destina tion can be specified as a repeat area. from 1 to 256 transfers can be specified. when the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. the other address register is then increm ented, decremented, or left fixed. in repeat transfer mode, the transfer counter (cral) is updated to the value specified in crah when cral becomes h'00. thus the transfer counter value does not reach h'00, and therefore a cpu interrupt cannot be requested when disel = 0. table 12.7 lists the register function in repeat transfer mode. figure 12.8 shows the memory map in repeat transfer mode. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 490 of 1340 rej09b0499-0200 table 12.7 register function in repeat transfer mode written back value register function cral is not 1 cral is 1 sar source address incremented/decremented/fixed * dts =0: incremented/ decremented/fixed * dts = 1: sar initial value dar destination address incremented/decremented/fixed * dts = 0: dar initial value dts =1: incremented/ decremented/fixed * crah transfer count storage crah crah cral transfer count a cral ? 1 crah crb transfer count b not updated not updated note: * transfer information writeback is skipped. sar transfer source data area (specified as repeat area) dar transfer transfer destination data area figure 12.8 memory map in repeat transfer mode (when transfer source is specified as repeat area) section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 491 of 1340 rej09b0499-0200 12.5.6 block transfer mode in block transfer mode, one operat ion transfers one block of data. either the transfer source or the transfer destination is de signated as a block area by the dts bit in mrb. the block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). when the transfer of one block ends, the block size counter (cral) and address register (sar when dts = 1 or dar when dts = 0) specified as the block area is restored to the initial state. the other address register is then incremented, decremented, or left fixed. from 1 to 65,536 transfer s can be specified. when the specified number of transfers ends, an interrupt is requested to the cpu. table 12.8 lists the register function in block transfer mode. figure 12.9 shows the memory map in block transfer mode. table 12.8 register function in block transfer mode register function written back value sar source address dts =0: incremented/decremented/fixed * dts = 1: sar initial value dar destination address dts = 0: dar initial value dts =1: incremented/decremented/fixed * crah block size storage crah cral block size counter crah crb block transfer counter crb ? 1 note: * transfer information writeback is skipped. transfer source data area transfer destination data area (specified as block area) block area dar sar : : transfer 1st block nth block figure 12.9 memory map in block transfer mode (when transfer destination is specified as block area) section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 492 of 1340 rej09b0499-0200 12.5.7 chain transfer setting the chne bit in mrb to 1 enables a number of data transfers to be performed consecutively in response to a si ngle transfer request. setting the chne and chns bits in mrb set to 1 enables a chain transfer only when the tr ansfer counter reaches 0. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 12.10 shows the chain transfer operation. in the case of transfer with chne set to 1, an in terrupt request to the cpu is not generated at the end of the specified number of transfers or by se tting the disel bit to 1, and the interrupt source flag for the activation source and dtcer are not affected. in repeat transfer mode, setting the rchne bit in dtccr and the chne and chns bits in mrb to 1 enables a chain transfer af ter transfer with transfer c ounter = 1 has been completed. transfer information chne = 1 transfer information chne = 0 transfer information stored in user area data area transfer source data (1) transfer destination data (1) transfer source data (2) transfer destination data (2) transfer information start address vector table dtc vector address figure 12.10 operation of chain transfer section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 493 of 1340 rej09b0499-0200 12.5.8 operation timing figures 12.11 to 12.14 show the dtc operation timings. clock address dtc activation request dtc request r w vector read transfer information read data transfer transfer information write figure 12.11 dtc operation timing (example of short address mode in normal transfer mode or repeat transfer mode) clock address dtc activation request dtc request rwr w vector read transfer information read data transfer transfer information write figure 12.12 dtc operation timing (example of short address mode in bloc k transfer mode with block size of 2) section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 494 of 1340 rej09b0499-0200 clock address dtc activation request dtc request rw r w vector read transfer information read data transfer transfer information write transfer information read data transfer transfer information write figure 12.13 dtc operation timing (example of short address mode in chain transfer) clock address dtc activation request dtc request r w vector read transfer information read data transfer transfer information write figure 12.14 dtc operation timing (example of full address mode in normal transfer mode or repeat transfer mode) section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 495 of 1340 rej09b0499-0200 12.5.9 number of dtc execution cycles table 12.9 shows the execution status for a singl e dtc data transfer, an d table 12.10 shows the number of cycles required for each execution. table 12.9 dtc execution status mode vector read i transfer information read j transfer information write l data read l data write m internal operation n normal 1 0 * 1 4 * 2 3 * 3 0 * 1 3 * 2.3 2 * 4 1 * 5 3 * 6 2 * 7 1 3 * 6 2 * 7 1 1 0 * 1 repeat 1 0 * 1 4 * 2 3 * 3 0 * 1 3 * 2.3 2 * 4 1 * 5 3 * 6 2 * 7 1 3 * 6 2 * 7 1 1 0 * 1 block transfer 1 0 * 1 4 * 2 3 * 3 0 * 1 3 * 2.3 2 * 4 1 * 5 3?p * 6 2?p * 7 1?p 3?p * 6 2?p * 7 1?p 1 0 * 1 [legend] p: block size (crah and cral value) note: 1. when transfer information read is skipped 2. in full address mode operation 3. in short address mode operation 4. when the sar or dar is in fixed mode 5. when the sar and dar are in fixed mode 6. when a longword is transferred while an odd address is specified in the address register 7. when a word is transferred while an odd addr ess is specified in the address register or when a longword is transferred while address 4n + 2 is specified section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 496 of 1340 rej09b0499-0200 table 12.10 number of cycles requ ired for each execution state object to be accessed on-chip ram on-chip rom on-chip i/o registers external devices bus width 32 32 8 16 32 8 16 access cycles 1 1 2 2 2 2 3 2 3 vector read s i 1 1 ? ? ? 8 12 + 4m 4 6 + 2m transfer information read s j 1 1 ? ? ? 8 12 + 4m 4 6 + 2m execution status transfer information write s k 1 1 ? ? ? 8 12 + 4m 4 6 + 2m byte data read s l 1 1 2 2 2 2 3 + m 2 3 + m word data read s l 1 1 4 2 2 4 4 + 2m 2 3 + m longword data read s l 1 1 8 4 2 8 12 + 4m 4 6 + 2m byte data write s m 1 1 2 2 2 2 3 + m 2 3 + m word data write s m 1 1 4 2 2 4 4 + 2m 2 3 + m longword data write s m 1 1 8 4 2 8 12 + 4m 4 6 + 2m internal operation s n 1 [legend] m: number of wait cycles 0 to 7 (for det ails, see section 9, bus controller (bsc).) the number of execu tion cycles is calculated from the formula below. note that means the sum of all transfers activ ated by one activation event (the number in which the chne bit is set to 1, plus 1). number of execution cycles = i ? s i + (j ? s j + k ? s k + l ? s l + m ? s m ) + n ? s n 12.5.10 dtc bus release timing the dtc requests the bus mastership to the bus arbiter when an activation request occurs. the dtc releases the bus after a vector read, transf er information read, a single data transfer, or transfer information writeback. the dtc does not release the bus during transfer information read, single data transfer, or transfer information writeback. 12.5.11 dtc priority level control to the cpu the priority of the dtc activation sources over the cpu can be controlled by the cpu priority level specified by bits cpup2 to cpup0 in cpupcr and the dtc priority level specified by bits dtcp2 to dtcp0. for details, see section 7, interrupt controller. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 497 of 1340 rej09b0499-0200 12.6 dtc activation by interrupt the procedure for using the dtc with interrupt activation is shown in figure 12.15. clearing the rrs bit in dtccr to 0 clears the read skip flag of transfer information. read skip is not performed when the dtc is activated after clearing the rrs bit. when updating transfer information, the rrs bit must be cleared. set the mra, mrb, sar, dar, cra, and crb transfer information in the data area. for details on setting transfer information, see section 12.2, register descriptions. for details on location of transfer information, see section 12.4, location of transfer information and dtc vector table. set the start address of the transfer information in the dtc vector table. for details on setting dtc vector table, see section 12.4, location of transfer information and dtc vector table. setting the rrs bit to 1 performs a read skip of second time or later transfer information when the dtc is activated consecu- tively by the same interrupt source. setting the rrs bit to 1 is always allowed. however, the value set during transfer will be valid from the next transfer. set the bit in dtcer corresponding to the dtc activation interrupt source to 1. for the correspondence of interrupts and dtcer, refer to table 12.1. the bit in dtcer may be set to 1 on the second or later transfer. in this case, setting the bit is not needed. set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. for details on the settings of the interrupt enable bits, see the corresponding descriptions of the corresponding module. after the end of one data transfer, the dtc clears the activation source flag or clears the corresponding bit in dtcer and requests an interrupt to the cpu. the operation after transfer depends on the transfer information. for details, see section 12.2, register descriptions and figure 12.4. dtc activation by interrupt clear rrs bit in dtccr to 0 set transfer information (mra, mrb, sar, dar, cra, crb) set starts address of transfer information in dtc vector table set rrs bit in dtccr to 1 set corresponding bit in dtcer to 1 set enable bit of interrupt request for activation source to 1 interrupt request generated dtc activated corresponding bit in dtcer cleared or cpu interrupt requested transfer end [1] [2] [3] [4] [5] [6] [7] [1] [2] [3] [4] [5] [6] [7] determine clearing method of activation source clear activation source clear corresponding bit in dtcer figure 12.15 dtc with interrupt activation section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 498 of 1340 rej09b0499-0200 12.7 examples of use of the dtc 12.7.1 normal transfer mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. 1. set mra to fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal transfer mode (md1 = md0 = 0), and byte size (sz1 = sz0 = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the rdr address of the sci in sar, the start address of the ram area where the data will be received in dar, and 128 (h' 0080) in cra. crb can be set to any value. 2. set the start address of the transfer informatio n for an rxi interrupt at the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the sci to the appropriate receive mode. se t the rie bit in scr to 1 to enable the receive end (rxi) interrupt. since the generation of a receive erro r during the sci reception operation will disable subsequent recep tion, the cpu should be en abled to accept receive error interrupts. 5. each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activ ated. the receive data is transferred from rdr to ram by the dtc. dar is incremented an d cra is decremented. the rdrf flag is automatically cleared to 0. 6. when cra becomes 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interr upt request is sent to the cpu. termination processing should be performed in the interrupt handling routine. 12.7.2 chain transfer an example of dtc chain transfer is shown in which pulse output is performed using the ppg. chain transfer can be used to perform pulse output data transfer and ppg output trigger cycle updating. repeat mode transfer to the ppg's ndr is performed in the first half of the chain transfer, and normal mode transfer to the tpu's tgr in the second half. this is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the ch ain transfer (transfer when chne = 0). section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 499 of 1340 rej09b0499-0200 1. perform settings for transfer to the ppg's ndr. set mra to source address incrementing (sm1 = 1, sm0 = 0), fixed destination address (dm1 = dm0 = 0), repeat mode (md1 = 0, md0 = 1), and word size (sz1 = 0, sz0 = 1). set th e source side as a repeat area (dts = 1). set mrb to chain transfer mode (chne = 1, chns = 0, disel = 0). set the data table start address in sar, the ndrh address in dar, and the da ta table size in crah and cral. crb can be set to any value. 2. perform settings for transfer to the tpu' s tgr. set mra to sour ce address incrementing (sm1 = 1, sm0 = 0), fixed destination address (dm1 = dm0 = 0), normal mode (md1 = md0 = 0), and word size (sz1 = 0, sz0 = 1). set th e data table start address in sar, the tgra address in dar, and the data table size in cra. crb can be set to any value. 3. locate the tpu transfer information consec utively after the ndr transfer information. 4. set the start address of the ndr transfer information to the dtc vector address. 5. set the bit corresponding to the tgia interrupt in dtcer to 1. 6. set tgra as an output compare register (output disabled) with tior, and enable the tgia interrupt with tier. 7. set the initial output value in podr, and the next output value in ndr. set bits in ddr and nder for which output is to be performed to 1. using pcr, select the tpu compare match to be used as the output trigger. 8. set the cst bit in tstr to 1, and start the tcnt count operation. 9. each time a tgra compare match occurs, the ne xt output value is transferred to ndr and the set value of the next output trigger period is transferred to tgra. the activation source tgfa flag is cleared. 10. when the specified number of transfers are completed (the tpu transfer cra value is 0), the tgfa flag is held at 1, the dtce bit is cleared to 0, and a tgia interrupt request is sent to the cpu. termination processing should be performed in the interrupt handling routine. 12.7.3 chain transfer when counter = 0 by executing a second data transfer and performing re -setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. an example is shown in which a 128-kbyte input buffer is configured. the input buffer is assumed to have been set to start at lower addr ess h'0000. figure 12.16 shows the chain transfer when the counter value is 0. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 500 of 1340 rej09b0499-0200 1. for the first transfer, set the normal transfer mode for input da ta. set the fixed transfer source address, cra = h'0000 (65,536 times), chne = 1, chns = 1, and disel = 0. 2. prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first data transfer in a separate area (in rom, etc.). for exam ple, if the input buff er is configured at addresses h'200000 to h'21ffff, prepare h'21 and h'20. 3. for the second transfer, set rep eat transfer mode (with the source side as the repeat area) for re- setting the transfer destination address for the fi rst data transfer. use th e upper eight bits of dar in the first transfer information area as th e transfer destination. set chne = disel = 0. if the above input buffer is specified as h'200000 to h'21ffff, set the transfer counter to 2. 4. execute the first data transfer 65536 times by means of interrupts. when the transfer counter for the first data transfer reaches 0, the second da ta transfer is started. set the upper eight bits of the transfer source address for the first data transfer to h'21. the lower 16 bits of the transfer destination addr ess of the first data transfer an d the transfer c ounter are h'0000. 5. next, execute the first data transfer the 65536 times specified for the first data transfer by means of interrupts. when the tran sfer counter for the first data transfer reaches 0, the second data transfer is started. set th e upper eight bits of the transfer source address for the first data transfer to h'20. the lower 16 b its of the transfer de stination address of th e first data transfer and the transfer co unter are h'0000. 6. steps 4 and 5 are repeated endlessly. as repeat mode is specified for the second data transfer, no interrupt request is sent to the cpu. 1st data transfer information 2nd data transfer information transfer information located on the on-chip memory chain transfer (counter = 0) input circuit input buffer upper 8 bits of dar figure 12.16 chain transfer when counter = 0 section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 501 of 1340 rej09b0499-0200 12.8 interrupt sources an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is genera ted. these interrupts to the cpu are subject to cpu mask level and priority level control in the interrupt controller. 12.9 usage notes 12.9.1 module stop state setting operation of the dtc can be disabled or enabled using the module stop control register. the initial setting is for operation of the dtc to be en abled. register access is disabled by setting the module stop state. the module st op state cannot be set while the dtc is activated. for details, refer to section 27, power-down modes. 12.9.2 on-chip ram transfer information can be located in on-chip ra m. in this case, the ra me bit in syscr must not be cleared to 0. 12.9.3 dmac transfer end interrupt when the dtc is activated by a dmac transfer end interrupt, the dte bit of dmdr is not controlled by the dtc but its value is modified with the write data regardless of the transfer counter value and disel bit setting. accordingl y, even if the dtc transfer counter value becomes 0, no interrupt request may be sent to the cpu in some cases. when the dtc is activated by a dmac transfer en d interrupt, even if disel=0, an automatic clearing of the relevant activation source flag is not automatically cleared by the dtc. therefore, write 1 to the dte bit by the dtc transfer and clear the ac tivation source flag to 0. 12.9.4 dtce bit setting for dtce bit setting, use bit manipulation instruc tions such as bset and bclr. if all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 502 of 1340 rej09b0499-0200 12.9.5 chain transfer when chain transfer is used, clearing of the activation source or dtcer is performed when the last of the chain of data transfers is ex ecuted. at this time, sci and a/d converter interrupt/activation sources, are cl eared when the dtc r eads or writes to the relevant register. therefore, when the dtc is activated by an interr upt or activation source, if a read/write of the relevant register is not included in the last chai ned data transfer, the inte rrupt or activation source will be retained. 12.9.6 transfer information start address, so urce address, and destination address the transfer information start addres s to be specified in the vector table should be address 4n. if an address other than address 4n is specified, the lower 2 bits of th e address are regarded as 0s. the source and destination addresses specified in sar and dar, respectively, will be transferred in the divided bus cycles depending on the address and data size. 12.9.7 transfer information modification when ibccs = 1 and the dmac is used, clear the ibccs bit to 0 and then set to 1 again before modifying the dtc transfer information in the cpu exception handling routine initiated by a dtc transfer end interrupt. 12.9.8 endian format the dtc supports big and little endian formats. the endian formats used when transfer information is written to and when transfer information is read from by the dtc must be the same. section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 503 of 1340 rej09b0499-0200 12.9.9 points for caution when overwriting dtcer when overwriting of the dtc-transfer enable register (dtcer) and the generation of an interrupt that is a source for dtc activation are in co mpetition, activation of the dtc and interrupt exception processing by the cpu wi ll both proceed at the same time. depending on the conditions at this time, doubling of interrupts may occur. if there is a possibility of competition between overwriting of the dtcer and generation of an in terrupt that is a source for dtc activation, proceed with overwriting of the dtcer according to the relevant procedure given below. end end in the case of interrupt-control mode 0 back-up the value of the ccr. set the interrupt-mask bit to 1 (corresponding bit = 1 in the ccr). overwrite the dtcer. dummy-read the dtcer. restore the original value of the interrupt-mask bit. in the case of interrupt-control mode 2 back-up the value of the exr. set the interrupt-request masking level to 7 (in the exr, i2, i1, i0 = b'111). overwrite the dtcer. dummy-read the dtcer. restore the original value of the interrupt-request masking level. interrupts are masked figure 12.17 example of proce dures for overwriting the dtcer section 12 data transfer controller (dtc) rev. 2.00 oct. 20, 2009 page 504 of 1340 rej09b0499-0200 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 505 of 1340 rej09b0499-0200 section 13 i/o ports table 13.1 summarizes the port functions. the pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. each i/o port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, a port register (port) used to read the pin states, and an input buffer control register (icr) that controls input buffer on/off. port 5 does not have a dr or a ddr register. ports d to f, h to k, and i have internal input pull-up moss and a pull-up mos control register (pcr) that controls the on/off state of the input pull-up moss. ports 2 and f include an open-drain control register (odr) that controls on/off of the output buffer pmoss. all of the i/o ports can drive a single ttl load an d capacitive loads up to 30 pf. also, all of the i/o ports can drive darlington transistors when functioning as output ports. port 2, j, and k are schmitt-trigger input. schmitt -trigger inputs for other ports are enabled when used as the irq , tpu, tmr, or iic2 input. table 13.1 po rt functions function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 7 p17/scl0 irq7 -a/ tclkd/ adtrg1 edrak1 irq7 -a, tclkd, scl0 6 p16/sda0 irq6 -a/ tclkc dack1 / edack1 -a irq6 -a, tclkc, sda0 5 p15/scl1 irq5 -a/ tclkb/ rxd5/ irrxd tend1 / etend1 -a irq5 -a, tclkb, scl1 4 p14/sda1 dreq1 / irq4 -a/ tclka/ edreq1 -a txd5/ irtxd irq4 -a, tclka, sda1 port 1 general i/o port also functioning as interrupt inputs, sci i/os, dmac i/os, exdmac i/os, a/d converter inputs, tpu inputs, and iic2 i/os 3 p13 adtrg0 / irq3 -a edrak0 irq3 -a ? ? section 13 i/o ports rev. 2.00 oct. 20, 2009 page 506 of 1340 rej09b0499-0200 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 2 p12/sck2 irq2 -a dack0 / edack0 -a irq2 -a 1 p11 rxd2/ irq1 -a tend0 / etend0 -a irq1 -a port 1 general i/o port also functioning as interrupt inputs, sci i/os, dmac i/os, exdmac i/os, a/d converter inputs, tpu inputs, and iic2 i/os 0 p10 dreq0 / irq0 -a/ edreq0 -a txd2 irq0 -a ? ? 7 p27/ tiocb5 tioca5 po7 p27, tiocb5, tioca5 6 p26/ tioca5 ? po6/tmo1/ txd1 all input functions 5 p25/ tioca4 tmci1/ rxd1 po5 p25, tioca4, tmci1 4 p24/ tiocb4/ sck1 tioca4/ tmri1 po4 p24, tiocb4, tioca4, tmri1 3 p23/ tiocd3 irq11 -a/ tiocc3 po3 p23, tiocd3, irq11 -a 2 p22/ tiocc3 irq10 -a po2/tmo0/ txd0 all input functions 1 p21/ tioca3 tmci0/ rxd0/ irq9 -a po1 p21, irq9 -a, tioca3, tmci0 port 2 general i/o port also functioning as interrupt inputs, ppg outputs, tpu i/os, tmr i/os, and sci i/os 0 p20/ tiocb3/ sck0 tioca3/ tmri0/ irq8 -a po0 p20, irq8 -a, tiocb3, tioca3, tmri0 ? o section 13 i/o ports rev. 2.00 oct. 20, 2009 page 507 of 1340 rej09b0499-0200 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 7 ? p57/an7/ irq7 -b da1 irq7 -b 6 ? p56/an6/ irq6 -b da0 irq6 -b 5 ? p55/an5/ irq5 -b ? irq5 -b 4 ? p54/an4/ irq4 -b ? irq4 -b 3 ? p53/an3/ irq3 -b ? irq3 -b 2 ? p52/an2/ irq2 -b ? irq2 -b 1 ? p51/an1/ irq1 -b ? irq1 -b port 5 general input port also functioning as interrupt inputs, a/d converter inputs, and d/a converter outputs 0 ? p50/an0/ irq0 -b ? irq0 -b ? ? section 13 i/o ports rev. 2.00 oct. 20, 2009 page 508 of 1340 rej09b0499-0200 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 7 ? ? ? ? 6 ? ? ? ? 5 p65 tck tmo3/ dack3 / edack1 -b tck 4 p64 tmci3/tdi tend3 / etend1 -b tmci3, tdi 3 p63 tmri3/ dreq3 / irq11 -b/ tms/ edreq1 -b ? tmri3, irq11 -b, tms 2 p62/sck4 irq10 -b/ trst tmo2/ dack2 / edack0 -b irq10 -b, trst 1 p61 tmci2/ rxd4/ irq9 -b tend2 / etend0 -b tmci2, irq9 -b port 6 general i/o port also functioning as sci inputs, dmac i/os, exdmac i/os, h-udi inputs, and interrupt inputs 0 p60 tmri2/ dreq2 / irq8 -b/ edreq0 -b txd4 tmri2, irq8 -b ? ? 7 ? pa7 b 6 pa6 ? as / ah / bs -b 5 pa5 ? rd 4 pa4 ? lhwr / lub 3 pa3 ? llwr / llb 2 pa2 breq / wait ? 1 pa1 ? back / (rd/ wr ) port a general i/o port also functioning as system clock output and bus control i/os 0 pa0 ? breqo / bs -a ? ? ? section 13 i/o ports rev. 2.00 oct. 20, 2009 page 509 of 1340 rej09b0499-0200 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 3 pb3 ? cs3 / cs7 -a 2 pb2 ? cs2 -a/ cs6 -a 1 pb1 ? cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b port b general i/o port also functioning as bus control outputs 0 pb0 ? cs0 / cs4 / cs5 -b ? ? ? 7 pd7 ? a7 6 pd6 ? a6 5 pd5 ? a5 4 pd4 ? a4 3 pd3 ? a3 2 pd2 ? a2 1 pd1 ? a1 port d * 3 general i/o port also functioning as address outputs 0 pd0 ? a0 ? o ? 7 pe7 ? a15 6 pe6 ? a14 5 pe5 ? a13 4 pe4 ? a12 3 pe3 ? a11 2 pe2 ? a10 1 pe1 ? a9 port e * 3 general i/o port also functioning as address outputs 0 pe0 ? a8 ? o ? section 13 i/o ports rev. 2.00 oct. 20, 2009 page 510 of 1340 rej09b0499-0200 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 4 pf4 ? a20 3 pf3 ? a19 2 pf2 ? a18 1 pf1 ? a17 port f general i/o port also functioning as address outputs 0 pf0 ? a16 ? o o 7 ph7/d7 * 2 ? ? 6 ph6/d6 * 2 ? ? 5 ph5/d5 * 2 ? ? 4 ph4/d4 * 2 ? ? 3 ph3/d3 * 2 ? ? 2 ph2/d2 * 2 ? ? 1 ph1/d1 * 2 ? ? port h general i/o port also functioning as bi-directional data bus 0 ph0/d0 * 2 ? ? ? o ? 7 pi7/d15 * 2 ? ? 6 pi6/d14 * 2 ? ? 5 pi5/d13 * 2 ? ? 4 pi4/d12 * 2 ? ? 3 pi3/d11 * 2 ? ? 2 pi2/d10 * 2 ? ? 1 pi1/d9 * 2 ? ? port i general i/o port also functioning as bi-directional data bus 0 pi0/d8 * 2 ? ? ? o ? 7 pj7/tiocb8 tioca8/tclkh po23 6 pj6/tioca8 ? po22 5 pj5/tiocb7 tioca7/tclkg po21 4 pj4/tioca7 ? po20 3 pj3/tiocd6 tiocc6/tclkf po19 2 pj2/tiocc6 tclke po18 1 pj1/tiocb6 tioca6 po17 port j * 4 general i/o port also functioning ppg i/os and tpu i/os 0 pj0/tioca6 ? po16 all input functions o ? section 13 i/o ports rev. 2.00 oct. 20, 2009 page 511 of 1340 rej09b0499-0200 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 7 pk7/tiocb11 tioca11 po31 6 pk6/tioca11 ? po30 5 pk5/tiocb10 tioca10 po29 4 pk4/tioca10 ? po28 3 pk3/tiocd9 tiocc9 po27 2 pk2/tiocc9 ? po26 1 pk1/tiocb9 tioca9 po25 port k * 4 general i/o port also functioning ppg i/os and tpu i/os 0 pk0/tioca9 ? po24 all input functions o ? 7 ? ? ? 6 ? ? ? 5 ? ? ? 4 pm4 ? ? 3 pm3 ? ? 2 pm2 ? ? 1 pm1 rxd6 ? port m general i/o port also functioning as sci i/os 0 pm0 ? txd6 ? ? ? notes: 1. pins without schmitt-tri gger input have cmos input functions. 2. addresses are also output when access ing to the address/data multiplexed i/o space. 3. pins are disabled when pcjke = 1. 4. pins are disabled when pcjke = 0. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 512 of 1340 rej09b0499-0200 13.1 register descriptions table 13.2 lists each port registers. table 13.2 register configuration in each port registers port number of pins ddr dr port icr pcr odr port 1 8 o o o o ? ? port 2 8 o o o o ? o port 5 8 ? ? o o ? ? port 6 * 3 6 o o o o ? ? port a 8 o o o o ? ? port b * 4 4 o o o o ? ? port d * 1 8 o o o o o ? port e * 1 8 o o o o o ? port f * 5 5 o o o o o o port h 8 o o o o o ? port i 8 o o o o o ? port j * 2 8 o o o o o ? port k * 2 8 o o o o o ? port m * 6 5 o o o o ? ? [legend] o: register exists ? : no register exists notes: 1. do not access port d or e registers when pcjke = 1. 2. do not access port j or k registers when pcjke = 0. 3. the lower six bits are valid and the upper two bits are reserved for port 6 registers. the write value should be the same as the initial value. 4. the lower four bits are valid and the upper four bits are reserved for port b registers. the write value should be the sa me as the initial value. 5. the lower five bits are valid and the upper three bits are reserved for port f registers. the write value should be the sa me as the initial value. 6. the lower five bits are valid and the upper three bits are reserved for port m registers. the write value should be the sa me as the initial value. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 513 of 1340 rej09b0499-0200 13.1.1 data direction register (pnddr) (n = 1, 2, 6, a, b, d to f, h to k, and m) ddr is an 8-bit write-only register that specifies the port input or output fo r each bit. a read from the ddr is invalid and ddr is alwa ys read as an undefined value. when the general i/o port function is selected, the corresponding pin functions as an output port by setting the corresponding ddr bit to 1; the corresponding pin functions as an input port by clearing the corresponding ddr bit to 0. the initial ddr values are shown in table 13.3. bit bit name initial value r/w note: the lower six bits are valid and the upper two bits are reserved for port 6 registers. the lower four bits are valid and the upper four bits are reserved for port b registers. the lower five bits are valid and the upper three bits are reserved for port f registers. the lower five bits are valid and the upper three bits are reserved for port m registers. do not access port j or k registers when pcjke = 0. do not access port d or e registers when pcjke = 1. 7 pn7ddr 0 w 6 pn6ddr 0 w 5 pn5ddr 0 w 4 pn4ddr 0 w 3 pn3ddr 0 w 2 pn2ddr 0 w 1 pn1ddr 0 w 0 pn0ddr 0 w table 13.3 startup mode and initial value startup mode port external extended mode single-chip mode port a h'80 h'00 other ports h'00 h'00 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 514 of 1340 rej09b0499-0200 13.1.2 data register (pndr) (n = 1, 2, 6, a, b, d to f, h to k, and m) dr is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. the initial value of dr is h'00. note: the lower six bits are valid and the upper two bits are reserved for port 6 registers. the lower four bits are valid and the upper four bits are reserved for port b registers. the lower five bits are valid and the upper three bits are reserved for port f registers. the lower five bits are valid and the upper three bits are reserved for port m registers. do not access port j or k registers when pcjke = 0. do not access port d or e registers when pcjke = 1. bit bit name initial value r/w 7 pn7dr 0 r/w 6 pn6dr 0 r/w 5 pn5dr 0 r/w 4 pn4dr 0 r/w 3 pn3dr 0 r/w 2 pn2dr 0 r/w 1 pn1dr 0 r/w 0 pn0dr 0 r/w 13.1.3 port register (portn) (n = 1, 2, 5, 6, a, b, d to f, h to k, and m) port is an 8-bit read-only register that reflects the port pin state. a write to port is invalid. when port is read, the dr bits that correspond to th e respective ddr bits set to 1 are read and the status of each pin whose corr esponding ddr bit is cleared to 0 is also read regardless of the icr value. the initial value of port is undefined and is determined based on the port pin state. note: the lower six bits are valid and the upper two bits are reserved for port 6 registers. the lower four bits are valid and the upper four bits are reserved for port b registers. the lower five bits are valid and the upper three bits are reserved for port f registers. the lower five bits are valid and the upper three bits are reserved for port m registers. do not access port j or k registers when pcjke = 0. do not access port d or e registers when pcjke = 1. bit bit name initial value r/w 7 pn7 undefined r 6 pn6 undefined r 5 pn5 undefined r 4 pn4 undefined r 3 pn3 undefined r 2 pn2 undefined r 1 pn1 undefined r 0 pn0 undefined r section 13 i/o ports rev. 2.00 oct. 20, 2009 page 515 of 1340 rej09b0499-0200 13.1.4 input buffer control register (pnicr) (n = 1, 2, 5, 6, a, b, d to f, h to k, and m) icr is an 8-bit readable/writable register that controls the port input buffers. for bits in icr set to 1, the input buffers of the corresponding pins are valid. for bits in icr cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. when the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. the initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. when port is read, the pin state is always read regardless of the icr value. when the icr value is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral module. if icr is modified, an internal edge may occur depending on the pin state. accordingly, icr should be modified when the corresponding input pins are not used. for example, an irq input, modify icr while the corresponding interrupt is disabled, clear the irqf flag in isr of the interrupt controller to 0, and then enable the co rresponding interrupt. if an edge occurs after the icr setting, the edge should be cancelled. the initial value of icr is h'00. note: the lower six bits are valid and the upper two bits are reserved for port 6 registers. the lower four bits are valid and the upper four bits are reserved for port b registers. the lower five bits are valid and the upper three bits are reserved for port f registers. the lower five bits are valid and the upper three bits are reserved for port m registers. do not access port j or k registers when pcjke = 0. do not access port d or e registers when pcjke = 1. bit bit name initial value r/w 7 pn7icr 0 r/w 6 pn6icr 0 r/w 5 pn5icr 0 r/w 4 pn4icr 0 r/w 3 pn3icr 0 r/w 2 pn2icr 0 r/w 1 pn1icr 0 r/w 0 pn0icr 0 r/w section 13 i/o ports rev. 2.00 oct. 20, 2009 page 516 of 1340 rej09b0499-0200 13.1.5 pull-up mos control register (pnpcr) (n = d to f, and h to k) pcr is an 8-bit readable/writable register that controls on/off of the port input pull-up mos. if a bit in pcr is set to 1 while the pin is in input state, the input pull-up mos corresponding to the bit in pcr is turned on. table 13.4 shows the input pull-up mos state. the initial value of pcr is h'00. bit bit name initial value r/w 7 pn7pcr 0 r/w 6 pn6pcr 0 r/w 5 pn5pcr 0 r/w 4 pn4pcr 0 r/w 3 pn3pcr 0 r/w 2 pn2pcr 0 r/w 1 pn1pcr 0 r/w 0 pn0pcr 0 r/w note: the lower five bits are valid and the upper three bits are reserved for port f registers. table 13.4 input pull-up mos state port pin state reset hardware standby mode software standby mode other operation port d address output off port output off port input off on/off port e address output off port output off port input off on/off port f address output off port output off port input off on/off port h data input/output off port output off port input off on/off port i data input/output off port output off port input off on/off section 13 i/o ports rev. 2.00 oct. 20, 2009 page 517 of 1340 rej09b0499-0200 port pin state reset hardware standby mode software standby mode other operation port j peripheral module output off port output off port input off on/off port k peripheral module output off port output off port input off on/off [legend] off: the input pull-up mos is always off. on/off: if pcr is set to 1, the input pull-up mos is on; if pcr is cleared to 0, the input pull-up mos is off. 13.1.6 open-drain control register (pnodr) (n = 2 and f) odr is an 8-bit readable/writable register th at selects the open-dra in output function. if a bit in odr is set to 1, the pin corresponding to that bit in odr functions as an nmos open- drain output. if a bit in odr is cleared to 0, the pin corresponding to that bit in odr functions as a cmos output. the initial value of odr is h'00. bit bit name initial value r/w 7 pn7odr 0 r/w 6 pn6odr 0 r/w 5 pn5odr 0 r/w 4 pn4odr 0 r/w 3 pn3odr 0 r/w 2 pn2odr 0 r/w 1 pn1odr 0 r/w 0 pn0odr 0 r/w section 13 i/o ports rev. 2.00 oct. 20, 2009 page 518 of 1340 rej09b0499-0200 13.2 output buffer control this section describes the ou tput priority of each pin. the name of each peripheral module pin is followed by "_oe". this (for example: tioca4_oe) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). table 13.5 lists each port output signal's valid setting. for details on the corresponding output signals, see the register description of each peripheral module. if the name of each peripheral module pin is followed by a or b, the pin function can be modified by the port function control register (pfcr). for details, see section 13.3, port function controller. for a pin whose initial value changes according to th e activation mode, "initi al value e" indicates the initial value when the lsi is started up in external extended mode and "initial value s" indicates the initial value when the lsi is started in single-chip mode. 13.2.1 port 1 (1) p17/ irq7 -a/tclkd/scl0/ edrak1 / adtrg1 the pin function is switched as shown below acc ording to the combination of the exdmac and iic2 register settings and p17ddr bit setting. setting exdmac iic2 i/o port module name pin function edrak1 _oe scl0_oe p17ddr exdmac edrak1 output 1 ? ? iic2 scl0 input/output 0 1 ? i/o port p17 output 0 0 1 p17 input (initial value) 0 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 519 of 1340 rej09b0499-0200 (2) p16/ dack1 / irq6 -a/tclkc/sda0/ edack1 -a the pin function is switched as shown below according to the combination of the exdmac, dmac and iic2 register settings and p16ddr bit setting. setting exdmac dmac iic2 i/o port module name pin function edack1a _oe dack1 _oe sda0_oe p16ddr exdmac edack1 -a output 1 ? ? ? dmac dack1 output 0 1 ? ? iic2 sda0 input/output 0 0 1 ? p16 output 0 0 0 1 i/o port p16 input (initial value) 0 0 0 0 (3) p15/rxd5/irrxd/ tend1 / etend1 -a/ irq5 -a/tclkb/scl1 the pin function is switched as shown below according to the combination of the exdmac, dmac and iic2 register settings and p15ddr bit setting. setting exdmac dmac iic2 i/o port module name pin function etend1a _oe tend1 _oe scl1_oe p15ddr exdmac etend1 -a output 1 ? ? ? dmac tend1 output 0 1 ? ? iic2 scl1 input/output 0 0 1 ? p15 output 0 0 0 1 i/o port p15 input (initial value) 0 0 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 520 of 1340 rej09b0499-0200 (4) p14/txd5/irtxd/ dreq1 / edreq1 -a/ irq4 -a/tclka/sda1 the pin function is switched as shown below according to the combination of the sci, irda, and iic2 register settings and p14ddr bit setting. setting sci irda iic2 i/o port module name pin function txd 5_oe irtxd_oe sda1_oe p14ddr sci txd5 output 1 ? ? ? irda irtxd output 0 1 ? ? iic2 sda1 input/output 0 0 1 ? i/o port p14 output 0 0 0 1 p14 input (initial value) 0 0 0 0 (5) p13/ adtrg0 / irq3 -a/ edrak0 the pin function is switched as shown below according to the register setting of exdmac and the p13ddr bit setting. setting exdmac i/o port module name pin function edrak0 _oe p13ddr i/o port edrak0 output 1 ? p13 output 0 1 p13 input (initial value) 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 521 of 1340 rej09b0499-0200 (6) p12/sck2/ dack0 / irq2 -a/ edack0 -a the pin function is switched as shown below according to the combination of the exdmac, dmac and sci register settings and p12ddr bit setting. setting exdmac dmac sci i/o port module name pin function edack0a _oe dack0 _oe sck2_oe p12ddr exdmac edack0 -a output 1 ? ? ? dmac dack0 output 0 1 ? ? sci sck2 output 0 0 1 ? p12 output 0 0 0 1 i/o port p12 input (initial value) 0 0 0 0 (7) p11/rxd2/ tend0 / irq1 -a/ etend0 -a the pin function is switched as shown below according to the combination of the exdmac and dmac register settings and p11ddr bit setting. setting exdmac dmac i/o port module name pin function etend0a _oe tend0 _oe p11ddr exdmac etend0 -a output 1 ? ? dmac tend0 output 0 1 ? p11 output 0 0 1 i/o port p11 input (initial value) 0 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 522 of 1340 rej09b0499-0200 (8) p10/txd2/ dreq0 / irq0 -a/ edreq0 -a the pin function is switched as shown below according to the combination of the sci register setting and p10ddr bit setting. setting sci i/o port module name pin function txd2_oe p10ddr sci txd2 output 1 ? p10 output 0 1 i/o port p10 input (initial value) 0 0 13.2.2 port 2 (1) p27/po7/tioca5/tiocb5 the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p27ddr bit setting. setting tpu ppg i/o port module name pin function tiocb5_oe po7_oe p27ddr tpu tiocb5 output 1 ? ? ppg po7 output 0 1 ? p27 output 0 0 1 i/o port p27 input (initial value) 0 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 523 of 1340 rej09b0499-0200 (2) p26/po6/tioca5/tmo1/txd1 the pin function is switched as shown below according to the combination of the tpu, tmr, sci, and ppg register settings and p26ddr bit setting. setting tpu tmr sci ppg i/o port module name pin function tioca5_oe tmo1_oe txd1_oe po6_oe p26ddr tpu tioca5 output 1 ? ? ? ? tmr tmo1 output 0 1 ? ? ? sci txd1 output 0 0 1 ? ? ppg po6 output 0 0 0 1 ? p26 output 0 0 0 0 1 i/o port p26 input (initial value) 0 0 0 0 0 (3) p25/po5/tioca4/tmci1/rxd1 the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p25ddr bit setting. setting tpu ppg i/o port module name pin function tioca4_oe po5_oe p25ddr tpu tioca4 output 1 ? ? ppg po5 output 0 1 ? p25 output 0 0 1 i/o port p25 input (initial value) 0 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 524 of 1340 rej09b0499-0200 (4) p24/po4/tioca4/tiocb4/tmri1/sck1 the pin function is switched as shown below according to the combination of the tpu, sci, and ppg register settings and p24ddr bit setting. setting tpu sci ppg i/o port module name pin function tiocb4_oe sck1_oe po4_oe p24ddr tpu tiocb4 output 1 ? ? ? sci sck1 output 0 1 ? ? ppg po4 output 0 0 1 ? p24 output 0 0 0 1 i/o port p24 input (initial value) 0 0 0 0 (5) p23/po3/tiocc3/tiocd3/ irq11 -a the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p23ddr bit setting. setting tpu ppg i/o port module name pin function tiocd3_oe po3_oe p23ddr tpu tiocd3 output 1 ? ? ppg po3 output 0 1 ? p23 output 0 0 1 i/o port p23 input (initial value) 0 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 525 of 1340 rej09b0499-0200 (6) p22 /po2/tiocc3/tmo0/txd0/ irq10 -a the pin function is switched as shown below according to the combination of the tpu, tmr, sci, and ppg register settings and p22ddr bit setting. setting tpu tmr sci ppg i/o port module name pin function tiocc3_oe tmo0_oe txd0_oe po2_oe p22ddr tpu tiocc3 output 1 ? ? ? ? tmr tmo0 output 0 1 ? ? ? sci txd0 output 0 0 1 ? ? ppg po2 output 0 0 0 1 ? p22 output 0 0 0 0 1 i/o port p22 input (initial value) 0 0 0 0 0 (7) p21/po1/tioca3/tmci0/rxd0/ irq9 -a the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p21ddr bit setting. setting tpu ppg i/o port module name pin function tioca3_oe po1_oe p21ddr tpu tioca3 output 1 ? ? ppg po1 output 0 1 ? p21 output 0 0 1 i/o port p21 input (initial value) 0 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 526 of 1340 rej09b0499-0200 (8) p20/po0/tioca3/tiocb3/tmri0/sck0/ irq8 -a the pin function is switched as shown below according to the combination of the tpu, ppg, and sci register settings and p20ddr bit setting. setting tpu sci ppg i/o port module name pin function tiocb3_oe sck0_oe po0_oe p20ddr tpu tiocb3 output 1 ? ? ? sci sck0 output 0 1 ? ? ppg po0 output 0 0 1 ? p20 output 0 0 0 1 i/o port p20 input (initial value) 0 0 0 0 13.2.3 port 5 (1) p57/an7/da1/ irq7 -b module name pin function d/a converter da1 output (2) p56/an6/da0/ irq6 -b module name pin function d/a converter da0 output section 13 i/o ports rev. 2.00 oct. 20, 2009 page 527 of 1340 rej09b0499-0200 13.2.4 port 6 (1) p65/tmo3/ dack3 / edack1 -b/tck the pin function is switched as shown below according to the combination of the exdmac, dmac and tmr register settings and p65ddr bit setting. setting exdmac dmac tmr i/o port module name pin function mcu operating mode edack1b _oe dack3 _oe tmo3_oe p65ddr exdmac edack1 -b output 1 ? ? ? dmac dack3 output 0 1 ? ? tmr tmo3 output 0 0 1 ? p65 output 0 0 0 1 i/o port p65 input (initial value) except for boundary scan enabled mode * 0 0 0 0 note: * these pins are boundary scan dedicated input pins during boundary scan enabled mode. (2) p64/tmci3/ tend3 / etend1 -b/tdi the pin function is switched as shown below according to the combination of the exdmac and dmac register settings and p64ddr bit setting. setting exdmac dmac i/o port module name pin function mcu operating mode etend1b _oe tend3 _oe p64ddr exdmac etend1 -b output 1 ? ? dmac tend3 output 0 1 ? i/o port p64 output 0 0 1 p64 input (initial value) except for boundary scan enabled mode * 0 0 0 note: * these pins are boundary scan dedicated input pins during boundary scan enabled mode. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 528 of 1340 rej09b0499-0200 (3) p63/tmri3/ dreq3 / edreq1 -b/ irq11 -b/tms the pin function is switched as shown below according to the p63ddr bit setting. setting i/o port module name pin function mcu operating mode p63ddr i/o port p63 output 1 p63 input (initial value) except for boundary scan enabled mode * 0 note: * these pins are boundary scan dedicated input pins during boundary scan enabled mode. (4) p62/tmo2/sck4/ dack2 / edack0 -b/ irq10 -b/ trst the pin function is switched as shown below according to the combination of the exdmac, dmac, tmr, and sci register settings and p62ddr bit setting. setting exdmac dmac tmr sci i/o port module name pin function mcu operating mode edack0b _oe dack2 _oe tmo2_oe sck4_oe p62ddr exdmac edack0 -b output 1 ? ? ? ? dmac dack2 output 0 1 ? ? ? tmr tmo2 output 0 0 1 ? ? sci sck4 output 0 0 0 1 ? p62 output 0 0 0 0 1 i/o port p62 input (initial value) except for boundary scan enabled mode * 0 0 0 0 0 note: * these pins are boundary scan dedicated input pins during boundary scan enabled mode. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 529 of 1340 rej09b0499-0200 (5) p61/tmci2/rxd4/ tend2 / etend0 -b/ irq9 -b the pin function is switched as shown below according to the combination of the exdmac and dmac register settings and p61ddr bit setting. setting exdmac dmac i/o port module name pin function etend0b _oe tend2 _oe p61ddr exdmac etend0 -b output 1 ? ? dmac tend2 output 0 1 ? i/o port p61 output 0 0 1 p61 input (initial value) 0 0 0 (6) p60/tmri2/txd4/ dreq2 / edreq0 -b/ irq8 -b the pin function is switched as shown below according to the combination of the sci register setting and p60ddr bit setting. setting sci i/o port module name pin function txd4_oe p60ddr sci txd4 output 1 ? p60 output 0 1 i/o port p60 input (initial value) 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 530 of 1340 rej09b0499-0200 13.2.5 port a (1) pa7/b the pin function is switched as shown below according to the pa7ddr bit setting. setting i/o port module name pin function pa7ddr i/o port b output * (initial value e) 1 pa7 input (initial value s) 0 [legend] initial value e: initial value in external extended mode initial value s: initial value in single-chip mode (2) pa6/ as / ah / bs -b the pin function is switched as shown below according to the combination of operating mode and the expe bit, the bus controller register, the port function control register (pfcr), and the pa6ddr bit settings. setting bus controller i/o port module name pin function ah _oe bs -b_oe as _oe pa6ddr ah output * 1 ? ? ? bs -b output * 0 1 ? ? bus controller as output * (initial value e) 0 0 1 ? pa6 output 0 0 0 1 i/o port pa6 input (initial value s) 0 0 0 0 [legend] initial value e: initial value in external extended mode initial value s: initial value in single-chip mode note: * valid in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 531 of 1340 rej09b0499-0200 (3) pa5/ rd the pin function is switched as shown below according to the combination of operating mode, the expe bit, and the pa5ddr bit settings. setting mcu operating mode i/o port module name pin function expe pa5ddr bus controller rd output * (initial value e) 1 ? pa5 output 0 1 i/o port pa5 input (initial value s) 0 0 [legend] initial value e: initial value in external extended mode initial value s: initial value in single-chip mode note: * valid in external extended mode (expe = 1) (4) pa4/ lhwr / lub the pin function is switched as shown below according to the combination of operating mode and the expe bit, the bus controller register, the port function control register (pfcr), and the pa4ddr bit settings. setting bus controller i/o port module name pin function lub _oe * 2 lhwr _oe * 2 pa4ddr lub output * 1 1 ? ? bus controller lhwr output * 1 (initial value e) ? 1 ? pa4 output 0 0 1 i/o port pa4 input (initial value s) 0 0 0 [legend] initial value e: initial value in external extended mode initial value s: initial value in single-chip mode notes: 1. valid in external extended mode (expe = 1) 2. when the byte control sram space is ac cessed while the byte control sram space is specified or while lhwroe = 1, this pin functions as the lub output; otherwise, the lhwr output. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 532 of 1340 rej09b0499-0200 (5) pa3/ llwr / llb the pin function is switched as shown below according to the combination of operating mode and the expe bit, the bus controller register, and the pa3ddr bit settings. setting bus controller i/o port module name pin function llb _oe * 2 llwr _oe * 2 pa3ddr llb output * 1 1 ? ? bus controller llwr output * 1 (initial value e) ? 1 ? pa3 output 0 0 1 i/o port pa3 input (initial value s) 0 0 0 [legend] initial value e: initial value in external extended mode initial value s: initial value in single-chip mode notes: 1. valid in external extended mode (expe = 1) 2. if the byte control sram space is accessed, this pin functions as the llb output; otherwise, the llwr . (6) pa2/ breq / wait the pin function is switched as shown below according to the combination of the bus controller register settings and the pa2ddr bit setting. setting bus controller i/o port module name pin function bcr_brle bcr_waite pa2ddr breq input 1 ? ? bus controller wait input 0 1 ? pa2 output 0 0 1 i/o port pa2 input (initial value) 0 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 533 of 1340 rej09b0499-0200 (7) pa1/ back /(rd/ wr ) the pin function is switched as shown below according to the combination of operating mode and the expe bit, the bus controller register, the port function control register (pfcr), and the pa1ddr bit settings. setting bus controller i/o port module name pin function back _oe byte control sram selection (rd/ wr )_oe pa1ddr back output * 1 ? ? ? 0 1 ? ? bus controller rd/ wr output * 0 0 1 ? pa1 output 0 0 0 1 i/o port pa1 input (initial value) 0 0 0 0 note: * valid in external extended mode (expe = 1) (8) pa0/ breqo / bs -a the pin function is switched as shown below according to the combination of operating mode and the expe bit, the bus controller register, the port function control register (pfcr), and the pa0ddr bit settings. setting i/o port bus controller i/o port module name pin function bs -a_oe breqo _oe pa0ddr bs -a output * 1 ? ? bus controller breqo output * 0 1 ? pa0 output 0 0 1 i/o port pa0 input (initial value) 0 0 0 note: * valid in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 534 of 1340 rej09b0499-0200 13.2.6 port b (1) pb3/ cs3 / cs7 -a the pin function is switched as shown below according to the combination of operating mode and the expe bit, the port function control register (pfcr), and the pb3ddr bit settings. setting i/o port module name pin function cs3 _oe cs7a _oe pb3ddr cs3 output * 1 ? ? bus controller cs7 -a output * ? 1 ? pb3 output 0 0 1 i/o port pb3 input (initial value) 0 0 0 note: * valid in external extended mode (expe = 1) (2) pb2/ cs2 -a/ cs6 -a the pin function is switched as shown below according to the combination of operating mode and the expe bit, the port function control register (pfcr), and the pb2ddr bit settings. setting i/o port module name pin function cs2a _oe cs6a _oe pb2ddr cs2 -a output * 1 ? ? bus controller cs6 -a output * ? 1 ? pb2 output 0 0 1 i/o port pb2 input (initial value) 0 0 0 note: * valid in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 535 of 1340 rej09b0499-0200 (3) pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b the pin function is switched as shown below according to the combination of operating mode and the expe bit, the bus controller register, the port function control register (pfcr), and the pb1ddr bit settings. setting i/o port module name pin function cs1 _oe cs2b _oe cs5a _oe cs6b _oe cs7b _oe pb1ddr cs1 output * 1 ? ? ? ? ? cs2 -b output * ? 1 ? ? ? ? cs5 -a output * ? ? 1 ? ? ? cs6 -b output * ? ? ? 1 ? ? bus controller cs7 -b output * ? ? ? ? 1 ? pb1 output 0 0 0 0 0 1 i/o port pb1 input (initial value) 0 0 0 0 0 0 note: * valid in external extended mode (expe = 1) (4) pb0/ cs0 / cs4 / cs5 -b the pin function is switched as shown below according to the combination of operating mode and the expe bit, the bus controller register, the port function control register (pfcr), and the pb0ddr bit settings. setting i/o port module name pin function cs0 _oe cs4 _oe cs5b _oe pb0ddr cs0 output (initial value e) 1 ? ? ? cs4 output ? 1 ? ? bus controller cs5 -b output ? ? 1 ? pb0 output 0 0 0 1 i/o port pb0 input (initial value s) 0 0 0 0 [legend] initial value e: initial value in on-chip rom disabled external mode initial value s: initial value in other modes note: * valid in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 536 of 1340 rej09b0499-0200 13.2.7 port d the pin function of port d can be switched with that of port j according to the combination of operating mode, the expe bit, and the pcjke bit settings. the pin function of port d can be switched according to the pcjke bit setting in the single-chip mode (expe = 0). however, do not change the setting of the pcjke bit in external extended mode. for details, see section 13.3.12, port function control register d (pfcrd). (1) pd7/a7, pd6/a6, pd5/a5, pd4/a4, pd3/a3, pd2/a2, pd1/a1, pd0/a0 the pin function is switched as shown below according to the combination of operating mode, the expe bit, and the pdnddr bit settings. setting i/o port module name pin function mcu operating mode pdnddr on-chip rom disabled extended mode ? bus controller address output on-chip rom enabled extended mode 1 pdn output single-chip mode * 1 i/o port pdn input (initial value) modes other than on-chip rom disabled extended mode 0 [legend] n: 0 to 7 note: * address output is enabled by setting pdnddr = 1 in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 537 of 1340 rej09b0499-0200 13.2.8 port e the pin function of port e can be switched with that of port k according to the combination of operating mode, the expe bit, and the pcjke bit settings. the pin function of port e can be switched according to the pcjke bit setting in the single-chip mode (expe = 0). however, do not change the setting of the pcjke bit in external extended mode. for details, see section 13.3.12, port function control register d (pfcrd). (1) pe7/a15, pe6/a14, pe5/a13, pe4/a12, pe3/a11, pe2/a10, pe1/a9, pe0/a8 the pin function is switched as shown below according to the combination of operating mode, the expe bit, and the penddr bit settings. setting i/o port module name pin function mcu operating mode penddr on-chip rom disabled extended mode ? bus controller address output on-chip rom enabled extended mode 1 pen output single-chip mode * 1 i/o port pen input (initial value) modes other than on-chip rom disabled extended mode 0 [legend] n: 0 to 7 note: * address output is enabled by setting pdnddr = 1 in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 538 of 1340 rej09b0499-0200 13.2.9 port f (1) pf4/a20 the pin function is switched as shown below according to the combination of operating mode, the expe bit, the port function control register (pfcr), and the pf4ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a20_oe pf4ddr on-chip rom disabled extended mode bus controller a20 output ? ? bus controller a20 output * 1 ? pf4 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf4 input (initial value) 0 0 note: * valid in external extended mode (expe = 1) (2) pf3/a19 the pin function is switched as shown below according to the combination of operating mode, the expe bit, the port function control register (pfcr), and the pf3ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a19_oe pf3ddr on-chip rom disabled extended mode bus controller a19 output ? ? bus controller a19 output * 1 ? pf3 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf3 input (initial value) 0 0 note: * valid in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 539 of 1340 rej09b0499-0200 (3) pf2/a18 the pin function is switched as shown below according to the combination of operating mode, the expe bit, the port function control register (pfcr), and the pf2ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a18_oe pf2ddr on-chip rom disabled extended mode bus controller a18 output ? ? bus controller a18 output * 1 ? pf2 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf2 input (initial value) 0 0 note: * valid in external extended mode (expe = 1) (4) pf1/a17 the pin function is switched as shown below according to the combination of operating mode, the expe bit, the port function control register (pfcr), and the pf1ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a17_oe pf1ddr on-chip rom disabled extended mode bus controller a17 output ? ? bus controller a17 output * 1 ? pf1 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf1 input (initial value) 0 0 note: * valid in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 540 of 1340 rej09b0499-0200 (5) pf0/a16 the pin function is switched as shown below according to the combination of operating mode, the expe bit, the port function control register (pfcr), and the pf0ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a16_oe pf0ddr on-chip rom disabled extended mode bus controller a16 output ? ? bus controller a16 output * 1 ? pf0 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf0 input (initial value) 0 0 note: * valid in external extended mode (expe = 1) 13.2.10 port h (1) ph7/d7, ph6/d6, ph5/d5, ph4/d4, ph3/d3, ph2/d2, ph1/d1, ph0/d0 the pin function is switched as shown below according to the combination of operating mode, the expe bit, and the phnddr bit settings. setting mcu operating mode i/o port module name pin function expe phnddr bus controller data i/o * (initial value e) 1 ? phn output 0 1 i/o port phn input (initial value s) 0 0 [legend] initial value e: initial value in external extended mode initial value s: initial value in single-chip mode n: 0 to 7 note: * valid in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 541 of 1340 rej09b0499-0200 13.2.11 port i (1) pi7/d15, pi6/d14, pi5/d13, pi4/d12, pi3/d11, pi2/d10, pi1/d9, pi0/d8 the pin function is switched as shown below according to the combination of operating mode, bus mode, the expe bit, and the pinddr bit settings. setting bus controller i/o port module name pin function 16-bit bus mode pinddr bus controller data i/o * (initial value e) 1 ? pin output 0 1 i/o port pin input (initial value s) 0 0 [legend] initial value e: initial value in external extended mode initial value s: initial value in single-chip mode n: 0 to 7 note: * valid in external extended mode (expe = 1) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 542 of 1340 rej09b0499-0200 13.2.12 port j the pin function of port j can be switched with that of port d according to the combination of operating mode, the expe bit, and the pcjke bit settings. the pin function of port j can be switched according to the pcjke bit setting in the single-chip mode (expe = 0). however, do not change the setting of the pcjke bit in external extended mode. for details, see section 13.3.12, port function control register d (pfcrd). (1) pj7/tioca8/tiocb8/tclkh/po23 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pj7ddr bit settings. setting ppg tpu i/o port module name pin function po23_oe tiocb8_oe pj7ddr ppg po23 output * 1 ? ? tpu tiocb8 output * 0 1 ? pj7 output * 0 0 1 i/o port pj7 input * 0 0 0 note: * valid when pcjke = 1. (2) pj6/tioca8/po22 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pj6ddr bit settings. setting ppg tpu i/o port module name pin function po22_oe tioca8_oe pj6ddr ppg po22 output * 1 ? ? tpu tioca8 output * 0 1 ? pj6 output * 0 0 1 i/o port pj6 input * 0 0 0 note: * valid when pcjke = 1. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 543 of 1340 rej09b0499-0200 (3) pj5/tioca7/tiocb7/tclkg/po21 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pj5ddr bit settings. setting ppg tpu i/o port module name pin function po21_oe tiocb7_oe pj5ddr ppg po21 output * 1 ? ? tpu tiocb7 output * 0 1 ? pj5 output * 0 0 1 i/o port pj5 input * 0 0 0 note: * valid when pcjke = 1. (4) pj4/tioca7/po20 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pj4ddr bit settings. setting ppg tpu i/o port module name pin function po20_oe tioca7_oe pj4ddr ppg po20 output * 1 ? ? tpu tioca7 output * 0 1 ? pj4 output * 0 0 1 i/o port pj4 input * 0 0 0 note: * valid when pcjke = 1. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 544 of 1340 rej09b0499-0200 (5) pj3/po19/tiocc6/tiocd6/tclkf the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pj3ddr bit settings. setting ppg tpu i/o port module name pin function po19_oe tiocd6_oe pj3ddr ppg po19 output * 1 ? ? tpu tiocd6 output * 0 1 ? pj3 output * 0 0 1 i/o port pj3 input * 0 0 0 note: * valid when pcjke = 1. (6) pj2/po18/tiocc6/tclke the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pj2ddr bit settings. setting ppg tpu i/o port module name pin function po18_oe tiocc6_oe pj2ddr ppg po18 output * 1 ? ? tpu tiocc6 output * 0 1 ? pj2 output * 0 0 1 i/o port pj2 input * 0 0 0 note: * valid when pcjke = 1. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 545 of 1340 rej09b0499-0200 (7) pj1/po17/tioca6/tiocb6 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pj1ddr bit settings. setting ppg tpu i/o port module name pin function po17_oe tiocb6_oe pj1ddr ppg po17 output * 1 ? ? tpu tiocb6 output * 0 1 ? pj1 output * 0 0 1 i/o port pj1 input * 0 0 0 note: * valid when pcjke = 1. (8) pj0/po16/tioca6 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pj0ddr bit settings. setting ppg tpu i/o port module name pin function po16_oe tioca6_oe pj0ddr ppg po16 output * 1 ? ? tpu tioca6 output * 0 1 ? pj0 output * 0 0 1 i/o port pj0 input * 0 0 0 note: * valid when pcjke = 1. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 546 of 1340 rej09b0499-0200 13.2.13 port k the pin function of port k can be switched with that of port e according to the combination of operating mode, the expe bit, and the pcjke bit settings. the pin function of port k can be switched according to the pcjke bit setting in the single-chip mode (expe = 0). however, do not change the setting of the pcjke bit in external extended mode. for details, see section 13.3.12, port function control register d (pfcrd). (1) pk7/po31/tioca11/tiocb11 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pk7ddr bit settings. setting ppg tpu i/o port module name pin function po31_oe tiocb11_oe pk7ddr ppg po31 output * 1 ? ? tpu tiocb11 output * 0 1 ? pk7 output * 0 0 1 i/o port pk7 input * 0 0 0 note: * valid when pcjke = 1. (2) pk6/po30/tioca11 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pk6ddr bit settings. setting ppg tpu i/o port module name pin function po30_oe tioca11_oe pk6ddr ppg po30 output * 1 ? ? tpu tioca11 output * 0 1 ? pk6 output * 0 0 1 i/o port pk6 input * 0 0 0 note: * valid when pcjke = 1. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 547 of 1340 rej09b0499-0200 (3) pk5/po29/tioca10/tiocb10 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pk5ddr bit settings. setting ppg tpu i/o port module name pin function po29_oe tiocb10_oe pk5ddr ppg po29 output * 1 ? ? tpu tiocb10 output * 0 1 ? pk5 output * 0 0 1 i/o port pk5 input * 0 0 0 note: * valid when pcjke = 1. (4) pk4/po28/tioca10 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pk4ddr bit settings. setting ppg tpu i/o port module name pin function po28_oe tioca10_oe pk4ddr ppg po28 output * 1 ? ? tpu tioca10 output * 0 1 ? pk4 output * 0 0 1 i/o port pk4 input * 0 0 0 note: * valid when pcjke = 1. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 548 of 1340 rej09b0499-0200 (5) pk3/po27/tiocc9/tiocd9 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pk3ddr bit settings. setting ppg tpu i/o port module name pin function po27_oe tiocd9_oe pk3ddr ppg po27 output * 1 ? ? tpu tiocd9 output * 0 1 ? pk3 output * 0 0 1 i/o port pk3 input * 0 0 0 note: * valid when pcjke = 1. (6) pk2/po26/tiocc9 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pk2ddr bit settings. setting ppg tpu i/o port module name pin function po26_oe tiocc9_oe pk2ddr ppg po26 output * 1 ? ? tpu tiocc9 output * 0 1 ? pk2 output * 0 0 1 i/o port pk2 input * 0 0 0 note: * valid when pcjke = 1. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 549 of 1340 rej09b0499-0200 (7) pk1/po25/tioca9/tiocb9 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pk1ddr bit settings. setting ppg tpu i/o port module name pin function po25_oe tiocb9_oe pk1ddr ppg po25 output * 1 ? ? tpu tiocb9 output * 0 1 ? pk1 output * 0 0 1 i/o port pk1 input * 0 0 0 note: * valid when pcjke = 1. (8) pk0/po24/tioca9 the pin function is switched as shown below according to the combination of register setting of ppg and tpu, setting of the port function control register (pfcr), and the pk0ddr bit settings. setting ppg tpu i/o port module name pin function po24_oe tioca9_oe pk0ddr ppg po24 output * 1 ? ? tpu tioca9 output * 0 1 ? pk0 output * 0 0 1 i/o port pk0 input * 0 0 0 note: * valid when pcjke = 1. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 550 of 1340 rej09b0499-0200 13.2.14 port m (1) pm4 the pin function is switched as shown below according to the combination of the usb register setting and the pm4ddr bit setting. setting usb i/o port module name pin function pullup_e pm4ddr usb pullup control output 1 ? pm4 output 0 1 i/o port pm4 input (initial value) 0 0 (2) pm3 the pin function is switched as shown below according to the combination of the pm3ddr bit setting. setting i/o port module name pin function pm3ddr pm3 output 1 i/o port pm3 input (initial value) 0 (3) pm2 the pin function is switched as shown below according to the combination of the pm2ddr bit setting. setting i/o port module name pin function pm2ddr pm2 output 1 i/o port pm2 input (initial value) 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 551 of 1340 rej09b0499-0200 (4) pm1/rxd6 the pin function is switched as shown below according to the combination of the pm1ddr bit setting. setting i/o port module name pin function pm1ddr pm1 output 1 i/o port pm1 input (initial value) 0 (5) pm0/txd6 the pin function is switched as shown below according to the combination of the sci register setting and pm0ddr bit setting. setting sci i/o port module name pin function txd6_oe pm0ddr sci txd6 output 1 ? pm0 output 0 1 i/o port pm0 input (initial value) 0 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 552 of 1340 rej09b0499-0200 table 13.5 available output sign als and settings in each port port output specification signal name output signal name signal selection register settings peripheral module settings edrak1 _oe edrak1 pfcr8.edmas1[a,b] = 00 syscr.expe = 1, edmdr_1.edrake = 1 7 scl0_oe scl0 iccra.ice = 1 edack1a _oe edack1 pfcr8.edmas1[a,b] = 00 syscr.expe = 1, edacr_1.ams = 1, edmdr_1.edrake = 1 dack1 _oe dack1 pfcr7.dmas1[a,b] = 00 dmac.dacr_1.ams = 1, dmdr_1.dacke = 1 6 sda0_oe sda0 iccra.ice = 1 etend1a _oe etend1 pfcr8.edmas1[a,b] = 00 syscr.expe = 1, edmdr_1.etende = 1 tend1 _oe tend1 pfcr7.dmas1[a,b] = 00 dmdr_1.tende = 1 5 scl1_oe scl1 iccra.ice = 1 txd5_oe txd5 scr.te = 1, ircr.ire = 0 irtxd_oe irtxd scr.te = 1, ircr.ire = 1 4 sda1_oe sda1 iccra.ice = 1 3 edrak0 _oe edrak0 pfcr8.edmas0[a,b] = 00 syscr.expe = 1, edmdr_0.edrake = 1 edack0a _oe edack0 pfcr8.edmas0[a,b] = 00 syscr.expe = 1, edacr_0.ams = 1, edmdr_0.edacke = 1 dack0 _oe dack0 pfcr7.dmas0[a,b] = 00 dmac.dacr_0.ams = 1, dmdr_0.dacke = 1 2 sck2_oe sck2 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke [1, 0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke [1, 0] = 01 or while smr.c/a = 1, scr.cke 1 = 0 etend0a _oe etend0 pfcr8.edmas0[a,b] = 00 syscr.expe = 1, edmdr_0.etende = 1 1 tend0 _oe tend0 pfcr7.dmas0[a,b] = 00 dmdr_0.tende = 1 p1 0 txd2_oe txd2 scr.te = 1 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 553 of 1340 rej09b0499-0200 port output specification signal name output signal name signal selection register settings peripheral module settings tiocb5_oe tiocb5 tpu.tior_5.iob3 = 0, tpu.tior_5.iob[1,0] = 01/10/11 7 po7_oe po7 nderl.nder7 = 1 tioca5_oe tioca5 tpu.tior_5.ioa3 = 0, tpu.tior_5.ioa[1,0] = 01/10/11 tmo1_oe tmo1 tmr.tcsr_1.tcsr.os3,2 = 01/10/11 or tmr.tcsr_1.os[1,0] = 01/10/11 txd1_oe txd1 scr.te = 1 6 po6_oe po6 nderl.nder6 = 1 tioca4_oe tioca4 tpu.tior_4.ioa3 = 0, tpu.tior_4.ioa[1,0] = 01/10/11 5 po5_oe po5 nderl.nder5 = 1 tiocb4_oe tiocb4 tpu.tior_4.iob3 = 0, tpu.tior_4.iob[1,0] = 01/10/11 sck1_oe sck1 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke [1, 0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke [1, 0] = 01 or while smr.c/a = 1, scr.cke 1 = 0 4 po4_oe po4 nderl.nder4 = 1 tiocd3_oe tiocd3 tpu.tmdr.bfb = 0, tpu.tiorl_3.iod3 = 0, tpu.tiorl_3.iod[1,0] = 01/10/11 3 po3_oe po3 nderl.nder3 = 1 tiocc3_oe tiocc3 tpu.tmdr.bfa = 0, tpu.tiorl_3.ioc3 = 0, tpu.tiorl_3.iod[1,0] = 01/10/11 tmo0_oe tmo0 tmr.tcsr_0.os[3,2] = 01/10/11 or tmr.tcsr_0.os[1,0] = 01/10/11 txd0_oe txd0 scr.te = 1 p2 2 po2_oe po2 nderl.nder2 = 1 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 554 of 1340 rej09b0499-0200 port output specification signal name output signal name signal selection register settings peripheral module settings tioca3_oe tioca3 tpu.tiorh_3.ioa3 = 0, tpu.tiorh_3.ioa[1,0] = 01/10/11 1 po1_oe po1 nderl.nder1 = 1 tiocb3_oe tiocb3 tpu.tiorh_3.iob3=0, tpu.tiorh_3.iob[1,0] = 01/10/11 sck0_oe sck0 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke [1, 0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke [1, 0] = 01 or while smr.c/a = 1, scr.cke 1 = 0 p2 0 po0_oe po0 nderl.nder0 = 1 edack1b _oe edack1 pfcr8.edmas1[a,b] = 01 syscr.expe = 1, edacr_1.ams = 1, edmdr_1.edacke = 1 dack3 _oe dack3 pfcr7.dmas3[a,b] = 01 dmac.dacr_3.ams = 1, dmdr_3.dacke = 1 5 tmo3_oe tmo3 tmr.tcsr_3.os[3,2] = 01/10/11 or tmr.tcsr_3.os[1,0] = 01/10/11 etend1b _oe etend1 pfcr8.edmas1[a,b] = 01 syscr.expe = 1, edmdr_1.etende = 1 4 tend3 _oe tend3 pfcr7.dmas3[a,b] = 01 dmdr_3.tende = 1 edack0b _oe edack0 pfcr8.edmas0[a,b] = 01 syscr.expe = 1, edacr_0.ams = 1, edmdr_0.edacke = 1 dack2 _oe dack2 pfcr7.dmas2[a,b] = 01 dmac.dacr_2.ams = 1, dmdr_2.dacke = 1 tmo2_oe tmo2 tmr.tcsr_2.os[3,2] = 01/10/11 or tmr.tcsr_2.os[1,0] = 01/10/11 p6 2 sck4_oe sck4 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke [1, 0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke [1, 0] = 01 or while smr.c/a = 1, scr.cke 1 = 0 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 555 of 1340 rej09b0499-0200 port output specification signal name output signal name signal selection register settings peripheral module settings etend0b _oe etend0 pfcr8.edmas0[a,b] = 01 syscr.expe = 1, edmdr_0.etende = 1 1 tend2 _oe tend2 pfcr7.dmas2[a,b] = 01 dmdr_2.tende = 1 p6 0 txd4_oe txd4 scr.te = 1 7 b _oe b paddr.pa7ddr = 1, sckcr.pstop1 = 0 ah _oe ah syscr.expe = 1, mpxcr.mpxen (n = 7 to 3) = 1 bsb _oe bs pfcr2.bss = 1 syscr.expe = 1, pfcr2.bse = 1 6 as _oe as syscr.expe = 1, pfcr2.asoe = 1 5 rd _oe rd syscr.expe = 1 lub _oe lub syscr.expe = 1, pfcr6.lhwroe = 1 or sramcr.bcseln = 1 4 lhwr _oe lhwr syscr.expe = 1, pfcr6.lhwroe = 1 llb _oe llb syscr.expe = 1, sramcr.bcseln = 1 3 llwr _oe llwr syscr.expe = 1 back _oe back syscr.expe = 1,bcr1.brle = 1 1 (rd/ wr )_oe rd/ wr syscr.expe = 1, pfcr2.rdwre = 1 or sramcr.bcseln = 1 bsa _oe bs pfcr2.bss = 0 syscr.expe = 1, pfcr2.bse = 1 pa 0 breqo _oe breqo syscr.expe = 1, bcr1.brle = 1, bcr1.breqoe = 1 cs3 _oe cs3 syscr.expe = 1, pfcr0.cs3e = 1 3 cs7a _oe cs7 pfcr1.cs7s[a,b] = 00 syscr.expe = 1, pfcr0.cs7e = 1 2 cs2a _oe cs2 pfcr2.cs2s = 0 syscr.expe = 1, pfcr0.cs2e = 1 cs6a _oe cs6 pfcr1.cs6s[a,b] = 00 syscr.expe = 1, pfcr0.cs6e = 1 cs1 _oe cs1 syscr.expe = 1, pfcr0.cs1e = 1 cs2b _oe cs2 pfcr2.cs2s = 1 syscr.expe = 1, pfcr0.cs2e = 1 cs5a _oe cs5 pfcr1.cs5s[a,b] = 00 syscr.expe = 1, pfcr0.cs5e = 1 cs6b _oe cs6 pfcr1.cs6s[a,b] = 01 syscr.expe = 1, pfcr0.cs6e = 1 1 cs7b _oe cs7 pfcr1.cs7s[a,b] = 01 syscr.expe = 1, pfcr0.cs7e = 1 cs0 _oe cs0 syscr.expe = 1, pfcr0.cs0e = 1 cs4 _oe cs4 syscr.expe = 1, pfcr0.cs4e = 1 pb 0 cs5b _oe cs5 pfcr1.cs5s[a,b] = 01 syscr.expe = 1, pfcr0.cs5e = 1 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 556 of 1340 rej09b0499-0200 port output specification signal name output signal name signal selection register settings peripheral module settings 7 a7_oe a7 syscr.expe = 1, pdddr.pd7ddr = 1 6 a6_oe a6 syscr.expe = 1, pdddr.pd6ddr = 1 5 a5_oe a5 syscr.expe = 1, pdddr.pd5ddr = 1 4 a4_oe a4 syscr.expe = 1, pdddr.pd4ddr = 1 3 a3_oe a3 syscr.expe = 1, pdddr.pd3ddr = 1 2 a2_oe a2 syscr.expe = 1, pdddr.pd2ddr = 1 1 a1_oe a1 syscr.expe = 1, pdddr.pd1ddr = 1 pd 0 a0_oe a0 syscr.expe = 1, pdddr.pd0ddr = 1 7 a15_oe a15 syscr.expe = 1, peddr.pe7ddr = 1 6 a14_oe a14 syscr.expe = 1, peddr.pe6ddr = 1 5 a13_oe a13 syscr.expe = 1, pedr.pe5ddr = 1 4 a12_oe a12 syscr.expe = 1, peddr.pe4ddr = 1 3 a11_oe a11 syscr.expe = 1, peddr.pe3ddr = 1 2 a10_oe a10 syscr.expe = 1, peddr.pe2ddr = 1 1 a9_oe a9 syscr.expe = 1, peddr.pe1ddr = 1 pe 0 a8_oe a8 syscr.expe = 1, peddr.pe0ddr = 1 4 a20_oe a20 syscr.expe = 1, pfcr4.a20e = 1 3 a19_oe a19 syscr.expe = 1, pfcr4.a19e = 1 2 a18_oe a18 syscr.expe = 1, pfcr4.a18e = 1 1 a17_oe a17 syscr.expe = 1, pfcr4.a17e = 1 pf 0 a16_oe a16 syscr.expe = 1, pfcr4.a16e = 1 7 d7_e d7 syscr.expe = 1 6 d6_e d6 syscr.expe = 1 5 d5_e d5 syscr.expe = 1 4 d4_e d4 syscr.expe = 1 3 d3_e d3 syscr.expe = 1 2 d2_e d2 syscr.expe = 1 1 d1_e d1 syscr.expe = 1 ph 0 d0_e d0 syscr.expe = 1 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 557 of 1340 rej09b0499-0200 port output specification signal name output signal name signal selection register settings peripheral module settings 7 d15_e d15 syscr.expe = 1, abwcr.abw[h,l]n = 01 6 d14_e d14 syscr.expe = 1, abwcr.abw[h,l]n = 01 5 d13_e d13 syscr.expe = 1, abwcr.abw[h,l]n = 01 4 d12_e d12 syscr.expe = 1, abwcr.abw[h,l]n = 01 3 d11_e d11 syscr.expe = 1, abwcr.abw[h,l]n = 01 2 d10_e d10 syscr.expe = 1, abwcr.abw[h,l]n = 01 1 d9_e d9 syscr.expe = 1, abwcr.abw[h,l]n = 01 pi 0 d8_e d8 syscr.expe = 1, abwcr.abw[h,l]n = 01 tiocb8_oe tiocb8 tpu.tior_8.iob3 = 0, tpu.tior_8.iob[1,0] = 01/10/11 7 po 23_oe po23 nderl_1.nder23 = 1 tioca8_oe tioca8 tpu.tior_8.ioa3 = 0, tpu.tior_8.ioa[1,0] = 01/10/11 6 po 22_oe po22 nderl_1.nder22 = 1 tiocb7_oe tiocb7 tpu.tior_7.iob3 = 0, tpu.tior_7.iob[1,0] = 01/10/11 5 po 21_oe po21 nderl_1.nder21 = 1 tioca7_oe tioca7 tpu.tior_7.ioa3 = 0, tpu.tior_7.ioa[1,0] = 01/10/11 4 po 20_oe po20 nderl_1.nder20 = 1 tiocd6_oe tiocd6 tpu.tmdr_6.bfb = 0, tpu.tiorl_6.iod3 =0, tpu.tiorl_6.iod[1,0] = 01/10/11 3 po 19_oe po19 nderl_1.nder19 = 1 tiocc6_oe tiocc6 tpu.tmdr_6.bfa = 0, tpu.tiorl_6.ioc3 = 0, tpu.tiorl_6.ioc[1,0] = 01/10/11 2 po 18_oe po18 nderl_1.nder18 = 1 tiocb6_oe tiocb6 tpu.tiorh_6.iob3 = 0, tpu.tiorh_6.iob[1,0] = 01/10/11 1 po 17_oe po17 nderl_1.nder17 = 1 tioca6_oe tioca6 tpu.tiorh_6.ioa3 = 0, tpu.tiorh_6.ioa[1,0] = 01/10/11 pj 0 po 16_oe po16 nderl_1.nder16 = 1 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 558 of 1340 rej09b0499-0200 port output specification signal name output signal name signal selection register settings peripheral module settings tiocb11_oe tiocb11 tpu.tior_11.iob3 = 0, tpu.tior_11.iob[1,0] = 01/10/11 7 po31_oe po31 nderh_1.nder31 = 1 tioca11_oe tioca11 tpu.tior_11.ioa3 = 0, tpu.tior_11.ioa[1,0] = 01/10/11 6 po30_oe po30 nderh_1.nder30 = 1 tiocb10_oe tiocb10 tpu.tior_10.iob3 = 0, tpu.tior_10.iob[1,0] = 01/10/11 5 po29_oe po29 nderh_1.nder29 = 1 tioca10_oe tioca10 tpu.tior_10.ioa3 = 0, tpu.tior_10.ioa[1,0] = 01/10/11 4 po28_oe po28 nderh_1.nder28 = 1 tiocd9_oe tiocd9 tpu.tmdr_9.bfb = 0, tpu.tiorl_9.iod3 = 0, tpu.tiorl_9.iod[1,0] = 01/10/11 3 po27_oe po27 nderh_1.nder27 = 1 tiocc9_oe tiocc9 tpu.tmdr_9.bfa = 0, tpu.tiorl_9.ioc3 = 0, tpu.tiorl_9.ioc[1,0] = 01/10/11 2 po26_oe po26 nderh_1.nder26 = 1 tiocb9_oe tiocb9 tpu.tiorh_9.iob3 = 0, tpu.tiorh_9.iob[1,0] = 01/10/11 1 po25_oe po25 nderh_1.nder25 = 1 tioca9_oe tioca9 tpu.tiorh_9.ioa3 = 0, tpu.tiorh_9.ioa[1,0] = 01/10/11 pk 0 po24_oe po24 nderh_1.nder24 = 1 section 13 i/o ports rev. 2.00 oct. 20, 2009 page 559 of 1340 rej09b0499-0200 13.3 port function controller the port function controller controls the i/o ports. the port function controller incorp orates the following registers. ? port function control register 0 (pfcr0) ? port function control register 1 (pfcr1) ? port function control register 2 (pfcr2) ? port function control register 4 (pfcr4) ? port function control register 6 (pfcr6) ? port function control register 7 (pfcr7) ? port function control register 8 (pfcr8) ? port function control register 9 (pfcr9) ? port function control register a (pfcra) ? port function control register b (pfcrb) ? port function control register c (pfcrc) ? port function control register d (pfcrd) section 13 i/o ports rev. 2.00 oct. 20, 2009 page 560 of 1340 rej09b0499-0200 13.3.1 port function contro l register 0 (pfcr0) pfcr0 enables/disables the cs output. bit bit name initial value r/w note: * 1 in external extended mode; 0 in other modes. 7 cs7e 0 r/w 6 cs6e 0 r/w 5 cs5e 0 r/w 4 cs4e 0 r/w 3 cs3e 0 r/w 2 cs2e 0 r/w 1 cs1e 0 r/w 0 cs0e undefined * r/w bit bit name initial value r/w description 7 cs7e 0 r/w 6 cs6e 0 r/w 5 cs5e 0 r/w 4 cs4e 0 r/w 3 cs3e 0 r/w 2 cs2e 0 r/w 1 cs1e 0 r/w 0 cs0e undefined * r/w cs7 to cs0 enable these bits enable/disable the corresponding csn output. 0: pin functions as i/o port 1: pin functions as csn output pin (n = 7 to 0) note: * 1 in external extended mode, 0 in other modes. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 561 of 1340 rej09b0499-0200 13.3.2 port function contro l register 1 (pfcr1) pfcr1 selects the cs output pins. bit bit name initial value r/w 7 cs7sa 0 r/w 6 cs7sb 0 r/w 5 cs6sa 0 r/w 4 cs6sb 0 r/w 3 cs5sa 0 r/w 2 cs5sb 0 r/w 1 cs4sa 0 r/w 0 cs4sb 0 r/w bit bit name initial value r/w description 7 6 cs7sa * cs7sb * 0 0 r/w r/w cs7 output pin select selects the output pin for cs7 when cs7 output is enabled (cs7e = 1) 00: specifies pin pb3 as cs7 -a output 01: specifies pin pb1 as cs7 -b output 10: setting prohibited 11: setting prohibited 5 4 cs6sa * cs6sb * 0 0 r/w r/w cs6 output pin select selects the output pin for cs6 when cs6 output is enabled (cs6e = 1) 00: specifies pin pb2 as cs6 -a output 01: specifies pin pb1 as cs6 -b output 10: setting prohibited 11: setting prohibited 3 2 cs5sa * cs5sb * 0 0 r/w r/w cs5 output pin select selects the output pin for cs5 when cs5 output is enabled (cs5e = 1) 00: specifies pin pb1 as cs5 -a output 01: specifies pin pb0 as cs5 -b output 10: setting prohibited 11: setting prohibited section 13 i/o ports rev. 2.00 oct. 20, 2009 page 562 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 0 cs4sa * cs4sb * 0 0 r/w r/w cs4 output pin select selects the output pin for cs4 when cs4 output is enabled (cs4e = 1) 00: specifies pin pb0 as cs4 output 01: setting prohibited 10: setting prohibited 11: setting prohibited note: * if multiple cs outputs are specified to a single pin according to the csn output pin select bits (n = 4 to 7), multiple cs signals are output from the pin. for details, see section 9.5.3, chip select signals. 13.3.3 port function contro l register 2 (pfcr2) pfcr2 selects the cs output pin, enables/disables bus control i/o, and selects the bus control i/o pins. bit bit name initial value r/w 7 ? 0 r 6 cs2s 0 r/w 5 bss 0 r/w 4 bse 0 r/w 3 ? 0 r 2 rdwre 0 r/w 1 asoe 1 r/w 0 ? 0 r bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 cs2s * 1 0 r/w cs2 output pin select selects the output pin for cs2 when cs2 output is enabled (cs2e = 1) 0: specifies pin pb2 as cs2 -a output pin 1: specifies pin pb1 as cs2 -b output pin section 13 i/o ports rev. 2.00 oct. 20, 2009 page 563 of 1340 rej09b0499-0200 bit bit name initial value r/w description 5 bss 0 r/w bs output pin select selects the bs output pin 0: specifies pin pa0 as bs -a output pin 1: specifies pin pa6 as bs -b output pin 4 bse 0 r/w bs output enable enables/disables the bs output 0: disables the bs output 1: enables the bs output 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 rdwre * 2 0 r/w rd/ wr output enable enables/disables the rd/ wr output 0: disables the rd/ wr output 1: enables the rd/ wr output 1 asoe 1 r/w as output enable enables/disables the as output 0: specifies pin pa6 as i/o port 1: specifies pin pa6 as as output pin 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. notes: 1. if multiple cs outputs are specified to a single pin according to the csn output pin select bit (n = 2), multiple cs signals are output from the pin. for details, see section 9.5.3, chip select signals. 2. if an area is specified as a byte cont rol sdram space, the pin functions as rd/ wr output regardless of the rdwre bit value. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 564 of 1340 rej09b0499-0200 13.3.4 port function contro l register 4 (pfcr4) pfcr4 enables/disables the address output. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 a20e 0/1 * r/w 3 a19e 0/1 * r/w 2 a18e 0/1 * r/w 1 a17e 0/1 * r/w 0 a16e 0/1 * r/w bit bit name initial value r/w description 7 to 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 a20e 0/1 * r/w address a20 enable enables/disables t he address output (a20) 0: disables the a20 output 1: enables the a20 output 3 a19e 0/1 * r/w address a19 enable enables/disables t he address output (a19) 0: disables the a19 output 1: enables the a19 output 2 a18e 0/1 * r/w address a18 enable enables/disables t he address output (a18) 0: disables the a18 output 1: enables the a18 output 1 a17e 0/1 * r/w address a17 enable enables/disables t he address output (a17) 0: disables the a17 output 1: enables the a17 output 0 a16e 0/1 * r/w address a16 enable enables/disables t he address output (a16) 0: disables the a16 output 1: enables the a16 output note: * initial value is switched according to oper ating mode. 1 when on-chip rom disabled, 0 when enabled. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 565 of 1340 rej09b0499-0200 13.3.5 port function contro l register 6 (pfcr6) pfcr6 selects the tpu clock input pin. bit bit name initial value r/w 7 ? 1 r/w 6 lhwroe 1 r/w 5 ? 1 r/w 4 ? 0 r 3 tclks 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w bit bit name initial value r/w description 7 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. 6 lhwroe 1 r/w lhwr output enable enables/disables lhwr output (valid in external extended mode). 0: specifies pin pa4 as i/o port 1: specifies pin pa4 as lhwr output pin 5 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. 4 ? 0 r reserved this is a read-only bit and cannot be modified. 3 tclks 0 r/w tpu external clock input pin select selects the tpu external clock input pins. 0: the tpu external clock input pins cannot be used. 1: specifies pins p14 to p17 as external clock input pins. 2 to 0 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 566 of 1340 rej09b0499-0200 13.3.6 port function contro l register 7 (pfcr7) pfcr7 selects the dmac i/o pins ( dreq , dack , and tend ). bit bit name initial value r/w 7 dmas3a 0 r/w 6 dmas3b 0 r/w 5 dmas2a 0 r/w 4 dmas2b 0 r/w 3 dmas1a 0 r/w 2 dmas1b 0 r/w 1 dmas0a 0 r/w 0 dmas0b 0 r/w bit bit name initial value r/w description 7 6 dmas3a dmas3b 0 0 r/w r/w dmac control pin select selects the i/o port to control dmac_3. 00: dmac_3 control pins are disabled. 01: specifies pins p63 to p65 as dmac control pins 10: setting prohibited 11: setting prohibited 5 4 dmas2a dmas2b 0 0 r/w r/w dmac control pin select selects the i/o port to control dmac_2. 00: dmac_2 control pins are disabled. 01: specifies pins p60 to p62 as dmac control pins 10: setting prohibited 11: setting prohibited 3 2 dmas1a dmas1b 0 0 r/w r/w dmac control pin select selects the i/o port to control dmac_1. 00: specifies pins p14 to p16 as dmac control pins 01: setting prohibited 10: setting prohibited 11: setting prohibited 1 0 dmas0a dmas0b 0 0 r/w r/w dmac control pin select selects the i/o port to control dmac_0. 00: specifies pins p10 to p12 as dmac control pins 01: setting prohibited 10: setting prohibited 11: setting prohibited section 13 i/o ports rev. 2.00 oct. 20, 2009 page 567 of 1340 rej09b0499-0200 13.3.7 port function contro l register 8 (pfcr8) pfcr8 selects the exdmac i/o pins ( edreq , edack , etend , and edrak ). bit bit name initial value r/w 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 edmas1a 0 r/w 2 edmas1b 0 r/w 1 edmas0a 0 r/w 0 edmas0b 0 r/w bit bit name initial value r/w description 7 to 4 ? 0 r/w reserved bit the write value should always be 0. 3 2 edmas1a edmas1b 0 0 r/w r/w exdmac control pin select selects the i/o port to control exdmac_1. 00: specifies pins p14 to p17 as exdmac control pins 01: specifies pins p63 to p65 as exdmac control pins 10: setting prohibited 11: setting prohibited 1 0 edmas0a edmas0b 0 0 r/w r/w exdmac control pin select selects the i/o port to control exdmac_0. 00: specifies pins p10 to p13 as exdmac control pins 01: specifies pins p60 to p62 as exdmac control pins 10: setting prohibited 11: setting prohibited section 13 i/o ports rev. 2.00 oct. 20, 2009 page 568 of 1340 rej09b0499-0200 13.3.8 port function contro l register 9 (pfcr9) pfcr9 selects the multiple functions for the tpu i/o pins. bit bit name initial value r/w 7 tpums5 0 r/w 6 tpums4 0 r/w 5 tpums3a 0 r/w 4 tpums3b 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w bit bit name initial value r/w description 7 tpums5 0 r/w tpu i/o pin multiplex function select selects tioca5 function. 0: specifies pin p26 as output compare output and input capture 1: specifies p27 as input capture input and p26 as output compare 6 tpums4 0 r/w tpu i/o pin multiplex function select selects tioca4 function. 0: specifies p25 as output compare output and input capture 1: specifies p24 as input capture input and p25 as output compare 5 tpums3a 0 r/w tpu i/o pin multiplex function select selects tioca3 function. 0: specifies p21 as output compare output and input capture 1: specifies p20 as input capture input and p21 as output compare 4 tpums3b 0 r/w tpu i/o pin multiplex function select selects tiocc3 function. 0: specifies p22 as output compare output and input capture 1: specifies p23 as input capture input and p22 as output compare 3 to 0 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 569 of 1340 rej09b0499-0200 13.3.9 port function control register a (pfcra) pfcra selects the multiple functions for the tpu i/o pins. bit bit name initial value r/w 7 tpums11 0 r/w 6 tpums10 0 r/w 5 tpums9a 0 r/w 4 tpums9b 0 r/w 3 tpums8 0 r/w 2 tpums7 0 r/w 1 tpums6a 0 r/w 0 tpum6b 0 r/w bit bit name initial value r/w description 7 tpums11 0 r/w tpu i/o pin multiplex function select selects tioca11 function. 0: specifies pin pk6 as output compare output and input capture 1: specifies pk7 as input capture input and pk6 as output compare 6 tpums10 0 r/w tpu i/o pin multiplex function select selects tioca10 function. 0: specifies pk4 as output compare output and input capture 1: specifies pk5 as input capture input and pk4 as output compare 5 tpums9a 0 r/w tpu i/o pin multiplex function select selects tioca9 function. 0: specifies pk0 as output compare output and input capture 1: specifies pk1 as input capture input and pk0 as output compare 4 tpums9b 0 r/w tpu i/o pin multiplex function select selects tiocc9 function. 0: specifies pk2 as output compare output and input capture 1: specifies pk3 as input capture input and pk2 as output compare section 13 i/o ports rev. 2.00 oct. 20, 2009 page 570 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 tpums8 0 r/w tpu i/o pin multiplex function select selects tioca8 function. 0: specifies pk6 as output compare output and input capture 1: specifies pk7 as input capture input and pk6 as output compare 2 tpums7 0 r/w tpu i/o pin multiplex function select selects tioca7 function. 0: specifies pj4 as output compare output and input capture 1: specifies pj5 as input capture input and pj4 as output compare 1 tpums6a 0 r/w tpu i/o pin multiplex function select selects tioca6 function. 0: specifies pj0 as output compare output and input capture 1: specifies pj1 as input capture input and pj0 as output compare 0 tpums6b 0 r/w tpu i/o pin multiplex function select selects tiocc6 function. 0: specifies pj2 as output compare output and input capture 1: specifies pj3 as input capture input and pj2 as output compare section 13 i/o ports rev. 2.00 oct. 20, 2009 page 571 of 1340 rej09b0499-0200 13.3.10 port function control register b (pfcrb) pfcrb selects an lvd interrupt* and the input pins for irq11 to irq8 . bit bit name initial value r/w 7 ? 0 r/w 6 its14 * 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 its11 0 r/w 2 its10 0 r/w 1 its9 0 r/w 0 its8 0 r/w note: * supported only by the h8sx/1655m group. ? h8sx/1655 group bit bit name initial value r/w description 7 to 4 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. ? h8sx/1655m group bit bit name initial value r/w description 7 ? 0 r/w reserved these bits are always read as 0. the write value should always be 0. 6 its14 0 r/w lvd interrupt select enables/disables the lvd interrupt select. 0: disables the lvd interrupt 1: enables the lvd interrupt 5 to 4 ? 0 r/w reserved these bits are always read as 0. the write value should always be 0. 3 its11 0 r/w irq11 pin select selects an input pin for irq11 . 0: selects pin p23 as irq11 -a input 1: selects pin p63 as irq11 -b input section 13 i/o ports rev. 2.00 oct. 20, 2009 page 572 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 its10 0 r/w irq10 pin select selects an input pin for irq10 . 0: selects pin p22 as irq10 -a input 1: selects pin p62 as irq10 -b input 1 its9 0 r/w irq9 pin select selects an input pin for irq9 . 0: selects pin p21 as irq9 -a input 1: selects pin p61 as irq9 -b input 0 its8 0 r/w irq8 pin select selects an input pin for irq8 . 0: selects pin p20 as irq8 -a input 1: selects pin p60 as irq8 -b input section 13 i/o ports rev. 2.00 oct. 20, 2009 page 573 of 1340 rej09b0499-0200 13.3.11 port function control register c (pfcrc) pfcrc selects input pins for irq7 to irq0 . bit bit name initial value r/w 7 its7 0 r/w 6 its6 0 r/w 5 its5 0 r/w 4 its4 0 r/w 3 its3 0 r/w 2 its2 0 r/w 1 its1 0 r/w 0 its0 0 r/w bit bit name initial value r/w description 7 its7 0 r/w irq7 pin select selects an input pin for irq7 . 0: selects pin p17 as irq7 -a input 1: selects pin p57 as irq7 -b input 6 its6 0 r/w irq6 pin select selects an input pin for irq6 . 0: selects pin p16 as irq6 -a input 1: selects pin p56 as irq6 -b input 5 its5 0 r/w irq5 pin select selects an input pin for irq5 . 0: selects pin p15 as irq5 -a input 1: selects pin p55 as irq5 -b input 4 its4 0 r/w irq4 pin select selects an input pin for irq4 . 0: selects pin p14 as irq4 -a input 1: selects pin p54 as irq4 -b input 3 its3 0 r/w irq3 pin select selects an input pin for irq3 . 0: selects pin p13 as irq3 -a input 1: selects pin p53 as irq3 -b input section 13 i/o ports rev. 2.00 oct. 20, 2009 page 574 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 its2 0 r/w irq2 pin select selects an input pin for irq2 . 0: selects pin p12 as irq2 -a input 1: selects pin p52 as irq2 -b input 1 its1 0 r/w irq1 pin select selects an input pin for irq1 . 0: selects pin p11 as irq1 -a input 1: selects pin p51 as irq1 -b input 0 its0 0 r/w irq0 pin select selects an input pin for irq0 . 0: selects pin p10 as irq0 -a input 1: selects pin p50 as irq0 -b input 13.3.12 port function control register d (pfcrd) pfcrd enables/disables the pin functions of ports j and k. bit bit name initial value r/w 7 pcjke * 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w bit bit name initial value r/w description 7 pcjke * 0 r/w ports j and k enable enables/disables ports j and k. 0: ports j and k are disabled 1: ports j and k are enabled 6 to 0 ? 0 r/w reserved these bits are always read as 0 and cannot be modified. the initial values should not be changed. note: * this bit is valid during single-chip mode. the initial value should not be changed except for the single-chip mode. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 575 of 1340 rej09b0499-0200 13.4 usage notes 13.4.1 notes on input buffer control register (icr) setting 1. when the icr setting is changed, the lsi may ma lfunction due to an edge occurred internally according to the pin state. before changing the i cr setting, fix the pin state high or disable the input function corresponding to the pin by the on-chip peripheral module settings. 2. if an input is enabled by setting icr while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs. care must be taken for each module settings for unused input functions. 3. when a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. to use the pin as an output, disable the input function for the pin by setting icr. 13.4.2 notes on port function control register (pfcr) settings 1. port function controller controls the i/o port. before enabling a port function, select the input/output destination. 2. when changing input pins, this lsi may malfunction due to the internal edge generated by the pin level difference before and after the change. ? to change input pins, the following procedure must be performed. a. disable the input function by the corresponding on-chip peripheral module settings b. select another input pin by pfcr c. enable its input function by the corresponding on-chip peripheral module settings 3. if a pin function has both a select bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin func tion by the enable bit. 4. modifying the pcjke bit should be done in the initial setting right after activation. set other bits after setting the pcjke bit. 5. do not change the pcjke bit setting once it is set. section 13 i/o ports rev. 2.00 oct. 20, 2009 page 576 of 1340 rej09b0499-0200 section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 577 of 1340 rej09b0499-0200 section 14 16-bit timer pulse unit (tpu) this lsi has two on-chip 16-bit timer pulse units (tpu), unit 0 and unit 1, and each comprises six channels. therefore, this ls i includes twelve channels. functions of unit 0 and unit 1 are shown in table 14.1 and table 14.2 respectively. block diagrams of unit 0 and unit 1 are shown in figure 14.1 and figure 14.2 respectively. 14.1 features ? maximum 16-pulse input/output ? selection of eight counter input clocks for each channel ? the following operations can be set for each channel: ? waveform output at compare match ? input capture function ? counter clear operation ? synchronous operations: ? multiple timer counters (tcnt) can be written to simultaneously ? simultaneous clearing by compare match and input capture possible ? simultaneous input/output for registers possible by counter synchronous operation ? maximum of 15-phase pwm output possible by combination with synchronous operation ? buffer operation settable for channels 0, 3, 6, and 9 ? phase counting mode settable independently for each of channels 1, 2, 4, 5, 7, 8, 10, and 11 ? cascaded operation ? fast access via internal 16-bit bus ? 26 interrupt sources ? automatic transfer of register data ? programmable pulse generator (ppg) output trigger can be generated ? conversion start trigger for the a/d converter can be generated (unit 0 only) ? module stop state can be set section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 578 of 1340 rej09b0499-0200 table 14.1 tpu (u nit 0) functions item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 count clock p /1 p /4 p /16 p /64 tclka tclkb tclkc tclkd p /1 p /4 p /16 p /64 p /256 tclka tclkb p /1 p /4 p /16 p /64 p /1024 tclka tclkb tclkc p /1 p /4 p /16 p /64 p /256 p /1024 p /4096 tclka p /1 p /4 p /16 p /64 p /1024 tclka tclkc p /1 p /4 p /16 p /64 p /256 tclka tclkc tclkd general registers (tgr) tgra_0 tgrb_0 tgra_1 tgrb_1 tgra_2 tgrb_2 tgra_3 tgrb_3 tgra_4 tgrb_4 tgra_5 tgrb_5 general registers/ buffer registers tgrc_0 tgrd_0 ? ? tgrc_3 tgrd_3 ? ? i/o pins ? ? ? tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output ? ? ? o o o 1 output ? ? ? o o o compare match output toggle output ? ? ? o o o input capture function o o ? o o o synchronous operation o o o o o o pwm mode o o o o o o phase counting mode ? o o ? o o buffer operation o ? ? o ? ? dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture [legend] o : possible ? : not possible section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 579 of 1340 rej09b0499-0200 item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 dmac activation tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match tgra_3 compare match or input capture tgra_4 compare match or input capture tgra_5 compare match or input capture a/d conversion start trigger tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match tgra_3 compare match or input capture tgra_4 compare match or input capture tgra_5 compare match or input capture ppg trigger tgra_0/ tgrb_0 compare match or input capture tgra_1/ tgrb_1 compare match or input capture tgra_2/ tgrb_2 compare match tgra_3/ tgrb_3 compare match or input capture ? ? 5 sources compare match or input capture 0a compare match or input capture 0b compare match or input capture 0c compare match or input capture 0d 4 sources compare match or input capture 1a compare match or input capture 1b 4 sources compare match 2a compare match 2b 5 sources compare match or input capture 3a compare match or input capture 3b compare match or input capture 3c compare match or input capture 3d 4 sources compare match or input capture 4a compare match or input capture 4b 4 sources compare match or input capture 5a compare match or input capture 5b interrupt sources overflow overflow underflow overflow underflow overflow overflow underflow overflow underflow section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 580 of 1340 rej09b0499-0200 table 14.2 tpu (u nit 1) functions item channel 6 channel 7 channel 8 channel 9 channel 10 channel 11 count clock p /1 p /4 p /16 p /64 tclke tclkf tclkg tclkh p /1 p /4 p /16 p /64 p /256 tclke tclkf p /1 p /4 p /16 p /64 p /1024 tclke tclkf tclkg p /1 p /4 p /16 p /64 p /256 p /1024 p /4096 tclke p /1 p /4 p /16 p /64 p /1024 tclke tclkg p /1 p /4 p /16 p /64 p /256 tclke tclkg tclkh general registers (tgr) tgra_6 tgrb_6 tgra_7 tgrb_7 tgra_8 tgrb_8 tgra_9 tgrb_9 tgra_10 tgrb_10 tgra_11 tgrb_11 general registers/ buffer registers tgrc_6 tgrd_6 ? ? tgrc_9 tgrd_9 ? ? i/o pins tioca6 tiocb6 tiocc6 tiocd6 tioca7 tiocb7 tioca8 tiocb8 tioca9 tiocb9 tiocc9 tiocd9 tioca10 tiocb10 tioca11 tiocb11 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output o o o o o o 1 output o o o o o o compare match output toggle output o o o o o o input capture function o o o o o o synchronous operation o o o o o o pwm mode o o o o o o phase counting mode ? o o ? o o buffer operation o ? ? o ? ? dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture [legend] o : possible ? : not possible section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 581 of 1340 rej09b0499-0200 item channel 6 channel 7 channel 8 channel 9 channel 10 channel 11 dmac activation tgra_6 compare match or input capture tgra_7 compare match or input capture tgra_8 compare match or input capture tgra_9 compare match or input capture tgra_10 compare match or input capture tgra_11 compare match or input capture a/d conversion start trigger ? ? ? ? ? ? ppg trigger tgra_6/ tgrb_6 compare match tgra_7/ tgrb_7 compare match tgra_8/ tgrb_8 compare match tgra_9/ tgrb_9 compare match ? ? 5 sources compare match or input capture 6a compare match or input capture 6b compare match or input capture 6c compare match or input capture 6d 4 sources compare match or input capture 7a compare match or input capture 7b 4 sources compare match or input capture 8a compare match or input capture 8b 5 sources compare match or input capture 9a compare match or input capture 9b compare match or input capture 9c compare match or input capture 9d 4 sources compare match or input capture 10a compare match or input capture 10b 4 sources compare match or input capture 11a compare match or input capture 11b interrupt sources overflow overflow underflow overflow underflow overflow overflow underflow overflow underflow section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 582 of 1340 rej09b0499-0200 channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb control logic tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd tsyr tstr input/output pins tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 clock input p /1 p /4 p /16 p /64 p /256 p /1024 p /4096 tclka tclkb tclkc tclkd interrupt request signals channel 3: channel 4: channel 5: interrupt request signals channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal ppg output trigger signal tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: [legend] tstr: timer start register tsyr: timer synchronous register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) tcnt: timer counter channel 2 common channel 5 bus interface figure 14.1 block diagram of tpu (unit 0) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 583 of 1340 rej09b0499-0200 channel 9 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 10 tmdr tsr tcr tior tier tgra tcnt tgrb control logic tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 9 to 11 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 7 tmdr tsr tcr tior tier tgra tcnt tgrb channel 6 tmdr tsr tcr tiorh tier control logic for channels 6 to 8 tgra tcnt tgrb tgrd tsyrb tstrb input/output pins tioca9 tiocb9 tiocc9 tiocd9 tioca10 tiocb10 tioca11 tiocb11 clock input p /1 p /4 p /16 p /64 p /256 p /1024 p /4096 tclke tclkf tclkg tclkh input/output pins tioca6 tiocb6 tiocc6 tiocd6 tioca7 tiocb7 tioca8 tiocb8 interrupt request signals channel 9: channel 10: channel 11: interrupt request signals channel 6: channel 7: channel 8: internal data bus tiorl module data bus tgi9a tgi9b tgi9c tgi9d tci9v tgi10a tgi10b tci10v tci10u tgi11a tgi11b tci11v tci11u tgi6a tgi6b tgi6c tgi6d tci6v tgi7a tgi7b tci7v tci7u tgi8a tgi8b tci8v tci8u channel 9: channel 10: channel 11: internal clock: external clock: channel 6: channel 7: channel 8: [legend] tstrb: timer start register tsyrb: timer synchronous register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) tcnt: timer counter channel 8 common channel 11 bus interface ppg output trigger signal figure 14.2 block diagram of tpu (unit 1) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 584 of 1340 rej09b0499-0200 14.2 input/output pins table 14.3 shows tpu pin configurations. table 14.3 pin configuration unit channel symbol i/o function tclka input external clock a input pin (channel 1 and 5 phase counting mode a phase input) tclkb input external clock b input pin (channel 1 and 5 phase counting mode b phase input) tclkc input external clock c input pin (channel 2 and 4 phase counting mode a phase input) all tclkd input external clock d input pin (channel 2 and 4 phase counting mode b phase input) tioca3 i/o tgra_3 input capture input/output compare output/pwm output pin tiocb3 i/o tgrb_3 input capture input/output compare output/pwm output pin tiocc3 i/o tgrc_3 input capture input/output compare output/pwm output pin 3 tiocd3 i/o tgrd_3 input capture input/output compare output/pwm output pin tioca4 i/o tgra_4 input capture input/output compare output/pwm output pin 4 tiocb4 i/o tgrb_4 input capture input/output compare output/pwm output pin tioca5 i/o tgra_5 input capture input/output compare output/pwm output pin 0 5 tiocb5 i/o tgrb_5 input capture input/output compare output/pwm output pin section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 585 of 1340 rej09b0499-0200 unit channel symbol i/o function tclke input external clock e input pin (channel 7 and 11 phase counting mode a phase input) tclkf input external clock f input pin (channel 7 and 11 phase counting mode b phase input) tclkg input external clock g input pin (channel 8 and 10 phase counting mode a phase input) all tclkh input external clock h input pin (channel 8 and 10 phase counting mode b phase input) tioca6 i/o tgra_6 input capture input/output compare output/pwm output pin tiocb6 i/o tgrb_6 input capture input/output compare output/pwm output pin tiocc6 i/o tgrc_6 input capture input/output compare output/pwm output pin 6 tiocd6 i/o tgrd_6 input capture input/output compare output/pwm output pin tioca7 i/o tgra_7 input capture input/output compare output/pwm output pin 7 tiocb7 i/o tgrb_7 input capture input/output compare output/pwm output pin tioca8 i/o tgra_8 input capture input/output compare output/pwm output pin 8 tiocb8 i/o tgrb_8 input capture input/output compare output/pwm output pin tioca9 i/o tgra_9 input capture input/output compare output/pwm output pin tiocb9 i/o tgrb_9 input capture input/output compare output/pwm output pin tiocc9 i/o tgrc_9 input capture input/output compare output/pwm output pin 9 tiocd9 i/o tgrd_9 input capture input/output compare output/pwm output pin tioca10 i/o tgra_10 input capture input/output compare output/pwm output pin 10 tiocb10 i/o tgrb_10 input capture input/output compare output/pwm output pin tioca11 i/o tgra_11 input capture input/output compare output/pwm output pin 1 11 tiocb11 i/o tgrb_11 input capture input/output compare output/pwm output pin section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 586 of 1340 rej09b0499-0200 14.3 register descriptions the tpu has the following registers in each channel. registers in the unit 0 and unit 1 have the same functions except for each tior and the bit 7 in each tier, namely, the ttge bit in un it 0 and a reserved bit in unit 1. unit 0 ? channel 0 ? timer control register_0 (tcr_0) ? timer mode register_0 (tmdr_0) ? timer i/o control register h_0 (tiorh_0) ? timer i/o control register l_0 (tiorl_0) ? timer interrupt enable register_0 (tier_0) ? timer status register_0 (tsr_0) ? timer counter_0 (tcnt_0) ? timer general register a_0 (tgra_0) ? timer general register b_0 (tgrb_0) ? timer general register c_0 (tgrc_0) ? timer general register d_0 (tgrd_0) ? channel 1 ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register _1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 587 of 1340 rej09b0499-0200 ? channel 2 ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register_2 (tsr_2) ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2) ? channel 3 ? timer control register_3 (tcr_3) ? timer mode register_3 (tmdr_3) ? timer i/o control register h_3 (tiorh_3) ? timer i/o control register l_3 (tiorl_3) ? timer interrupt enable register_3 (tier_3) ? timer status register_3 (tsr_3) ? timer counter_3 (tcnt_3) ? timer general register a_3 (tgra_3) ? timer general register b_3 (tgrb_3) ? timer general register c_3 (tgrc_3) ? timer general register d_3 (tgrd_3) ? channel 4 ? timer control register_4 (tcr_4) ? timer mode register_4 (tmdr_4) ? timer i/o control register _4 (tior_4) ? timer interrupt enable register_4 (tier_4) ? timer status register_4 (tsr_4) ? timer counter_4 (tcnt_4) ? timer general register a_4 (tgra_4) ? timer general register b_4 (tgrb_4) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 588 of 1340 rej09b0499-0200 ? channel 5 ? timer control register_5 (tcr_5) ? timer mode register_5 (tmdr_5) ? timer i/o control register_5 (tior_5) ? timer interrupt enable register_5 (tier_5) ? timer status register_5 (tsr_5) ? timer counter_5 (tcnt_5) ? timer general register a_5 (tgra_5) ? timer general register b_5 (tgrb_5) ? common registers ? timer start register (tstr) ? timer synchronous register (tsyr) unit 1 ? channel 6 ? timer control register_6 (tcr_6) ? timer mode register_6 (tmdr_6) ? timer i/o control register h_6 (tiorh_6) ? timer i/o control register l_6 (tiorl_6) ? timer interrupt enable register_6 (tier_6) ? timer status register_6 (tsr_6) ? timer counter_6 (tcnt_6) ? timer general register a_6 (tgra_6) ? timer general register b_6 (tgrb_6) ? timer general register c_6 (tgrc_6) ? timer general register d_6 (tgrd_6) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 589 of 1340 rej09b0499-0200 ? channel 7 ? timer control register_7 (tcr_7) ? timer mode register_7 (tmdr_7) ? timer i/o control register _7 (tior_7) ? timer interrupt enable register_7 (tier_7) ? timer status register_7 (tsr_7) ? timer counter_7 (tcnt_7) ? timer general register a_7 (tgra_7) ? timer general register b_7 (tgrb_7) ? channel 8 ? timer control register_8 (tcr_8) ? timer mode register_8 (tmdr_8) ? timer i/o control register_8 (tior_8) ? timer interrupt enable register_8 (tier_8) ? timer status register_8 (tsr_8) ? timer counter_8 (tcnt_8) ? timer general register a_8 (tgra_8) ? timer general register b_8 (tgrb_8) ? channel 9 ? timer control register_9 (tcr_9) ? timer mode register_9 (tmdr_9) ? timer i/o control register h_9 (tiorh_9) ? timer i/o control register l_9 (tiorl_9) ? timer interrupt enable register_9 (tier_9) ? timer status register_9 (tsr_9) ? timer counter_9 (tcnt_9) ? timer general register a_9 (tgra_9) ? timer general register b_9 (tgrb_9) ? timer general register c_9 (tgrc_9) ? timer general register d_9 (tgrd_9) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 590 of 1340 rej09b0499-0200 ? channel 10 ? timer control register_10 (tcr_10) ? timer mode register_10 (tmdr_10) ? timer i/o control register _10 (tior_10) ? timer interrupt enable register_10 (tier_10) ? timer status register_10 (tsr_10) ? timer counter_10 (tcnt_10) ? timer general register a_10 (tgra_10) ? timer general register b_10 (tgrb_10) ? channel 11 ? timer control register_11 (tcr_11) ? timer mode register_11 (tmdr_11) ? timer i/o control register_11 (tior_11) ? timer interrupt enable register_11 (tier_11) ? timer status register_11 (tsr_11) ? timer counter_11 (tcnt_11) ? timer general register a_11 (tgra_11) ? timer general register b_11 (tgrb_11) ? common registers ? timer start register (tstrb) ? timer synchronous register (tsyrb) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 591 of 1340 rej09b0499-0200 14.3.1 timer control register (tcr) tcr controls the tcnt operation for each channel. the tpu has a to tal of 12 tcr registers, one for each channel. tcr register settings should be made only while tcnt operation is stopped. 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 2 to 0 these bits select the tcnt counter clearing source. see tables 14.4 and 14.5 for details. 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 1 and 0 these bits select the input clock edge. for details, see table 14.6. when the input clock is counted using both edges, the input clock period is halved (e.g. p /4 both edges = p /2 rising edge). if phase counting mode is used on channels 1, 2, 4, 5, 7, 8, 10, and 11, this setting is ignored and the phase counting mode setting has priority. internal clock edge selection is valid when the input clock is p /4 or slower. this setting is ignored if the input clock is p /1, or when overflow/underflow of another channel is selected. 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w timer prescaler 2 to 0 these bits select the tcnt counter clock. the clock source can be selected independently for each channel. see tables 14.7 to 14.12 for details. to select the external clock as the clock source, the ddr bit and icr bit for the corresponding pin should be set to 0 and 1, respectively. for details, see section 13, i/o ports. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 592 of 1340 rej09b0499-0200 table 14.4 cclr2 to cclr0 (channels 0, 3, 6, and 9) channel bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0 0 0 tcnt clearing disabled 0 0 1 tcnt cleared by tgra compare match/input capture 0 1 0 tcnt cleared by tgrb compare match/input capture 0 1 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 0 1 tcnt cleared by tgrc compare match/input capture * 2 1 1 0 tcnt cleared by tgrd compare match/input capture * 2 0, 3, 6, 9 1 1 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is select ed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer re gister, tcnt is not cleared because the buffer register setting has priority, and comp are match/input capture does not occur. table 14.5 cclr2 to cclr0 (channels 1, 2, 4, 5, 7, 8, 10, and 11) channel bit 7 reserved * 2 bit 6 cclr1 bit 5 cclr0 description 0 0 0 tcnt clearing disabled 0 0 1 tcnt cleared by tgra compare match/input capture 0 1 0 tcnt cleared by tgrb compare match/input capture 1, 2, 4, 5, 7, 8, 10, 11 0 1 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is select ed by setting the sync bit in tsyr to 1. 2. bit 7 is reserved in channels 1, 2, 4, 5, 7, 8, 10, and 11. it is always read as 0 and cannot be modified. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 593 of 1340 rej09b0499-0200 table 14.6 input cl ock edge selection clock edge selection input clock ckeg1 ckeg0 internal clock external clock 0 0 counted at falling edge counted at rising edge 0 1 counted at rising edge counted at falling edge 1 x counted at both edges counted at both edges [legend] x: don't care table 14.7 tpsc2 to tp sc0 (channels 0 and 6) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkb pin input 1 1 0 external clock: counts on tclkc pin input 0, 6 1 1 1 external clock: counts on tclkd pin input section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 594 of 1340 rej09b0499-0200 table 14.8 tpsc2 to tp sc0 (channels 1 and 7) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkb pin input 1 1 0 internal clock: counts on p /256 1, 7 1 1 1 counts on tcnt2 * overflow/underflow notes: this setting is ignored when channel 1 is in phase counting mode. * counts on tcnt8 overflow/underfl ow in the case of tcr_7. table 14.9 tpsc2 to tp sc0 (channels 2 and 8) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkb pin input 1 1 0 external clock: counts on tclkc pin input 2, 8 1 1 1 internal clock: counts on p /1024 note: this setting is ignored when channel 2 is in phase counting mode. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 595 of 1340 rej09b0499-0200 table 14.10 tpsc2 to tp sc0 (channels 3 and 9) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 internal clock: counts on p /1024 1 1 0 internal clock: counts on p /256 3, 9 1 1 1 internal clock: counts on p /4096 table 14.11 tpsc2 to tp sc0 (channels 4 and 10) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkc pin input 1 1 0 internal clock: counts on p /1024 4, 10 1 1 1 counts on tcnt5 * overflow/underflow note: this setting is ignored when channel 4 is in phase counting mode. * counts on tcnt11 overflow/underflow in the case of tcr_10. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 596 of 1340 rej09b0499-0200 table 14.12 tpsc2 to tp sc0 (channels 5 and 11) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkc pin input 1 1 0 internal clock: counts on p /256 5, 11 1 1 1 external clock: counts on tclkd pin input note: this setting is ignored when channel 5 is in phase counting mode. 14.3.2 timer mode register (tmdr) tmdr sets the operating mode for each channel. the tpu has 12 tmdr registers, one for each channel. tmdr register settings should be made only while tcnt operation is stopped. 7 ? 1 ? 6 ? 1 ? 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 md0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 bfb 0 r/w buffer operation b specifies whether tgrb is to normally operate, or tgrb and tgrd are to be used toget her for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output com pare is not generated. in channels 1, 2, 4, 5, 7, 8, 10, and 11, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: tgrb operates normally 1: tgrb and tgrd used together for buffer operation section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 597 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 bfa 0 r/w buffer operation a specifies whether tgra is to normally operate, or tgra and tgrc are to be used toget her for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output com pare is not generated. in channels 1, 2, 4, 5, 7, 8, 10, and 11, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. 0: tgra operates normally 1: tgra and tgrc used together for buffer operation 3 2 1 0 md3 md2 md1 md0 0 0 0 0 r/w r/w r/w r/w modes 3 to 0 set the timer operating mode. md3 is a reserved bit. the write value should always be 0. see table 14.13 for details. table 14.13 md3 to md0 bit 3 md3 * 1 bit 2 md2 * 2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation 0 0 0 1 reserved 0 0 1 0 pwm mode 1 0 0 1 1 pwm mode 2 0 1 0 0 phase counting mode 1 0 1 0 1 phase counting mode 2 0 1 1 0 phase counting mode 3 0 1 1 1 phase counting mode 4 1 x x x ? [legend] x: don't care notes: 1. md3 is a reserved bit. the write value should always be 0. 2. phase counting mode cannot be set for channel s 0, 3, 6, and 9. in this case, 0 should always be written to md2. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 598 of 1340 rej09b0499-0200 14.3.3 timer i/o control register (tior) tior controls tgr. the tpu has 16 tior register s, two each for channels 0, 3, 6 and 9 and one each for channels 1, 2, 4, 5, 7, 8, 10 and 11. care is required si nce tior is affected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. to designate the input capture pin in tior, th e ddr bit and icr bit for the corresponding pin should be set to 0 and 1, respectively. for details, see section 13, i/o ports. ? tiorh_0, tior_1, tior_2, tiorh_3, tior_4, tior_5 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w bit bit name initial value r/w ? tiorl_0, torl_3 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w 0 ioc0 0 r/w bit bit name initial value r/w section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 599 of 1340 rej09b0499-0200 ? tiorh_0, tior_1, tior_2, tiorh_3, tior_4, tior_5 (unit 0) ? tiorh_6, tior_7, tior_8, tiorh_9, tior_10, tior_11 (unit 1) bit bit name initial value r/w description 7 6 5 4 iob3 iob2 iob1 iob0 0 0 0 0 r/w r/w r/w r/w i/o control b3 to b0 specify the function of tgrb. for details, see tables 14. 14, 14.16 to 14.18, 14.20 and 14.21. 3 2 1 0 ioa3 ioa2 ioa1 ioa0 0 0 0 0 r/w r/w r/w r/w i/o control a3 to a0 specify the function of tgra. for details, see tables 14. 22, 14.24 to 14.26, 14.28 and 14.29. ? tiorl_0, tiorl_3 (unit 0) ? tiorl_6, tiorl_9 (unit 1) bit bit name initial value r/w description 7 6 5 4 iod3 iod2 iod1 iod0 0 0 0 0 r/w r/w r/w r/w i/o control d3 to d0 specify the function of tgrd. for details, see tables 14.15, and 14.19. 3 2 1 0 ioc3 ioc2 ioc1 ioc0 0 0 0 0 r/w r/w r/w r/w i/o control c3 to c0 specify the function of tgrc. for details, see tables 14.23, and 14.27. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 600 of 1340 rej09b0499-0200 table 14.14 tiorh_0 (unit 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_0 function tiocb0 pin function * 1 0 0 0 0 output compare register output disabled 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 x ? setting prohibited 1 1 x x input capture register capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down * 2 [legend] x: don't care note: 1. in pwm mode 1, the settings of bits iob3 to iob0 control the tioca0 pin output. 2. when bits tpsc2 to tpsc0 in tcr_1 are set to b'000 and p /1 is used as the tcnt_1 count clock, this setting is inva lid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 601 of 1340 rej09b0499-0200 table 14.15 tiorl_0 (unit 0) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_0 function tiocd0 pin function * 1 0 0 0 0 output compare register * 2 output disabled 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 x ? setting prohibited 1 1 x x input capture register * 2 capture input source is channel 1/count clock input capture at t cnt_1 count-up/count- down * 3 [legend] x: don't care notes: 1. in pwm mode 1, the settings of bi ts iod3 to iod0 control the tiocc0 pin output. 2. when the bfb bit in tmdr_0 is set to 1 and tgrd_0 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 3. when bits tpsc2 to tpsc0 in tcr_1 are set to b'000 and p /1 is used as the tcnt_1 count clock, this setting is inva lid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 602 of 1340 rej09b0499-0200 table 14.16 tior_1 (unit 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_1 function tiocb1 pin function * 0 0 0 0 output compare register output disabled 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 x ? setting prohibited 1 1 x x input capture register tgrc_0 compare match/input capture input capture at generation of tgrc_0 compare match/input capture [legend] x: don't care note: * in pwm mode 1, the settings of bits iob 3 to iob0 control the tioca1 pin output. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 603 of 1340 rej09b0499-0200 table 14.17 tior_2 (unit 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_2 function tiocb2 pin function * 0 0 0 0 output compare register output disabled 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 x 0 0 1 x 0 1 ? setting prohibited 1 x 1 x input capture register capture input source is tiocb2 pin input capture at both edges [legend] x: don't care note: * in pwm mode 1, the settings of bits iob 3 to iob0 control the tioca2 pin output. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 604 of 1340 rej09b0499-0200 table 14.18 tiorh_3 (unit 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_3 function tiocb3 pin function * 1 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb3 pin input capture at rising edge 1 0 0 1 capture input source is tiocb3 pin input capture at falling edge 1 0 1 x capture input source is tiocb3 pin input capture at both edges 1 1 x x input capture register capture input source is channel 4/count clock input capture at tcnt _4 count-up/count-down * 2 [legend] x: don't care notes: 1. in pwm mode 1, the settings of bi ts iob3 to iob0 control the tioca3 pin output. 2. when bits tpsc2 to tpsc0 in tcr_4 are set to b'000 and p /1 is used as the tcnt_4 count clock, this setting is inva lid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 605 of 1340 rej09b0499-0200 table 14.19 tiorl_3 (unit 0) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_3 function tiocd3 pin function * 1 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocd3 pin input capture at rising edge 1 0 0 1 capture input source is tiocd3 pin input capture at falling edge 1 0 1 x capture input source is tiocd3 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 4/count clock input capture at tcnt _4 count-up/count-down * 3 [legend] x: don't care notes: 1. in pwm mode 1, the settings of bi ts iod3 to iod0 control the tiocc3 pin output. 2. when the bfb bit in tmdr_3 is set to 1 and tgrd_3 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 3. when bits tpsc2 to tpsc0 in tcr_4 are set to b'000 and p /1 is used as the tcnt_4 count clock, this setting is inva lid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 606 of 1340 rej09b0499-0200 table 14.20 tior_4 (unit 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_4 function tiocb4 pin function * 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb4 pin input capture at rising edge 1 0 0 1 capture input source is tiocb4 pin input capture at falling edge 1 0 1 x capture input source is tiocb4 pin input capture at both edges 1 1 x x input capture register capture input source is tgrc_3 compare match/input capture input capture at generat ion of tgrc_3 compare match/input capture [legend] x: don't care note: * in pwm mode 1, the settings of bits iob 3 to iob0 control the tioca4 pin output. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 607 of 1340 rej09b0499-0200 table 14.21 tior_5 (unit 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_5 function tiocb5 pin function * 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 capture input source is tiocb5 pin input capture at rising edge 1 x 0 1 capture input source is tiocb5 pin input capture at falling edge 1 x 1 x input capture register capture input source is tiocb5 pin input capture at both edges [legend] x: don't care note: * in pwm mode 1, the settings of bits iob 3 to iob0 control the tioca5 pin output. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 608 of 1340 rej09b0499-0200 table 14.22 tiorh_6 (unit 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_6 function tiocb6 pin function * 1 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb6 pin input capture at rising edge 1 0 0 1 capture input source is tiocb6 pin input capture at falling edge 1 0 1 x capture input source is tiocb6 pin input capture at both edges 1 1 x x input capture register capture input source is channel 7/count clock input capture at tcnt _7 count-up/count-down * 2 [legend] x: don't care notes: 1. in pwm mode 1, the settings of bi ts iob3 to iob0 control the tioca6 pin output. 2. when the bits tpsc2 to tpsc 0 in tcr_7 are set to b'000 and p /1 is used as the count clock of tcnt_7, this setting is in valid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 609 of 1340 rej09b0499-0200 table 14.23 tiorl_6 (unit 1) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_6 function tiocd6 pin function * 1 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocd6 pin input capture at rising edge 1 0 0 1 capture input source is tiocd6 pin input capture at falling edge 1 0 1 x capture input source is tiocd6 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 7/count clock input capture at tcnt _7 count-up/count-down * 3 [legend] x: don't care notes: 1. in pwm mode 1, the settings of bi ts iod3 to iod0 control the tiocc6 pin output. 2. when the bfb bit in tmdr_6 is set to 1 and tgrd_6 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 3. when the bits tpsc2 to tpsc0 in tcr_7 are set to b'000 and p /1 is used as the count clock of tcnt_7, this setting is in valid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 610 of 1340 rej09b0499-0200 table 14.24 tior_7 (unit 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_7 function tiocb7 pin function * 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb7 pin input capture at rising edge 1 0 0 1 capture input source is tiocb7 pin input capture at falling edge 1 0 1 x capture input source is tiocb7 pin input capture at both edges 1 1 x x input capture register tgrc_6 compare match/input capture input capture at generat ion of tgrc_6 compare match/input capture [legend] x: don't care note: * in pwm mode 1, the settings of bits iob 3 to iob0 control the tioca7 pin output. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 611 of 1340 rej09b0499-0200 table 14.25 tior_8 (unit 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_8 function tiocb8 pin function * 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 capture input source is tiocb8 pin input capture at rising edge 1 x 0 1 capture input source is tiocb8 pin input capture at falling edge 1 x 1 x input capture register capture input source is tiocb8 pin input capture at both edges [legend] x: don't care note: * in pwm mode 1, the settings of bits iob 3 to iob0 control the tioca8 pin output. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 612 of 1340 rej09b0499-0200 table 14.26 tiorh_9 (unit 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_9 function tiocb9 pin function * 1 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb9 pin input capture at rising edge 1 0 0 1 capture input source is tiocb9 pin input capture at falling edge 1 0 1 x capture input source is tiocb9 pin input capture at both edges 1 1 x x input capture register capture input source is channel 10/count clock input capture at tcnt _10 count-up/count-down * 2 [legend] x: don't care notes: 1. in pwm mode 1, the settings of bi ts iob3 to iob0 control the tioca9 pin output. 2. when the bits tpsc2 to tpsc 0 in tcr_10 are set to b'000 and p /1 is used as the count clock of tcnt_10, this setting is in valid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 613 of 1340 rej09b0499-0200 table 14.27 tiorl_9 (unit 1) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_9 function tiocd9 pin function * 1 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocd9 pin input capture at rising edge 1 0 0 1 capture input source is tiocd9 pin input capture at falling edge 1 0 1 x capture input source is tiocd9 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 10/count clock input capture at tcnt _10 count-up/count-down * 3 [legend] x: don't care notes: 1. in pwm mode 1, the settings of bi ts iod3 to iod0 control the tiocc9 pin output. 2. when the bfb bit in tmdr_9 is set to 1 and tgrd_9 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 3. when the bits tpsc2 to tpsc 0 in tcr_10 are set to b'000 and p /1 is used as the count clock of tcnt_10, this setting is in valid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 614 of 1340 rej09b0499-0200 table 14.28 tior_10 (unit 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_10 function tiocb10 pin function * 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb10 pin input capture at rising edge 1 0 0 1 capture input source is tiocb10 pin input capture at falling edge 1 0 1 x capture input source is tiocb10 pin input capture at both edges 1 1 x x input capture register capture input source is tgrc_9 compare match/input capture input capture at generat ion of tgrc_9 compare match/input capture [legend] x: don't care note: * in pwm mode 1, the settings of bits iob 3 to iob0 control the tioca10 pin output. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 615 of 1340 rej09b0499-0200 table 14.29 tior_11 (unit 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_11 function tiocb11 pin function * 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 input capture source is tiocb11 pin input capture at rising edge 1 x 0 1 input capture source is tiocb11 pin input capture at falling edge 1 x 1 x input capture register input capture source is tiocb11 pin input capture at both edges [legend] x: don't care note: * in pwm mode 1, the settings of bits iob 3 to iob0 control the tioca11 pin output. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 616 of 1340 rej09b0499-0200 table 14.30 tiorh_0 (unit 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_0 function tioca0 pin function 0 0 0 0 output compare register output disabled 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 x ? setting prohibited 1 1 x x input capture register capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down * [legend] x: don't care note: * when bits tpsc2 to tpsc0 in tcr_1 are set to b'000 and p /1 is used as the tcnt_1 count clock, this setting is inva lid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 617 of 1340 rej09b0499-0200 table 14.31 tiorl_0 (unit 0) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_0 function tiocc0 pin function 0 0 0 0 output compare register * 2 output disabled 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 x ? setting prohibited 1 1 x x input capture register * 2 capture input source is channel 1/count clock input capture at t cnt_1 count-up/count- down * 1 [legend] x: don't care notes: 1. when bits tpsc2 to tpsc0 in tcr_1 are set to b'000 and p /1 is used as the tcnt_1 count clock, this setting is inva lid and input capture is not generated. 2. when the bfa bit in tmdr_0 is set to 1 and tgrc_0 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 618 of 1340 rej09b0499-0200 table 14.32 tior_1 (unit 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_1 function tioca1 pin function 0 0 0 0 output compare register output disabled 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 x ? setting prohibited 1 1 x x input capture register capture input source is tgra_0 compare match/input capture input capture at gener ation of channel 0/tgra_0 compare ma tch/input capture [legend] x: don't care section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 619 of 1340 rej09b0499-0200 table 14.33 tior_2 (unit 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_2 function tioca2 pin function 0 0 0 0 output compare register output disabled 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 x 0 0 1 x 0 1 ? setting prohibited 1 x 1 x input capture register capture input source is tioca2 pin input capture at both edges [legend] x: don't care section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 620 of 1340 rej09b0499-0200 table 14.34 tiorh_3 (unit 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_3 function tioca3 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tioca3 pin input capture at rising edge 1 0 0 1 capture input source is tioca3 pin input capture at falling edge 1 0 1 x capture input source is tioca3 pin input capture at both edges 1 1 x x input capture register capture input source is channel 4/count clock input capture at tcnt _4 count-up/count-down * [legend] x: don't care note: * when bits tpsc2 to tpsc0 in tcr_4 are set to b'000 and p /1 is used as the tcnt_4 count clock, this setting is inva lid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 621 of 1340 rej09b0499-0200 table 14.35 tiorl_3 (unit 0) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_3 function tiocc3 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocc3 pin input capture at rising edge 1 0 0 1 capture input source is tiocc3 pin input capture at falling edge 1 0 1 x capture input source is tiocc3 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 4/count clock input capture at tcnt _4 count-up/count-down * 1 [legend] x: don't care notes: 1. when bits tpsc2 to tpsc0 in tcr_4 are set to b'000 and p /1 is used as the tcnt_4 count clock, this setting is inva lid and input capture is not generated. 2. when the bfa bit in tmdr_3 is set to 1 and tgrc_3 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 622 of 1340 rej09b0499-0200 table 14.36 tior_4 (unit 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_4 function tioca4 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tioca4 pin input capture at rising edge 1 0 0 1 capture input source is tioca4 pin input capture at falling edge 1 0 1 x capture input source is tioca4 pin input capture at both edges 1 1 x x input capture register capture input source is tgrc_3 compare match/input capture input capture at generat ion of tgrc_3 compare match/input capture [legend] x: don't care section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 623 of 1340 rej09b0499-0200 table 14.37 tior_5 (unit 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_5 function tioca5 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 capture input source is tioca5 pin input capture at rising edge 1 x 0 1 capture input source is tioca5 pin input capture at falling edge 1 x 1 x input capture register capture input source is tioca5 pin input capture at both edges [legend] x: don't care section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 624 of 1340 rej09b0499-0200 table 14.38 tiorh_6 (unit 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_6 function tioca6 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 1 capture input source is tioca6 pin input capture at falling edge 1 0 0 0 capture input source is tioca6 pin input capture at rising edge 1 0 1 x capture input source is tioca6 pin input capture at both edges 1 1 x x input capture register capture input source is channel 7/count clock input capture at tcnt _7 count-up/count-down * [legend] x: don't care note: * when the bits tpsc2 to tpsc0 in tcr_7 are set to b'000 and p /1 is used as the count clock of tcnt_7, this setting is in valid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 625 of 1340 rej09b0499-0200 table 14.39 tiorl_6 (unit 1) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_6 function tiocc6 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocc6 pin input capture at rising edge 1 0 0 1 capture input source is tiocc6 pin input capture at falling edge 1 0 1 x capture input source is tiocc6 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 7/count clock input capture at tcnt _7 count-up/count-down * 1 [legend] x: don't care notes: 1. when the bits tpsc2 to tpsc0 in tcr_7 are set to b'000 and p /1 is used as the count clock of tcnt_7, this setting is in valid and input capture is not generated. 2. when the bfa bit in tmdr_6 is set to 1 and tgrc_6 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 626 of 1340 rej09b0499-0200 table 14.40 tior_7 (unit 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_7 function tioca7 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tioca7 pin input capture at rising edge 1 0 0 1 capture input source is tioca7 pin input capture at falling edge 1 0 1 x capture input source is tioca7 pin input capture at both edges 1 1 x x input capture register capture input source is tgra_6 compare match/input capture input capture at generati on of channel 6/tgra_6 compare match/input capture [legend] x: don't care section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 627 of 1340 rej09b0499-0200 table 14.41 tior_8 (unit 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_8 function tioca8 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 capture input source is tioca8 pin input capture at rising edge 1 x 0 1 capture input source is tioca8 pin input capture at falling edge 1 x 1 x input capture register capture input source is tioca8 pin input capture at both edges [legend] x: don't care section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 628 of 1340 rej09b0499-0200 table 14.42 tiorh_9 (unit 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_9 function tioca9 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tioca9 pin input capture at rising edge 1 0 0 1 capture input source is tioca9 pin input capture at falling edge 1 0 1 x capture input source is tioca9 pin input capture at both edges 1 1 x x input capture register capture input source is channel 10/count clock input capture at tcnt _10 count-up/count-down * [legend] x: don't care note: * when the bits tpsc2 to tpsc0 in tcr_10 are set to b'000 and p /1 is used as the count clock of tcnt_10, this setting is in valid and input capture is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 629 of 1340 rej09b0499-0200 table 14.43 tiorl_9 (unit 1) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_9 function tiocc9 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocc9 pin input capture at rising edge 1 0 0 1 capture input source is tiocc9 pin input capture at falling edge 1 0 1 x capture input source is tiocc9 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 10/count clock input capture at tcnt _10 count-up/count-down * 1 [legend] x: don't care notes: 1. when the bits tpsc2 to tpsc0 in tcr_10 are set to b'000 and p /1 is used as the count clock of tcnt_10, this setting is in valid and input capture is not generated. 2. when the bfa bit in tmdr_9 is set to 1 and tgrc_9 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 630 of 1340 rej09b0499-0200 table 14.44 tior_10 (unit 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_10 function tioca10 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tioca10 pin input capture at rising edge 1 0 0 1 capture input source is tioca10 pin input capture at falling edge 1 0 1 x capture input source is tioca10 pin input capture at both edges 1 1 x x input capture register capture input source is tgra_9 compare match/input capture input capture at generat ion of tgra_9 compare match/input capture [legend] x: don't care section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 631 of 1340 rej09b0499-0200 table 14.45 tior_11 (unit 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_11 function tioca11 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 input capture source is tioca11 pin input capture at rising edge 1 x 0 1 input capture source is tioca11 pin input capture at falling edge 1 x 1 x input capture register input capture source is tioca11 pin input capture at both edges [legend] x: don't care section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 632 of 1340 rej09b0499-0200 14.3.4 timer interrupt enable register (tier) tier controls enabling or disabling of interrupt requests for each channel. the tpu has six tier registers, one for each channel. bit bit name initial value r/w 7 ttge * 0 r/w 6 ? 1 ? 5 tcieu 0 r/w 4 tciev 0 r/w 3 tgied 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w 0 tgiea 0 r/w note: * bit 7 in tier of unit 1 is a reserved bit. this bit is always read as 0 and the initial value should not be changed. bit bit name initial value r/w description 7 ttge * 0 r/w a/d conversion start request enable enables/disables generatio n of a/d conversion start requests by tgra input capture/compare match. 0: a/d conversion start request generation disabled 1: a/d conversion start request generation enabled 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcieu 0 r/w underflow interrupt enable enables/disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1, 2, 4, 5, 7, 8, 10, and 11. in channels 0, 3, 6, and 9, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tciu) by tcfu disabled 1: interrupt requests (tciu) by tcfu enabled 4 tciev 0 r/w overflow interrupt enable enables/disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. 0: interrupt requests (tciv) by tcfv disabled 1: interrupt requests (tciv) by tcfv enabled section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 633 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 tgied 0 r/w tgr interrupt enable d enables/disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, 5, 7, 8, 10, and 11, bit 3 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgid ) by tgfd bit disabled 1: interrupt requests (tgid) by tgfd bit enabled 2 tgiec 0 r/w tgr interrupt enable c enables/disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0, 3, 6, and 9. in channels 1, 2, 4, 5, 7, 8, 10, and 11, bit 2 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgic ) by tgfc bit disabled 1: interrupt requests (tgic) by tgfc bit enabled 1 tgieb 0 r/w tgr interrupt enable b enables/disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. 0: interrupt requests (tgib) by tgfb bit disabled 1: interrupt requests (tgib) by tgfb bit enabled 0 tgiea 0 r/w tgr interrupt enable a enables/disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. 0: interrupt requests (tgia) by tgfa bit disabled 1: interrupt requests (tgia) by tgfa bit enabled note: * the bit 7 in tier of unit 1 is a reserved bit this bit is always read as 0 and the initial value should not be changed. 14.3.5 timer status register (tsr) tsr indicates the status of each channel. the tpu has 12 tsr registers, one for each channel. bit bit name initial value r/w 7 tcfd 1 r 6 ? 1 ? 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * 0 tgfa 0 r/(w) * note: * only 0 can be written to bits 5 to 0, to clear flags. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 634 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 tcfd 1 r count direction flag status flag that shows the dire ction in which tcnt counts in channels 1, 2, 4, 5, 7, 8, 10, and 11. in channels 0, 3, 6, and 9, bit 7 is reserved. it is always read as 1 and cannot be modified. 0: tcnt counts down 1: tcnt counts up 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcfu 0 r/(w) * underflow flag status flag that indicates that a tcnt underflow has occurred when channels 1, 2, 4, 5, 7, 8, 10, and 11 are set to phase counting mode. in channels 0, 3, 6, and 9, bit 5 is reserved. it is always read as 0 and cannot be modified. [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) [clearing condition] when a 0 is written to tcfu after reading tcfu = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 4 tcfv 0 r/(w) * overflow flag status flag that indicates that a tcnt overflow has occurred. [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000) [clearing condition] when a 0 is written to tcfv after reading tcfv = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 635 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 tgfd 0 r/(w) * input capture/output compare flag d status flag that indicates the occurrence of tgrd input capture or compare match in channels 0, 3, 6, and 9. in channels 1, 2, 4, 5, 7, 8, 10, and 11, bit 3 is reserved. it is always read as 0 and cannot be modified. [setting conditions] ? when tcnt = tgrd while tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register [clearing conditions] ? when dtc is activated by a tgid interrupt while the disel bit in mrb of dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 2 tgfc 0 r/(w) * input capture/output compare flag c status flag that indicates the occurrence of tgrc input capture or compare match in channels 0, 3, 6, and 9. in channels 1, 2, 4, 5, 7, 8, 10, and 11, bit 2 is reserved. it is always read as 0 and cannot be modified. [setting conditions] ? when tcnt = tgrc while tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register [clearing conditions] ? when dtc is activated by a tgic interrupt while the disel bit in mrb of dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 636 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 tgfb 0 r/(w) * input capture/output compare flag b status flag that indicates t he occurrence of tgrb input capture or compare match. [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing conditions] ? when dtc is activated by a tgib interrupt while the disel bit in mrb of dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 0 tgfa 0 r/(w) * input capture/output compare flag a status flag that indicates t he occurrence of tgra input capture or compare match. [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing conditions] ? when dtc is activated by a tgia interrupt while the disel bit in mrb of dtc is 0 ? when dmac is activated by a tgia interrupt while the dta bit in dmdr of dtc is 1 ? when 0 is written to tgfa after reading tgfa = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) note: * only 0 can be written to clear the flag. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 637 of 1340 rej09b0499-0200 14.3.6 timer counter (tcnt) tcnt is a 16-bit readable/writable counter. the tpu has 12 tcnt counters, one for each channel. tcnt is initialized to h'0000 by a reset or in hardware standby mode. tcnt cannot be accessed in 8-bit units. tcnt must always be accessed in 16-bit units. bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 14.3.7 timer general register (tgr) tgr is a 16-bit readable/writable register with a dual function as output compare and input capture registers. the tpu has 32 tgr registers, four each for channels 0, 3, 6, and 9 and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. tgrc and tgrd for ch annels 0, 3, 6, and 9 can also be designated for operation as buffer register s. the tgr registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. tgr and buffer register combinations during buffer operations are tgra ? tgrc and tgrb ? tgrd. bit bit name initial value r/w 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w bit bit name initial value r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 638 of 1340 rej09b0499-0200 14.3.8 timer start register (tstr) tstr starts or stops operation for channels 0 to 11. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. 7 ? 0 ? 6 ? 0 ? 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w 0 cst0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7, 6 ? all 0 ? reserved the write value should always be 0. 5 4 3 2 1 0 cst5 cst4 cst3 cst2 cst1 cst0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w counter start 5 to 0 these bits select operat ion or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for outpu t, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_5 to tcnt_0 * count operation is stopped. 1: tcnt_5 to tcnt_0 * performs count operation. note: * in the case of unit 1, these bits select operation or stoppage for tcnt_11 to tcnt_6. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 639 of 1340 rej09b0499-0200 14.3.9 timer synchronous register (tsyr) tsyr selects independent operation or synchronous operation for the tcnt counters of channels 0 to 11. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. 7 ? 0 r/w 6 ? 0 r/w 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved the write value should always be 0. 5 4 3 2 1 0 sync5 sync4 sync3 sync2 sync1 sync0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w timer synchronization 5 to 0 these bits select whether oper ation is independent of or synchronized with other channels. when synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit, the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. 0: tcnt_5 to tcnt_0 * operate independently (tcnt presetting/clearing is unrelated to other channels) 1: tcnt_5 to tcnt_0 * perform synchronous operation (tcnt synchronous presetting/synchronous clearing is possible) note: * in the case of unit 1, these bits sele ct independent or synchronous operation for tcnt_11 to tcnt_6. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 640 of 1340 rej09b0499-0200 14.4 operation 14.4.1 basic functions each channel has a tcnt and tgr register. tcnt performs up-counting, an d is also capable of free-running operation, periodic counting, and external event counting. each tgr can be used as an input captur e register or output compare register. (1) counter operation when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counte r, periodic counter, and so on. (a) example of count operati on setting procedure figure 14.3 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 641 of 1340 rej09b0499-0200 (b) free-running count operation an d periodic count operation immediately after a reset, the tpu's tcnt counte rs are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up-count operation as a free-running counter. when tcnt overflows (changes from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 14.4 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 14.4 free-running counter operation when compare match is selected as the tcnt cl earing source, the tcnt co unter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts count-up operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000. figure 14.5 illustrates periodic counter operation. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 642 of 1340 rej09b0499-0200 tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software or dtc activation figure 14.5 periodic counter operation (2) waveform output by compare match the tpu can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) example of setting procedure for wa veform output by compare match figure 14.6 shows an example of the setting procedure for waveform output by a compare match. select waveform output mode output selection set output timing start count section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 643 of 1340 rej09b0499-0200 (b) examples of waveform output operation figure 14.7 shows an example of 0 output/1 output. in this example, tcnt has been designated as a free-running counter, and settings have been made so that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level match, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1-output 0-output figure 14.7 example of 0-output/1-output operation figure 14.8 shows an example of toggle output. in this example, tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle-output toggle-output counter cleared by tgrb compare match figure 14.8 example of toggle output operation section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 644 of 1340 rej09b0499-0200 (3) input capture function the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detection edge. for channels 0, 1, 3, 4, 6, 7, 9, and 10, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. note: when another channel's counter input clock is used as the input capture input for channels 0, 3, 6, and 9, p /1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if p /1 is selected. (a) example of setting procedure for input capture operation figure 14.9 shows an example of the setting procedure for input capture operation. select input capture input input selection start count [1] [2] [1] designate tgr as an input capture register by means of tior, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). [2] set the cst bit in tstr to 1 to start the count operation. figure 14.9 example of setting pr ocedure for input capture operation section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 645 of 1340 rej09b0499-0200 (b) example of input capture operation figure 14.10 shows an example of input capture operation. in this example, both rising and falling edges have been selected as the tioca pin input capture input edge, falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb inpu t capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 14.10 example of input capture operation section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 646 of 1340 rej09b0499-0200 14.4.2 synchronous operation in synchronous operation, the values in multiple tcnt counters can be rewritten simultaneously (synchronous presetting). also, multiple tcnt counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in tcr. synchronous operation enables tgr to be incr emented with respect to a single time base. synchronous operation can be designated for each unit of channels 0 to 5 and 6 to 11. (1) example of synchronous operation setting procedure figure 14.11 shows an example of the synchronous operation setting procedure. synchronous operation selection set tcnt synchronous presetting section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 647 of 1340 rej09b0499-0200 (2) example of synchronous operation figure 14.12 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 3 to 5, tgrb_3 compare match has been set as the channel 3 counter clearing source, and synchronous clearing has been set for the channels 4 and 5 counter clearing source. three-phase pwm waveforms are output from pins tioca3, tioca4, and tioca5. at this time, synchronous presetting and synchronous clearing by tgrb_3 compare match are performed for channel 3 to 5 tcnt counters, and the data set in tgrb_3 is used as the pwm cycle. for details on pwm modes, see section 14.4.5, pwm modes. tcnt_3 to tcnt_5 values h'0000 tioca3 tioca4 tgrb_3 synchronous clearing by tgrb_3 compare match tgra_5 tgra_4 tgrb_5 tgra_3 tgrb_4 tioca5 time figure 14.12 example of synchronous operation section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 648 of 1340 rej09b0499-0200 14.4.3 buffer operation buffer operation, provided for channels 0, 3, 6 and 9, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or a compare match register. table 14.46 shows the register combinations used in buffer operation. table 14.46 register combinat ions in buffer operation channel timer general re gister buffer register tgra_0 tgrc_0 0 tgrb_0 tgrd_0 tgra_3 tgrc_3 3 tgrb_3 tgrd_3 tgra_6 tgrc_6 6 tgrb_6 tgrd_6 tgra_9 tgrc_9 9 tgrb_9 tgrd_9 ? when tgr is an output compare register when a compare match occurs, the value in the bu ffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 14.13. buffer register timer general register tcnt comparator compare match signal figure 14.13 compare match buffer operation section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 649 of 1340 rej09b0499-0200 ? when tgr is an inpu t capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in tgr is transferre d to the buffer register. this operation is illustrated in figure 14.14. buffer register timer general register tcnt input capture signal figure 14.14 input capture buffer operation (1) example of buffer operation setting procedure figure 14.15 shows an example of the buffer operation setting procedure. select tgr function buffer operation set buffer operation start count section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 650 of 1340 rej09b0499-0200 (2) examples of buffer operation (a) when tgr is an output compare register figure 14.16 shows an operation example in which pwm mode 1 has been designated for channel 3, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been set, when compare match a occurs, the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time compare match a occurs. for details on pwm modes, see section 14.4.5, pwm modes. tcnt value tgrb_3 h'0000 tgrc_3 tgra_3 h'0200 h'0520 tioca3 h'0200 h'0450 h'0520 h'0450 tgra_3 h'0450 h'0200 transfer time figure 14.16 example of buffer operation (1) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 651 of 1340 rej09b0499-0200 (b) when tgr is an input capture register figure 14.17 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 14.17 example of buffer operation (2) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 652 of 1340 rej09b0499-0200 14.4.4 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4, 7, or 10) counter clock at overflow/underflow of tcnt_2 (tcnt_5, tcnt_8, or tcnt_11) as set in bits tpsc2 to tpsc0 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 14.47 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. table 14.47 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt_1 tcnt_2 channels 4 and 5 tcnt_4 tcnt_5 channels 7 and 8 tcnt_7 tcnt_8 channels 10 and 11 tcnt_10 tcnt_11 (1) example of cascaded operation setting procedure figure 14.18 shows an example of the setting procedure for cascaded operation. cascaded operation set cascading start count section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 653 of 1340 rej09b0499-0200 (2) examples of cascaded operation figure 14.19 illustrates the operation when counting upon tcnt_5 overflow/underflow has been set for tcnt_4, tgra_4and tgra_5 have been designated as input capture registers, and the tioc pin rising edge has been selected. when a rising edge is input to the tioca4 and tioca5 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to tgra_4, and the lower 16 bits to tgra_5. tcnt_5 clock tcnt_5 h'ffff h'0000 h'0001 tioca4, tioca5 tgra_4 h'03a2 tgra_5 h'0000 tcnt_4 clock tcnt_4 h'03a1 h'03a2 figure 14.19 example of cascaded operation (1) figure 14.20 illustrates the operation when counting upon tcnt_5 overflow/underflow has been set for tcnt_4, and phase counting mode has been designated for channel 5. tcnt_4 is incremented by tcnt_5 overflow and decremented by tcnt_5 underflow. tclkc tcnt_5 fffd tcnt_4 0001 tclkd fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 14.20 example of cascaded operation (2) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 654 of 1340 rej09b0499-0200 14.4.5 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each tgr. settings of tgr registers can output a pwm waveform in the range of 0% to 100% duty cycle. designating tgr compare match as the counter clear ing source enables the cycle to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. 1. pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the outputs specified by bits ioa3 to ioa0 and ioc3 to ioc0 in tior are output from the tioca and tiocc pins at compare matches a and c, respectively. the outputs specified by bits iob3 to iob0 and iod3 to iod0 in tior are output at compare matches b and d, respectively. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, th e output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. 2. pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty cycle registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronou s register compare match, the output value of each pin is the initial value set in tior. if the set values of th e cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 15-phase pwm output is possible by combined use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 14.48. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 655 of 1340 rej09b0499-0200 table 14.48 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 tgra_0 tgrb_0 ? ? tgrc_0 0 tgrd_0 ? ? tgra_1 1 tgrb_1 ? ? tgra_2 2 tgrb_2 ? ? tgra_3 tioca3 tgrb_3 tioca3 tiocb3 tgrc_3 tiocc3 3 tgrd_3 tiocc3 tiocd3 tgra_4 tioca4 4 tgrb_4 tioca4 tiocb4 tgra_5 tioca5 5 tgrb_5 tioca5 tiocb5 tgra_6 tioca6 tgrb_6 tioca6 tiocb6 tgrc_6 tiocc6 6 tgrd_6 tiocc6 tiocd6 tgra_7 tioca7 7 tgrb_7 tioca7 tiocb7 tgra_8 tioca8 8 tgrb_8 tioca8 tiocb8 tgra_9 tioca9 tgrb_9 tioca9 tiocb9 tgrc_9 tiocc9 9 tgrd_9 tiocc9 tiocd9 tgra_10 tioca10 10 tgrb_10 tioca10 tiocb10 section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 656 of 1340 rej09b0499-0200 output pins channel registers pwm mode 1 pwm mode 2 tgra_11 tioca11 11 tgrb_11 tioca11 tiocb11 note: in pwm mode 2, pwm output is not possible fo r the tgr register in which the cycle is set. (1) example of pwm mode setting procedure figure 14.21 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 657 of 1340 rej09b0499-0200 (2) examples of pwm mode operation figure 14.22 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is used as th e cycle, and the value set in tgrb register as the duty cycle. tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 14.22 example of pwm mode operation (1) figure 14.23 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 3 and 4, tgrb_4 compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgra_3 to tgrd_3, tgra_4), to output a 5-phase pwm waveform. in this case, the value set in tgrb_4 is used as the cycle, and the values set in the other tgrs as the duty cycle. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 658 of 1340 rej09b0499-0200 tcnt value tgrb_4 h'0000 tioca3 counter cleared by tgrb_4 compare match time tgra_4 tgrd_3 tgrc_3 tgrb_3 tgra_3 tiocb3 tiocc3 tiocd3 tioca4 figure 14.23 example of pwm mode operation (2) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 659 of 1340 rej09b0499-0200 figure 14.24 shows examples of pwm waveform output with 0% duty cycle and 100% duty cycle in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb changed tgrb changed tgrb changed tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb changed tgrb changed tgrb changed output does not change when compare matches in cycle register and duty register occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb changed tgrb changed tgrb changed output does not change when compare matches in cycle register and duty register occur simultaneously 0% duty figure 14.24 example of pwm mode operation (3) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 660 of 1340 rej09b0499-0200 14.4.6 phase counting mode in phase counting mode, the phase difference betw een two external clock inputs is detected and tcnt is incremented/decremented acco rdingly. this mode can be set fo r channels 1, 2, 4, 5, 7, 8, 10, and 11. when phase counting mode is set, an external cl ock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and input capture/compare match and interrupt functions can be used. this can be used for two-phase encoder pulse input. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag pr ovides an indication of whether tcnt is counting up or down. table 14.49 shows the correspondence between external clock pins and channels. table 14.49 clock input pins in phase counting mode external clock pins channels a-phase b-phase when channel 1, 5, 7, or 11 is set to phase counting mode tclka tclkb when channel 2, 4, 8, or 10 is set to phase counting mode tclkc tclkd section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 661 of 1340 rej09b0499-0200 (1) example of phase counting mode setting procedure figure 14.25 shows an example of the phase counting mode setting procedure. phase counting mode select phase counting mode start count section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 662 of 1340 rej09b0499-0200 (2) examples of phase counting mode operation in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four mode s, according to the count conditions. (a) phase counting mode 1 figure 14.26 shows an example of phase counting mode 1 operation, and table 14.50 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1, 5, 7, and 11) tclkc (channels 2, 4, 8, and 10) tclkb (channels 1, 5, 7, and 11) tclkd (channels 2, 4, 8, and 10) figure 14.26 example of phase counting mode 1 operation table 14.50 up/down-count condit ions in phase counting mode 1 tclka (channels 1, 5, 7, and 11) tclkc (channels 2, 4, 8, and 10) tclkb (channels 1, 5, 7, and 11) tclkd (channels 2, 4, 8, and 10) operation high level low level low level high level up-count high level low level high level low level down-count [legend] : rising edge : falling edge section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 663 of 1340 rej09b0499-0200 (b) phase counting mode 2 figure 14.27 shows an example of phase counting mode 2 operation, and table 14.51 summarizes the tcnt up/down-count conditions. time down-count up-count tcnt value tclka (channels 1, 5, 7, and 11) tclkc (channels 2, 4, 8, and 10) tclkb (channels 1, 5, 7, and 11) tclkd (channels 2, 4, 8, and 10) figure 14.27 example of phase counting mode 2 operation table 14.51 up/down-count condit ions in phase counting mode 2 tclka (channels 1, 5, 7, and 11) tclkc (channels 2, 4, 8, and 10) tclkb (channels 1, 5, 7, and 11) tclkd (channels 2, 4, 8, and 10) operation high level don't care low level don't care low level don't care high level up-count high level don't care low level don't care high level don't care low level down-count [legend] : rising edge : falling edge section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 664 of 1340 rej09b0499-0200 (c) phase counting mode 3 figure 14.28 shows an example of phase counting mode 3 operation, and table 14.52 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channels 1, 5, 7, and 11) tclkc (channels 2, 4, 8, and 10) tclkb (channels 1, 5, 7, and 11) tclkd (channels 2, 4, 8, and 10) figure 14.28 example of phase counting mode 3 operation table 14.52 up/down-count condit ions in phase counting mode 3 tclka (channels 1, 5, 7, and 11) tclkc (channels 2, 4, 8, and 10) tclkb (channels 1, 5, 7, and 11) tclkd (channels 2, 4, 8, and 10) operation high level don't care low level don't care low level don't care high level up-count high level down-count low level don't care high level don't care low level don't care [legend] : rising edge : falling edge section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 665 of 1340 rej09b0499-0200 (d) phase counting mode 4 figure 14.29 shows an example of phase counting mode 4 operation, and table 14.53 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channels 1, 5, 7, and 11) tclkc (channels 2, 4, 8, and 10) tclkb (channels 1, 5, 7, and 11) tclkd (channels 2, 4, 8, and 10) figure 14.29 example of phase counting mode 4 operation table 14.53 up/down-count condit ions in phase counting mode 4 tclka (channels 1, 5, 7, and 11) tclkc (channels 2, 4, 8, and 10) tclkb (channels 1, 5, 7, and 11) tclkd (channels 2, 4, 8, and 10) operation high level low level up-count low level high level don't care high level low level down-count high level low level don't care [legend] : rising edge : falling edge section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 666 of 1340 rej09b0499-0200 (3) phase counting mode application example figure 14.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgrc_0 compare match; tgra_0 and tgrc_0 are used for the compare match function and are set with the speed control cycle and position control cycle. tgrb_0 is used for input capture, with tgrb_0 and tgrd_0 operating in buffer mode. the channel 1 counter input clock is designated as the tgrb_0 input capture source, and the pulse width of 2-phase encoder 4-multiplication pulses is detected. tgra_1 and tgrb_1 for channel 1 are designated for input capture, channel 0 tgra_0 and tgrc_0 compare matches are selected as the in put capture source, and the up/down-counter values for the control cycles are stored. this procedure enables accurate position/speed detection to be achieved. tcnt_1 tcnt_0 channel 1 tgra_1 (speed cycle capture) tgra_0 (speed control cycle) tgrb_1 (position cycle capture) tgrc_0 (position control cycle) tgrb_0 (pulse width capture) tgrd_0 (buffer operation) channel 0 tclka tclkb edge detection circuit + - + - figure 14.30 phase counting mode application example section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 667 of 1340 rej09b0499-0200 14.5 interrupt sources there are three kinds of tpu interrupt sources: tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cancelled by clearing the status flag to 0. relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. for details, see section 7, interrupt controller. table 14.54 lists the tpu interrupt sources. table 14.54 tpu interrupts channel name interrupt source interrupt flag dtc activation dmac activation 0 tgi0a tgra_0 input capture/com pare match tgfa_0 possible possible tgi0b tgrb_0 input capture/compar e match tgfb_0 possi ble not possible tgi0c tgrc_0 input capture/compar e match tgfc_0 possible not possible tgi0d tgrd_0 input capture/compar e match tgfd_0 possible not possible tci0v tcnt_0 overflow tcfv _0 not possible not possible 1 tgi1a tgra_1 input capture/com pare match tgfa_1 possible possible tgi1b tgrb_1 input capture/compar e match tgfb_1 possi ble not possible tci1v tcnt_1 overflow tcfv _1 not possible not possible tci1u tcnt_1 underflow tcfu _1 not possible not possible 2 tgi2a tgra_2 compare matc h tgfa_2 possible possible tgi2b tgrb_2 compare match tgfb_2 possible not possible tci2v tcnt_2 overflow tcfv _2 not possible not possible tci2u tcnt_2 underflow tcfu _2 not possible not possible section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 668 of 1340 rej09b0499-0200 channel name interrupt source interrupt flag dtc activation dmac activation 3 tgi3a tgra_3 input capture/com pare match tgfa_3 possible possible tgi3b tgrb_3 input capture/compar e match tgfb_3 possi ble not possible tgi3c tgrc_3 input capture/compar e match tgfc_3 possible not possible tgi3d tgrd_3 input capture/compar e match tgfd_3 possible not possible tci3v tcnt_3 overflow tcfv _3 not possible not possible 4 tgi4a tgra_4 input capture/com pare match tgfa_4 possible possible tgi4b tgrb_4 input capture/compar e match tgfb_4 possi ble not possible tci4v tcnt_4 overflow tcfv _4 not possible not possible tci4u tcnt_4 underflow tcfu _4 not possible not possible 5 tgi5a tgra_5 input capture/com pare match tgfa_5 possible possible tgi5b tgrb_5 input capture/compar e match tgfb_5 possi ble not possible tci5v tcnt_5 overflow tcfv _5 not possible not possible tci5u tcnt_5 underflow tcfu _5 not possible not possible 6 tgi6a tgra_6 input capture/com pare match tgfa_6 possible possible tgi6b tgrb_6 input capture/compar e match tgfb_6 possi ble not possible tgi6c tcrc_6 input capture/compar e match tgfc_6 possi ble not possible tgi6d tcrd_6 input capture/compar e match tgfd_6 possi ble not possible 7 tgi7a tgra_7 input capture/com pare match tgfa_7 possible possible tgi7b tgrb_7 input capture/compar e match tgfb_7 possi ble not possible tci7v tcnt_7 overflow tcfv _7 not possible not possible tci7u tcnt_7 underflow tcfu _7 not possible not possible 8 tgi8a tgra_8 input capture/com pare match tgfa_8 possible possible tgi8b tgrb_8 input capture/compar e match tgfb_8 possi ble not possible tci8v tcnt_8 overflow tcfv _8 not possible not possible tci8u tcnt_8 underflow tcfu _8 not possible not possible 9 tgi9a tgra_9 input capture/com pare match tgfa_9 possible possible tgi9b tgrb_9 input capture/compar e match tgfb_9 possi ble not possible tgi9c tgrc_9 input capture/compar e match tgfc_9 possible not possible tgi9d tgrd_9 input capture/compar e match tgfd_9 possible not possible tci9v tcnt_9 overflow tcfv _9 not possible not possible section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 669 of 1340 rej09b0499-0200 channel name interrupt source interrupt flag dtc activation dmac activation 10 tgi10a tgra_10 input capture/comp are match tgfa_10 possible possible tgi10b tgrb_10 input capture/compar e match tgfb_10 possi ble not possible tci10v tcnt_10 overflow tcfv _10 not possible not possible tci10u tcnt_10 underflow tcfu _10 not possible not possible 11 tgi11a tgra_11 input capture/comp are match tgfa_11 possible possible tgi11b tgrb_11 input capture/compar e match tgfb_11 possi ble not possible tci11v tcnt_11 overflow tcfv _11 not possible not possible tci11u tcnt_11 underflow tcfu _11 not possible not possible note: this table shows the initial state immediat ely after a reset. the relative channel priority levels can be changed by the interrupt controller. (1) input capture/compar e match interrupt an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a chan nel. the interrupt request is cancelled by clearing the tgf flag to 0. the tpu has 32 input capture/compare match interrupts, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. (2) overflow interrupt an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of a tcnt overflow on a channel. the interrupt request is cancelled by clearing the tcfv flag to 0. the tpu has s12 overflow interrupts, one for each channel. (3) underflow interrupt an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of a tcnt underflow on a channel. the interrupt request is cancelled by clearing the tcfu flag to 0. the tpu has eight un derflow interrupts, one each for channels 1, 2, 4, 5, 7, 8, 10, and 11. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 670 of 1340 rej09b0499-0200 14.6 dtc activation the dtc can be activated by the tgr input capture /compare match interrupt for a channel. for details, see section 12, data transfer controller (dtc). a total of 32 tpu input capture/compare match in terrupts can be used as dtc activation sources, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. 14.7 dmac activation the dmac can be activated by the tgra input capture/compare match in terrupt for a channel. for details, see section 10, dma controller (dmac). in tpu, one in each channel, totally 12 tgra i nput capture/compare match interrupts can be used as dmac activation sources. 14.8 a/d converter activation concerning the unit 0 in tpu, the tgra inpu t capture/compare match for each channel can activate the a/d converter. (however, the a/d converter cannot be act ivated in unit 1.) if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to start a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. in the tpu, a total of six tgra input capture/c ompare match interrupts can be used as a/d converter conversion start sources, on e for each channel of unit 0. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 671 of 1340 rej09b0499-0200 14.9 operation timing 14.9.1 input/output timing (1) tcnt count timing figure 14.31 shows tcnt count timing in internal clock operation, and figure 14.32 shows tcnt count timing in external clock operation. p internal clock tcnt input clock tcnt falling edge rising edge n ? 1n + 1n + 2 n falling edge figure 14.31 count timing in internal clock operation p external clock tcnt input clock tcnt falling edge rising edge n ? 1n + 1n + 2 n falling edge figure 14.32 count timing in external clock operation section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 672 of 1340 rej09b0499-0200 (2) output compare output timing a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin (tioc pin). after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 14.33 shows output compare output timing. p tcnt input clock tcnt n + 1 n compare match signal tioc pin tgr n figure 14.33 output compare output timing (3) input capture signal timing figure 14.34 shows input capture signal timing. p tcnt n + 1 n tgr input capture input input capture signal n + 2 n n + 2 figure 14.34 input capture input signal timing section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 673 of 1340 rej09b0499-0200 (4) timing for counter clearing by compare match/input capture figure 14.35 shows the timing when counter clear ing by compare match o ccurrence is specified, and figure 14.36 shows the timing when counter clearing by input capture occurrence is specified. p tcnt n tgr compare match signal counter clear signal h'0000 n figure 14.35 counter clea r timing (compare match) tgr counter clear signal h'0000 p tcnt n input capture signal n figure 14.36 counter clea r timing (input capture) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 674 of 1340 rej09b0499-0200 (5) buffer operation timing figures 14.37 and 14.38 show the timings in buffer operation. p n + 1 n tgra, tgrb tgrc, tgrd n n compare match signal tcnt n figure 14.37 buffer operat ion timing (compare match) p tcnt n + 1 n input capture signal tgra, tgrb tgrc, tgrd n n + 1 n nn figure 14.38 buffer operat ion timing (input capture) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 675 of 1340 rej09b0499-0200 14.9.2 interrupt signal timing (1) tgf flag setting timing in case of compare match figure 14.39 shows the timing for setting of the tgf flag in tsr by compare match occurrence, and the tgi interrupt request signal timing. tgr compare match signal p tcnt input clock tcnt n + 1 n n tgf flag tgi interrupt figure 14.39 tgi interrupt timing (compare match) (2) tgf flag setting timing in case of input capture figure 14.40 shows the timing for setting of the tgf flag in tsr by input capture occurrence, and the tgi interrupt request signal timing. tgr p tcnt n input capture signal tgf flag tgi interrupt n figure 14.40 tgi interrupt timing (input capture) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 676 of 1340 rej09b0499-0200 (3) tcfv flag/tcfu flag setting timing figure 14.41 shows the timing for setting of the tcfv flag in tsr by overflow occurrence, and the tciv interrupt request signal timing. figure 14.42 shows the timing for setting of the tcfu flag in tsr by underflow occurrence, and the tciu interrupt request signal timing. h'ffff p tcnt input clock tcnt (overflow) overflow signal tcfv flag tciv interrupt h'0000 figure 14.41 tciv in terrupt setting timing h'0000 p tcnt input clock tcnt (underflow) underflow signal tcfu flag tciu interrupt h'ffff figure 14.42 tciu in terrupt setting timing section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 677 of 1340 rej09b0499-0200 (4) status flag clearing timing after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc or dmac is activated, the flag is cl eared automatically. figure 14.43 shows the timing for status flag clearing by the cpu, and figures 14.44 and 14.45 show the timing for status flag clearing by the dtc or dmac. status flag p interrupt request signal address write t 1 t 2 tsr address tsr write cycle figure 14.43 timing for st atus flag clearing by cpu the status flag and interrupt request sign al are cleared in sy nchronization with p after the dtc or dmac transfer has started, as shown in figure 14.44. if conflict occurs for clearing the status flag and interrupt request signal due to activation of mu ltiple dtc or dmac transfers, it will take up to five clock cycles (p ) for clearing them, as show n in figure 14.45. the next transfer request is masked for a longer period of either a period un til the current transfer ends or a period for five clock cycles (p ) from the beginning of the transfer. note th at in the dtc transfer, the status flag may be cleared during outputting the destination address. section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 678 of 1340 rej09b0499-0200 p address status flag interrupt request signal source address destination address period in which the next transfer request is masked t 1 t 2 dtc/dmac read cycle dtc/dmac write cycle t 1 t 2 figure 14.44 timing for status flag clearing by dtc/dmac activation (1) p address status flag interrupt request signal source address destination address period of flag clearing period of interrupt request signal clearing period in which the next transfer request is masked dtc/dmac read cycle dtc/dmac write cycle figure 14.45 timing for status flag clearing by dtc/dmac activation (2) section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 679 of 1340 rej09b0499-0200 14.10 usage notes 14.10.1 module stop function setting operation of the tpu can be disabled or enabled using the module stop control register. the initial setting is for operation of the tpu to be halted. register access is enabled by clearing module stop state. for details, see sec tion 27, power-down modes. 14.10.2 input clock restrictions the input clock pulse width must be at least 1.5 st ates in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. the tpu will not operate properly with a narrower pulse width. in phase counting mode, the phase difference and ove rlap between the two inpu t clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 14.46 shows the input clock conditions in phase counting mode. tclka (tclkc) tclkb (tclkd) overlap phase difference pulse width note: phase difference, overlap 1.5 states pulse width 2.5 states pulse width phase difference overlap pulse width pulse width figure 14.46 phase difference, overlap, and pulse width in phase counting mode section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 680 of 1340 rej09b0499-0200 14.10.3 caution on cycle setting when counter clearing by compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = p (n + 1) f: p : n: counter frequency operating frequency tgr set value 14.10.4 conflict between tcnt write and clear operations if the counter-clearing signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 14.47 shows the timing in this case. counter clear signal h'0000 p tcnt n address write t 1 t 2 tcnt address tcnt write cycle figure 14.47 conflict between tc nt write and clear operations section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 681 of 1340 rej09b0499-0200 14.10.5 conflict between tcnt write and increment operations if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 14 .48 shows the timing in this case. p tcnt input clock tcnt n address write t 1 t 2 tcnt write cycle m tcnt write data tcnt address figure 14.48 conflict between tcnt write and increment operations 14.10.6 conflict between tgr write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is disabled. a compare match also does not occur when the same value as before is written. figure 14.49 shows the timing in this case. tgr compare match signal p tcnt n + 1 n address write t 1 t 2 m tgr address tgr write cycle n disabled tgr write data figure 14.49 conflict between tgr write and compare match section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 682 of 1340 rej09b0499-0200 14.10.7 conflict between buffer regist er write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the data transferred to tgr by the buffer operation will be the write data. figure 14.50 shows the timing in this case. tgr compare match signal p n address write t 1 t 2 m tgr write cycle buffer register address data written to buffer register m buffer register figure 14.50 conflict between bu ffer register write and compare match 14.10.8 conflict between tgr read and input capture if the input capture signal is generated in the t1 st ate of a tgr read cycle, the data that is read will be the data after input capture transfer. figure 14.51 shows the timing in this case. tgr p input capture signal address tgr address read t 1 t 2 tgr read cycle xm m internal data bus figure 14.51 conflict between tgr read and input capture section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 683 of 1340 rej09b0499-0200 14.10.9 conflict between tgr write and input capture if the input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the wr ite to tgr is not performed. figure 14.52 shows the timing in this case. tcnt p input capture signal address tgr address write t 1 t 2 tgr write cycle m m tgr figure 14.52 conflict between tgr write and input capture section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 684 of 1340 rej09b0499-0200 14.10.10 conflict between buffer regist er write and input capture if the input capture signal is generated in the t2 st ate of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 14.53 shows the timing in this case. tcnt p input capture signal address buffer register address write t 1 t 2 buffer register write cycle n n tgr buffer register m m figure 14.53 conflict between buff er register write a nd input capture section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 685 of 1340 rej09b0499-0200 14.10.11 conflict between overflow/unde rflow and counter clearing if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 14.54 shows the operation timing when a tgr compare match is sp ecified as the clearing source, and h'ffff is set in tgr. counter clear signal h'0000 p tcnt input clock tcnt tgf flag tcfv flag h'ffff disabled figure 14.54 conflict between overflow and coun ter clearing 14.10.12 conflict between tcnt writ e and overflow/underflow if an overflow/underflow occurs due to incremen t/decrement in the t2 state of a tcnt write cycle, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set. figure 14.55 shows the operation timing when there is conflict between tcnt write and overflow. p tcnt h'ffff tcfv flag address write tcnt address m tcnt write data t 1 t 2 tgr write cycle figure 14.55 conflict between tcnt write and overflow section 14 16-bit timer pulse unit (tpu) rev. 2.00 oct. 20, 2009 page 686 of 1340 rej09b0499-0200 14.10.13 interrupts and modu le stop mode if module stop state is entered when an interrupt ha s been requested, it will not be possible to clear the cpu interrupt source or the dtc and dmac activation sources. interrupts should therefore be disabled before entering module stop state. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 687 of 1340 rej09b0499-0200 section 15 programmable pulse generator (ppg) the programmable pulse generator (ppg) provides pulse outputs by using the 16-bit timer pulse unit (tpu) as a time base. the ppg pulse outputs are divided into 4-bit groups (groups 7 to 4 and 1 to 0) that can operate both simultaneously and independently. figures 15.1 and 15.2 show a block diagram of the ppg. table 15.1 shows a list of ppg functions. 15.1 features ? 28-bit output data ? four output groups ? selectable output trigger signals ? non-overlapping mode ? can operate together with the data transfer controller (dtc) and dma controller (dmac) ? inverted output can be set ? module stop state specifiable table 15.1 list of ppg functions function ppg0 ppg1 compare match possible not possible tpu0 input capture possible not possible compare match not possible possible ppg output trigger tpu1 input capture not possible not possible non-overlapping mode possible possible dtc possible possible output data transfer dmac possible possible inverted output possible possible section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 688 of 1340 rej09b0499-0200 compare match signals po7 po6 po5 po4 po3 po2 po1 po0 [legend] pmr: pcr: nderh: nderl: ppg output mode register ppg output control register next data enable register h next data enable register l ndrh: ndrl: podrh: podrl: next data register h next data register l output data register h output data register l internal data bus pulse output pins, group 1 pulse output pins, group 0 podrh podrl ndrh ndrl control logic nderh pmr nderl pcr figure 15.1 block diagram of ppg (unit 0) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 689 of 1340 rej09b0499-0200 compare match signals po31 po30 po29 po28 po27 po26 po25 po24 po23 po22 po21 po20 po19 po18 po17 po16 [legend] pmr_1: pcr_1: nderh_1: nderl_1: ppg output mode register_1 ppg output control register_1 next data enable register h_1 next data enable register l_1 ndrh_1: ndrl_1: podrh_1: podrl_1: next data register h_1 next data register l_1 output data register h_1 output data register l_1 internal data bus pulse output pins, group 7 pulse output pins, group 6 pulse output pins, group 5 pulse output pins, group 4 podrh_1 podrl_1 ndrh_1 ndrl_1 control logic nderh_1 pmr_1 nderl_1 pcr_1 figure 15.2 block diagram of ppg (unit 1) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 690 of 1340 rej09b0499-0200 15.2 input/output pins table 15.2 shows the ppg pin configuration. table 15.2 pin configuration unit pin name i/o function po0 output po1 output po2 output po3 output group 0 pulse output po4 output po5 output po6 output 0 po7 output group 1 pulse output po16 output po17 output po18 output po19 output group 4 pulse output po20 output po21 output po22 output po23 output group 5 pulse output po24 output po25 output po26 output po27 output group 6 pulse output po28 output po29 output po30 output 1 po31 output group 7 pulse output section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 691 of 1340 rej09b0499-0200 15.3 register descriptions the ppg has the following registers. unit 0: ? next data enable register h (nderh) ? next data enable register l (nderl) ? output data register h (podrh) ? output data register l (podrl) ? next data register h (ndrh) ? next data register l (ndrl) ? ppg output control register (pcr) ? ppg output mode register (pmr) unit 1: ? next data enable register h_1 (nderh_1) ? next data enable register l_1 (nderl_1) ? output data register h_1 (podrh_1) ? output data register l_1 (podrl_1) ? next data register h_1 (ndrh_1) ? next data register l_1 (ndrl_1) ? ppg output control register_1 (pcr_1) ? ppg output mode register_1 (pmr_1) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 692 of 1340 rej09b0499-0200 15.3.1 next data enable registers h, l (nderh, nderl) nderh and nderl enable/disable pulse output on a bit-by-bit basis. ? nderh 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w 0 nder8 0 r/w bit bit name initial value r/w ? nderl 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w 0 nder0 0 r/w bit bit name initial value r/w ? nderh bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 15 to 8 these are read-only bits and cannot be modified. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 693 of 1340 rej09b0499-0200 ? nderl bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 7 to 0 when a bit is set to 1, the value in the corresponding ndrl bit is transferred to the podrl bit by the selected output trigger. values are not transferred from ndrl to podrl for cleared bits. ? nderh_1 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder31 nder30 nder29 nder28 nder27 nder26 nder25 nder24 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 31 to 24 when a bit is set to 1, the value in the corresponding ndrh_1 bit is transferred to the podrh_1 bit by the selected output trigger. values are not transferred from ndrh_1 to podrh_1 for cleared bits. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 694 of 1340 rej09b0499-0200 ? nderl_1 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder23 nder22 nder21 nder20 nder19 nder18 nder17 nder16 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 23 to 16 when a bit is set to 1, the value in the corresponding ndrl_1 bit is transferred to the podrl_1 bit by the selected output trigger. values are not transferred from ndrl_1 to podrl_1 for cleared bits. 15.3.2 output data registers h, l (podrh, podrl) podrh and podrl store output data for use in pulse output. a bit that has been set for pulse output by nder is read-only and cannot be modified. ? podrh 7 pod15 0 r/w 6 pod14 0 r/w 5 pod13 0 r/w 4 pod12 0 r/w 3 pod11 0 r/w 2 pod10 0 r/w 1 pod9 0 r/w 0 pod8 0 r/w bit bit name initial value r/w ? podrl 7 pod7 0 r/w 6 pod6 0 r/w 5 pod5 0 r/w 4 pod4 0 r/w 3 pod3 0 r/w 2 pod2 0 r/w 1 pod1 0 r/w 0 pod0 0 r/w bit bit name initial value r/w section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 695 of 1340 rej09b0499-0200 ? podrh bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 15 to 8 these are read-only bits and cannot be modified. ? podrl bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 7 to 0 for bits which have been set to pulse output by nderl, the output trigger transfers ndrl values to this register during ppg operation. while nderl is set to 1, the cpu cannot write to this register. while nderl is cleared, the initial output value of the pulse can be set. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 696 of 1340 rej09b0499-0200 ? podrh_1 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod31 pod30 pod29 pod28 pod27 pod26 pod25 pod24 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 31 to 24 for bits which have been set to pulse output by nderh_1, the output trigger transfers ndrh_1 values to this register during ppg operation. while nderh_1 is set to 1, the cpu cannot write to this register. while nderh_1 is cleared, the initial output value of the pulse can be set. ? podrl_1 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod23 pod22 pod21 pod20 pod19 pod18 pod17 pod16 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 23 to 16 for bits which have been set to pulse output by nderl_1, the output trigger transfers ndrl_1 values to this register during ppg operation. while nderl_1 is set to 1, the cpu cannot write to this register. while nderl_1 is cleared, the initial output value of the pulse can be set. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 697 of 1340 rej09b0499-0200 15.3.3 next data registers h, l (ndrh, ndrl) ndrh and ndrl store the next data for pulse output. the ndr addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. ? ndrh bit bit name initial value r/w 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 0 r/w ? ndrl bit bit name initial value r/w 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 0 r/w ? ndrh if pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 15 to 8 these are read-only bits and cannot be modified. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 698 of 1340 rej09b0499-0200 ? ndrl if pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 7 to 0 the register contents ar e transferred to the corresponding podrl bits by the output trigger specified with pcr. if pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. bit bit name initial value r/w description 7 6 5 4 ndr7 ndr6 ndr5 ndr4 0 0 0 0 r/w r/w r/w r/w next data register 7 to 4 the register contents ar e transferred to the corresponding podrl bits by the output trigger specified with pcr. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ndr3 ndr2 ndr1 ndr0 0 0 0 0 r/w r/w r/w r/w next data register 3 to 0 the register contents ar e transferred to the corresponding podrl bits by the output trigger specified with pcr. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 699 of 1340 rej09b0499-0200 ? ndrh_1 if pulse output groups 6 and 7 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr31 ndr30 ndr29 ndr28 ndr27 ndr26 ndr25 ndr24 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 31 to 24 the register contents ar e transferred to the corresponding podrh_1 bits by the output trigger specified with pcr_1. if pulse output groups 6 and 7 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. bit bit name initial value r/w description 7 6 5 4 ndr31 ndr30 ndr29 ndr28 0 0 0 0 r/w r/w r/w r/w next data register 31 to 28 the register contents ar e transferred to the corresponding podrh_1 bits by the output trigger specified with pcr_1. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ndr27 ndr26 ndr25 ndr24 0 0 0 0 r/w r/w r/w r/w next data register 27 to 24 the register contents ar e transferred to the corresponding podrh_1 bits by the output trigger specified with pcr_1. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 700 of 1340 rej09b0499-0200 ? ndrl_1 if pulse output groups 4 and 5 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr23 ndr22 ndr21 ndr20 ndr19 ndr18 ndr17 ndr16 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 23 to 16 the register contents ar e transferred to the corresponding podrl_1 bits by the output trigger specified with pcr_1. if pulse output groups 4 and 5 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. bit bit name initial value r/w description 7 6 5 4 ndr23 ndr22 ndr21 ndr20 0 0 0 0 r/w r/w r/w r/w next data register 23 to 20 the register contents ar e transferred to the corresponding podrl_1 bits by the output trigger specified with pcr_1. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ndr19 ndr18 ndr17 ndr16 0 0 0 0 r/w r/w r/w r/w next data register 19 to 16 the register contents ar e transferred to the corresponding podrl_1 bits by the output trigger specified with pcr_1. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 701 of 1340 rej09b0499-0200 15.3.4 ppg output control register (pcr) pcr selects output trigger signals on a group-by-group basis. for details on output trigger selection, refer to section 15.3.5, ppg output mode register (pmr). 7 g3cms1 1 r/w 6 g3cms0 1 r/w 5 g2cms1 1 r/w 4 g2cms0 1 r/w 3 g1cms1 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w 0 g0cms0 1 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 g3cms1 g3cms0 1 1 r/w r/w group 3 compare match select 1 and 0 these are read-only bits and cannot be modified. 5 4 g2cms1 g2cms0 1 1 r/w r/w group 2 compare match select 1 and 0 these are read-only bits and cannot be modified. 3 2 g1cms1 g1cms0 1 1 r/w r/w group 1 compare match select 1 and 0 these bits select output tri gger of pulse output group 1. 00: compare match in tpu channel 0 01: compare match in tpu channel 1 10: compare match in tpu channel 2 11: compare match in tpu channel 3 1 0 g0cms1 g0cms0 1 1 r/w r/w group 0 compare match select 1 and 0 these bits select output tri gger of pulse output group 0. 00: compare match in tpu channel 0 01: compare match in tpu channel 1 10: compare match in tpu channel 2 11: compare match in tpu channel 3 section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 702 of 1340 rej09b0499-0200 ? pcr_1 bit bit name initial value r/w description 7 6 g3cms1 g3cms0 1 1 r/w r/w group 7 compare match select 1 and 0 these bits select output tri gger of pulse output group 7. 00: compare match in tpu channel 6 01: compare match in tpu channel 7 10: compare match in tpu channel 8 11: compare match in tpu channel 9 5 4 g2cms1 g2cms0 1 1 r/w r/w group 6 compare match select 1 and 0 these bits select output tri gger of pulse output group 6. 00: compare match in tpu channel 6 01: compare match in tpu channel 7 10: compare match in tpu channel 8 11: compare match in tpu channel 9 3 2 g1cms1 g1cms0 1 1 r/w r/w group 5 compare match select 1 and 0 these bits select output tri gger of pulse output group 5. 00: compare match in tpu channel 6 01: compare match in tpu channel 7 10: compare match in tpu channel 8 11: compare match in tpu channel 9 1 0 g0cms1 g0cms0 1 1 r/w r/w group 4 compare match select 1 and 0 these bits select output tri gger of pulse output group 4. 00: compare match in tpu channel 6 01: compare match in tpu channel 7 10: compare match in tpu channel 8 11: compare match in tpu channel 9 section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 703 of 1340 rej09b0499-0200 15.3.5 ppg output mode register (pmr) pmr selects the pulse output mode of the ppg for each group. if inverted output is selected, a low-level pulse is output when podrh is 1 and a high-level pulse is output when podrh is 0. if non-overlapping operation is selected, ppg updates its output values at compare match a or b of the tpu that becomes the output trigger. for details, refer to section 15.4.4, non-overlapping pulse output. 7 g3inv 1 r/w 6 g2inv 1 r/w 5 g1inv 1 r/w 4 g0inv 1 r/w 3 g3nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w 0 g0nov 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 g3inv 1 r/w group 3 inversion these are read-only bits and cannot be modified. 6 g2inv 1 r/w group 2 inversion these are read-only bits and cannot be modified. 5 g1inv 1 r/w group 1 inversion selects direct output or inve rted output for pulse output group 1. 0: inverted output 1: direct output 4 g0inv 1 r/w group 0 inversion selects direct output or inve rted output for pulse output group 0. 0: inverted output 1: direct output section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 704 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 g3nov 0 r/w group 3 non-overlap these are read-only bits and cannot be modified. 2 g2nov 0 r/w group 2 non-overlap these are read-only bits and cannot be modified. 1 g1nov 0 r/w group 1 non-overlap selects normal or non-overlapping operation for pulse output group 1. 0: normal operation (output values updated at compare match a in the selected tpu channel) 1: non-overlapping operation (output values updated at compare match a or b in the selected tpu channel) 0 g0nov 0 r/w group 0 non-overlap selects normal or non-overlapping operation for pulse output group 0. 0: normal operation (output values updated at compare match a in the selected tpu channel) 1: non-overlapping operation (output values updated at compare match a or b in the selected tpu channel) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 705 of 1340 rej09b0499-0200 ? pmr_1 bit bit name initial value r/w description 7 g3inv 1 r/w group 7 inversion selects direct output or inve rted output for pulse output group 7. 0: inverted output 1: direct output 6 g2inv 1 r/w group 6 inversion selects direct output or inve rted output for pulse output group 6. 0: inverted output 1: direct output 5 g1inv 1 r/w group 5 inversion selects direct output or inve rted output for pulse output group 5. 0: inverted output 1: direct output 4 g0inv 1 r/w group 4 inversion selects direct output or inve rted output for pulse output group 4. 0: inverted output 1: direct output section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 706 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 g3nov 0 r/w group 7 non-overlap selects normal or non-overlapping operation for pulse output group 7. 0: normal operation (output values updated by compare match a on the selected tpu channel) 1: non-overlapping operation (output values updated by compare match a or b on the selected tpu channel) 2 g2nov 0 r/w group 6 non-overlap selects normal or non-overlapping operation for pulse output group 6. 0: normal operation (output values updated by compare match a on the selected tpu channel) 1: non-overlapping operation (output values updated by compare match a or b on the selected tpu channel) 1 g1nov 0 r/w group 5 non-overlap selects normal or non-overlapping operation for pulse output group 5. 0: normal operation (output values updated by compare match a on the selected tpu channel) 1: non-overlapping operation (output values updated by compare match a or b on the selected tpu channel) 0 g0nov 0 r/w group 4 non-overlap selects normal or non-overlapping operation for pulse output group 4. 0: normal operation (output values updated by compare match a on the selected tpu channel) 1: non-overlapping operation (output values updated by compare match a or b on the selected tpu channel) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 707 of 1340 rej09b0499-0200 15.4 operation figure 15.3 shows a schematic diagram of the ppg. ppg pulse output is enabled when the corresponding bits in nder are set to 1. an initial output value is determined by its corresponding podr initial setting. when the compare match event specified by pcr occurs, the corresponding ndr bit contents are transferred to podr to update the output values. sequential output of data of up to 8 bits from unit 0 or 16 bits from unit 1 is possible by writing new output data to ndr before the next compare match. output trigger signal pulse output pin internal data bus normal output/inverted output c podr qd nder q ndr qd figure 15.3 schematic diagram of ppg 15.4.1 output timing if pulse output is enabled, the ndr contents ar e transferred to podr and output when the specified compare match event occurs. figure 15.4 shows the timing of th ese operations for the case of normal output in groups 2 and 3, triggered by compare match a. tcnt n n + 1 p tgra n compare match a signal ndrh mn podrh po8 to po15 n m n figure 15.4 timing of transfer and output of ndr contents (example) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 708 of 1340 rej09b0499-0200 15.4.2 sample setup procedure for normal pulse output figures 15.5 and 15.6 show a sample procedure for setting up normal pulse output. ? sample setup procedure for ppg0 select tgr functions [1] set tgra value set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data normal ppg output no yes tpu0 setup ppg0 setup tpu0 setup [2] [3] [4] [5] [6] [7] [8] [9] [10] compare match? [1] set tior in tpu0 to make tgra an output compare register (with output disabled). [2] set the ppg output trigger cycle. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the bits in nder for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the output trigger in pcr. [8] set the next pulse output values in ndr. [9] set the cst bit in tstr to 1 to start the tcnt counter. [10] at each tgia interrupt, set the next figure 15.5 setup procedure fo r normal pulse output (ppg0) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 709 of 1340 rej09b0499-0200 ? sample setup procedure for ppg1 select tgr functions [1] set tgra value set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data normal ppg output no yes tpu1 setup ppg1 setup tpu1 setup [2] [3] [4] [5] [6] [7] [8] [9] [10] compare match? [1] set tior in tpu1 to make tgra an output compare register (toggle output). [2] set the ppg output trigger cycle. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the bits in nder for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the output trigger in pcr. [8] set the next pulse output values in ndr. [9] set the cst bit in tstr to 1 to start the tcnt counter. [10] at each tgia interrupt, set the next output values in ndr. figure 15.6 setup procedure fo r normal pulse output (ppg1) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 710 of 1340 rej09b0499-0200 15.4.3 example of normal pulse output (e xample of 5-phase pulse output) figure 15.7 shows an example in which pulse output is used for cyclic 5-phase pulse output. tcnt value tcnt tgra h'0000 ndrh 00 80 c0 40 60 20 30 10 18 08 88 podrh po15 po14 po13 po12 po11 time compare match c0 80 c0 80 40 60 20 30 10 18 08 88 80 c0 40 figure 15.7 normal pulse output example (5-phase pulse output) 1. set up tgra in tpu which is used as the outp ut trigger to be an output compare register. set a cycle in tgra so the counter will be cleared by compare match a. set the tgiea bit in tier to 1 to enable the compare match/input capture a (tgia) interrupt. 2. write h'f8 to nderh, and set bits g3cms1, g3cms0, g2cms1, and g2cms0 in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. write output data h'80 in ndrh. 3. the timer counter in the tpu channel starts. when compare match a occurs, the ndrh contents are transferred to podrh and output. th e tgia interrupt handling routine writes the next output data (h'c0) in ndrh. 4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing h'40, h'60, h'20, h'30, h'10, h'18, h'08, h'88... at successive tgia interrupts. if the dtc or dmac is set for activation by the tgia interrupt, pulse output can be obtained without imposing a load on the cpu. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 711 of 1340 rej09b0499-0200 15.4.4 non-overlapping pulse output during non-overlapping operation, transfer from ndr to podr is performed as follows: ? at compare match a, the ndr bits are always transferred to podr. ? at compare match b, the ndr bits are transferre d only if their value is 0. the ndr bits are not transferred if their value is 1. figur4.8 illustrates the non-overlapping pulse output operation. compare match a compare match b pulse output pin internal data bus normal output/inverted output c podr qd nder q ndr qd figure 15.8 non-overl apping pulse output therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. the ndr contents should not be altered during the interval from compare match b to compare match a (the non-overlapping margin). this can be accomplished by having the tgia interrupt handling routine write the next data in ndr, or by having the tgia interrupt activate the dtc or dmac. note, however, that the next data must be written before the next compare match b occurs. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 712 of 1340 rej09b0499-0200 figure 15.9 shows the timing of this operation. 0/1 output 0 output 0/1 output 0 output do not write to ndr here write to ndr here compare match a compare match b ndr podr do not write to ndr here write to ndr here write to ndr write to ndr figure 15.9 non-overlapping operation and ndr write timing section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 713 of 1340 rej09b0499-0200 15.4.5 sample setup procedure for non-overlapping pulse output figures 15.10 and 15.11 show a sample procedure for setting up non-overlapping pulse output. ? sample setup procedure for ppg0 select tgr functions [1] set tgr values set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data compare match a? no yes tpu0 setup ppg0 setup tpu0 setup non-overlapping pulse output set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] set tior in tpu0 to make tgra and tgrb output compare registers (with output disabled). [2] set the pulse output trigger cycle in tgrb and the non-overlapping margin in tgra. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the bits in nder for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the pulse output trigger in pcr. [8] in pmr, select the groups that will operate in non-overlapping mode. [9] set the next pulse output values in ndr. [10] set the cst bit in tstr to 1 to start the tcnt counter. [11] at each tgia interrupt, set the next output values in ndr. figure 15.10 setup procedure for no n-overlapping pulse output (ppg0) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 714 of 1340 rej09b0499-0200 ? sample setup procedure for ppg1 select tgr functions [1] set tgr values set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data compare match a? no yes tpu1 setup ppg1 setup tpu1 setup non-overlapping pulse output set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] set tior in tpu1 to make tgra and tgrb output compare registers (toggle output). [2] set the pulse output trigger cycle in tgrb and the non-overlapping margin in tgra. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the bits in nder for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the pulse output trigger in pcr. [8] in pmr, select the groups that will operate in non-overlapping mode. [9] set the next pulse output values in ndr. [10] set the cst bit in tstr to 1 to start the tcnt counter. [11] at each tgia interrupt, set the next output values in ndr. figure 15.11 setup procedure for no n-overlapping pulse output (ppg1) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 715 of 1340 rej09b0499-0200 15.4.6 example of non-overlapping pulse output (example of 4-phase complementary non-overlapping pulse output) figure 15.12 shows an example in which pulse output is used for 4-phase complementary non- overlapping pulse output. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrh po15 po14 po13 po12 po11 po10 po9 po8 time non-overlapping margin figure 15.12 non-overlappi ng pulse output example (4-phase complementary) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 716 of 1340 rej09b0499-0200 1. set up the tpu channel to be used as the output trigger channel so that tgra and tgrb are output compare registers. set the cycle in tgrb and the non-overlapping margin in tgra, and set the counter to be cleared by compare match b. set the tgiea bit in tier to 1 to enable the tgia interrupt. 2. write h'ff to nderh, and set bits g3cms1, g3cms0, g2cms1, and g2cms0 in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. set bits g3nov and g2nov in pmr to 1 to select non-overlapping pulse output. write output data h'95 to ndrh. 3. the timer counter in the tpu channel starts. when a compare match with tgrb occurs, outputs change from 1 to 0. when a compare match with tgra occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in tgra). the tgia interrupt handling routine writes the next output data (h'65) to ndrh. 4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing h'59, h'56, h'95... at succes sive tgia interrupts. if the dtc or dmac is set for activation by a tgia interrupt, pulse can be output without imposing a load on the cpu. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 717 of 1340 rej09b0499-0200 15.4.7 inverted pulse output if the g3inv, g2inv, g1inv, and g0inv bits in pmr are cleared to 0, values that are the inverse of the podr contents can be output. figure 15.13 shows the outputs when the g3inv an d g2inv bits are cleared to 0, in addition to the settings of figure 15.12. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrl po15 po14 po13 po12 po11 po10 po9 po8 time figure 15.13 inverted pulse output (example) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 718 of 1340 rej09b0499-0200 15.4.8 pulse output triggered by input capture pulse output of ppg0 can be triggered by tpu0 input capture as well as by compare match. if tgra functions as an in put capture register in the tpu0 chan nel selected by pcr, pulse output will be triggered by the input capture signal. figure 15.14 shows the timing of this output. ppg1 cannot be used to trigger pulse output by input capturer. p n mn tioc pin input capture signal ndr podr mn po figure 15.14 pulse output tri ggered by input capture (example) section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 719 of 1340 rej09b0499-0200 15.5 usage notes 15.5.1 module stop state setting ppg operation can be disabled or enabled using the module stop control register. the initial value is for ppg operation to be halted. register acce ss is enabled by clearing the module stop state. for details, refer to section 27, power-down modes. 15.5.2 operation of pulse output pins pins po0 to po7 are also used for other peripheral functions such as the tpu. when output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. note, however, that data tr ansfer from ndr bits to podr bits takes place, regardless of the usage of the pins. pin functions should be changed only under conditions in which the output trigger event will not occur. 15.5.3 tpu setting when ppg1 is in use when using ppg1, output toggling on compare-matches must be specified in the tior register of the tpu that acts as the activation source and out put must be selected as the ppg1 function. section 15 programmable pulse generator (ppg) rev. 2.00 oct. 20, 2009 page 720 of 1340 rej09b0499-0200 section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 721 of 1340 rej09b0499-0200 section 16 8-bit timers (tmr) this lsi has four units (unit 0 to unit 3) of an on-chip 8-bit timer module that comprise two 8-bit counter channels, totaling eight channels. the 8-bi t timer module can be us ed to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers. figures 16.1 to 16.4 show block diagrams of the 8-bit timer module (unit 0 to unit 3). this section describes unit 0 (channels 0 and 1) and unit 2 (channels 4 and 5), both of which have the same functions. unit 2 and unit 3 can generate baud rate clock for sci and have the same functions. 16.1 features ? selection of seven clock sources the counters can be driven by one of six internal clock signals (p /2, p /8, p /32, p /64, p /1024, or p /8192) or an external clock input (only internal clock available in units 2 and 3: p , p /2, p /8, p /32, p /64, p /1024, and p /8192). ? selection of three ways to clear the counters the counters can be cleared on compare match a or b, or by an external reset signal. (this is available only in unit 0 and unit 1.) ? timer output control by a combination of two compare match signals the timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to output pulses with a desired duty cycle or pwm output. ? cascading of two channels operation as a 16-bit timer is possible, using tmr_0 for the upper 8 bits and tmr_1 for the lower 8 bits (16-bit count mode). tmr_1 can be used to count tmr_0 compare matches (compare match count mode). ? three interrupt sources compare match a, compare match b, and overflow interrupts can be requested independently. (this is available only in unit 0 and unit 1.) ? generation of trigger to start a/d converter conversion (available in unit 0 to unit 3) ? capable of generating baud rate clock for sci_5 and sci_6. (this is available only in unit 2 and unit 3). for details, see section 18, seri al communication inte rface (sci, irda, crc). ? module stop state specifiable section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 722 of 1340 rej09b0499-0200 cmia0 cmia1 cmib0 cmib1 ovi0 ovi1 tmo0 tmo1 tmci0 tmci1 tmri0 tmri1 tcora_1: tcnt_1: tcorb_1: tcsr_1: tcr_1: tccr_1: tcora_0: tcnt_0: tcorb_0: tcsr_0: tcr_0: tccr_0: p /2 p /8 p /32 p /64 p /1024 p /81 9 2 counter clock 1 counter clock 0 compare match a1 compare match a0 overflow 1 overflow 0 counter clear 0 counter clear 1 compare match b1 compare match b0 comparator a_0 comparator a_1 tcora_0 tcorb_0 tcsr_0 tccr_0 tcora_1 tcnt_1 tcorb_1 tcsr_1 tccr_1 tcr_0 tcr_1 tcnt_0 comparator b_0 comparator b_1 a/d conversion start request signal * internal bus time constant register a_1 timer counter_1 time constant register b_1 timer control/status register_1 timer control register_1 timer counter control register_1 time constant register a_0 timer counter_0 time constant register b_0 timer control/status register_0 timer control register_0 timer counter control register_0 interrupt signals internal clocks clock select control logic external clocks [legend] channel 1 (tmr_1) channel 0 (tmr_0) note: * for the corresponding a/d converter channels, see section 21, a/d converter. figure 16.1 block diagram of 8-bit timer module (unit 0) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 723 of 1340 rej09b0499-0200 cmia2 cmia3 cmib2 cmib3 ovi2 ovi3 tmo2 tmo3 tmci2 tmci3 tmri2 tmri3 tcora_3: tcnt_3: tcorb_3: tcsr_3: tcr_3: tccr_3: tcora_2: tcnt_2: tcorb_2: tcsr_2: tcr_2: tccr_2: p /2 p /8 p /32 p /64 p /1024 p /81 9 2 counter clock 3 counter clock 2 compare match a3 compare match a2 overflow 3 overflow 2 counter clear 2 counter clear 3 compare match b3 compare match b2 comparator a_2 comparator a_3 tcora_2 tcorb_2 tcsr_2 tccr_2 tcora_3 tcnt_3 tcorb_3 tcsr_3 tccr_3 tcr_2 tcr_3 tcnt_2 comparator b_2 comparator b_3 a/d conversion start request signal * internal bus time constant register a_3 timer counter_3 time constant register b_3 timer control/status register_3 timer control register_3 timer counter control register_3 time constant register a_2 timer counter_2 time constant register b_2 timer control/status register_2 timer control register_2 timer counter control register_2 interrupt signals internal clocks clock select control logic external clocks [legend] channel 3 (tmr_3) channel 2 (tmr_2) note: * for the corresponding a/d converter channels, see section 21, a/d converter. figure 16.2 block diagram of 8-bit timer module (unit 1) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 724 of 1340 rej09b0499-0200 cmia4 cmib4 cmia5 cmib5 tcora_5: tcnt_5: tcorb_5: tcsr_5: tcr_5: tccr_5: tcora_4: tcnt_4: tcorb_4: tcsr_4: tcr_4: tccr_4: p p /2 p /8 p /32 p /64 p /1024 p /81 9 2 counter clock 5 counter clock 4 compare match a5 compare match a4 overflow 5 overflow 4 tmo4 tmo5 to sci_5 counter clear 4 counter clear5 compare match b5 compare match b4 comparator a_4 comparator a_5 tcora_4 tcorb_4 tcsr_4 tccr_4 tcora_5 tcnt_5 tcorb_5 tcsr_5 tccr_5 cmi4 cmi5 tcr_4 tcr_5 tcnt_4 comparator b_4 comparator b_5 internal bus time constant register a_5 timer counter_5 time constant register b_5 timer control/status register_5 timer control register_5 timer counter control register_5 time constant register a_4 timer counter_4 time constant register b_4 timer control/status register_4 timer control register_4 timer counter control register_4 interrupt signals internal clocks clock select control logic [legend] channel 5 (tmr_5) channel 4 (tmr_4) note: * for the corresponding a/d converter channels, see section 21, a/d converter. a/d conversion start request signal * figure 16.3 block diagram of 8-bit timer module (unit 2) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 725 of 1340 rej09b0499-0200 tcora_7: tcnt_7: tcorb_7: tcsr_7: tcr_7: tccr_7: tcora_6: tcnt_6: tcorb_6: tcsr_6: tcr_6: tccr_6: p p /2 p /8 p /32 p /64 p /1024 p /81 9 2 counter clock 7 counter clock 6 compare match a7 compare match a6 overflow 7 overflow 6 counter clear 6 counter clear 7 compare match b7 compare match b6 comparator a_6 comparator a_7 tcora_6 tcorb_6 tcsr_6 tccr_6 tcora_7 tcnt_7 tcorb_7 tcsr_7 tccr_7 tcr_6 tcr_7 tcnt_6 comparator b_6 comparator b_7 internal bus time constant register a_7 timer counter_7 time constant register b_7 timer control/status register_7 timer control register_7 timer counter control register_7 time constant register a_6 timer counter_6 time constant register b_6 timer control/status register_6 timer control register_6 timer counter control register_6 interrupt signals internal clocks clock select control logic [legend] cmia6 cmib6 cmia7 cmib7 cmi6 cmi7 channel 7 (tmr_7) channel 6 (tmr_6) tmo6 tmo7 to sci_6 a/d conversion start request signal * note: * for the corresponding a/d converter channels, see section 21, a/d converter. figure 16.4 block diagram of 8-bit timer module (unit 3) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 726 of 1340 rej09b0499-0200 16.2 input/output pins table 16.1 shows the pin configuration of the tmr. table 16.1 pin configuration unit channel name symbol i/o function timer output pin tmo0 output outputs compare match timer clock input pin tmci0 input inputs external clock for counter 0 timer reset input pin tmri0 input inputs external reset to counter timer output pin tmo1 output outputs compare match timer clock input pin tmci1 input inputs external clock for counter 0 1 timer reset input pin tmri1 input inputs external reset to counter timer output pin tmo2 output outputs compare match timer clock input pin tmci2 input inputs external clock for counter 2 timer reset input pin tmri2 input inputs external reset to counter timer output pin tmo3 output outputs compare match timer clock input pin tmci3 input inputs external clock for counter 1 3 timer reset input pin tmri3 input inputs external reset to counter 4 2 5 6 3 7 ? ? ? ? section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 727 of 1340 rej09b0499-0200 16.3 register descriptions the tmr has the following registers. unit 0: ? channel 0 (tmr_0): ? timer counter_0 (tcnt_0) ? time constant register a_0 (tcora_0) ? time constant register b_0 (tcorb_0) ? timer control register_0 (tcr_0) ? timer counter control register_0 (tccr_0) ? timer control/status register_0 (tcsr_0) ? channel 1 (tmr_1): ? timer counter_1 (tcnt_1) ? time constant register a_1 (tcora_1) ? time constant register b_1 (tcorb_1) ? timer control register_1 (tcr_1) ? timer counter control register_1 (tccr_1) ? timer control/status register_1 (tcsr_1) unit 1: ? channel 2 (tmr_2): ? timer counter_2 (tcnt_2) ? time constant register a_2 (tcora_2) ? time constant register b_2 (tcorb_2) ? timer control register_2 (tcr_2) ? timer counter control register_2 (tccr_2) ? timer control/status register_2 (tcsr_2) ? channel 3 (tmr_3): ? timer counter_3 (tcnt_3) ? time constant register a_3 (tcora_3) ? time constant register b_3 (tcorb_3) ? timer control register_3 (tcr_3) ? timer counter control register_3 (tccr_3) ? timer control/status register_3 (tcsr_3) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 728 of 1340 rej09b0499-0200 unit 2: ? channel 4 (tmr_4): ? timer counter_4 (tcnt_4) ? time constant register a_4 (tcora_4) ? time constant register b_4 (tcorb_4) ? timer control register_4 (tcr_4) ? timer counter control register_4 (tccr_4) ? timer control/status register_4 (tcsr_4) ? channel 5 (tmr_5): ? timer counter_5 (tcnt_5) ? time constant register a_5 (tcora_5) ? time constant register b_5 (tcorb_5) ? timer control register_5 (tcr_5) ? timer counter control register_5 (tccr_5) ? timer control/status register_5 (tcsr_5) unit 3: ? channel 6 (tmr_6): ? timer counter_6 (tcnt_6) ? time constant register a_6 (tcora_6) ? time constant register b_6 (tcorb_6) ? timer control register_6 (tcr_6) ? timer counter control register_6 (tccr_6) ? timer control/status register_6 (tcsr_6) ? channel 7 (tmr_7): ? timer counter_7 (tcnt_7) ? time constant register a_7 (tcora_7) ? time constant register b_7 (tcorb_7) ? timer control register_7 (tcr_7) ? timer counter control register_7 (tccr_7) ? timer control/status register_7 (tcsr_7) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 729 of 1340 rej09b0499-0200 16.3.1 timer counter (tcnt) tcnt is an 8-bit readable/writable up-counter. tcnt_0 and tcnt_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. bits cks2 to cks0 in tcr and bits icks1 and icks0 in tccr are used to select a clock. tcnt can be cleared by an external reset input signal, compare match a signal, or compare match b signal. which signal to be used for clearing is selected by bits cclr1 and cclr0 in tcr. when tcnt overflows from h'ff to h'00, bit ovf in tcsr is set to 1. tcnt is initialized to h'00. 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt_0 tcnt_1 bit bit name initial value r/w 16.3.2 time constant register a (tcora) tcora is an 8-bit readable/writable register. tcora_0 and tcora_1 comprise a single 16-bit register so they can be accessed together by a wo rd transfer inst ruction. the value in tcora is continually compared with the value in tcnt. when a match is detected, the corresponding cmfa flag in tcsr is set to 1. note however that comparison is disabled during the t2 state of a tcora write cycle. the timer output from the tmo pin can be freely controlled by this compare match signal (compare match a) and the settings of bits os1 and os0 in tcsr. tcora is initialized to h'ff. 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora_0 tcora_1 bit bit name initial value r/w section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 730 of 1340 rej09b0499-0200 16.3.3 time constant register b (tcorb) tcorb is an 8-bit readable/writable register. tcorb_0 and tcorb_1 comprise a single 16-bit register so they can be accessed together by a wo rd transfer inst ruction. tcorb is continually compared with the value in tcnt . when a match is detected, th e corresponding cmfb flag in tcsr is set to 1. note however that comparison is disabled during the t2 state of a tcorb write cycle. the timer output from the tmo pin can be freely controlled by this compare match signal (compare match b) and the settings of bits os3 and os2 in tcsr. tcorb is initialized to h'ff. 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb_0 tcorb_1 bit bit name initial value r/w 16.3.4 timer control register (tcr) tcr selects the tcnt clock source and the condition for clearing tcnt, and enables/disables interrupt requests. 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b selects whether cmfb interrupt requests (cmib) are enabled or disabled when the cmfb flag in tcsr is set to 1. * 2 0: cmfb interrupt requests (cmib) are disabled 1: cmfb interrupt requests (cmib) are enabled section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 731 of 1340 rej09b0499-0200 bit bit name initial value r/w description 6 cmiea 0 r/w compare match interrupt enable a selects whether cmfa interrupt requests (cmia) are enabled or disabled when the cmfa flag in tcsr is set to 1. * 2 0: cmfa interrupt requests (cmia) are disabled 1: cmfa interrupt requests (cmia) are enabled 5 ovie 0 r/w timer overflow interrupt enable * 3 selects whether ovf interrupt requests (ovi) are enabled or disabled when the ovf flag in tcsr is set to 1. 0: ovf interrupt requests (ovi) are disabled 1: ovf interrupt requests (ovi) are enabled 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 * 1 these bits select the method by which tcnt is cleared. 00: clearing is disabled 01: cleared by compare match a 10: cleared by compare match b 11: cleared at rising edge (tmris in tccr is cleared to 0) of the external reset input or when the external reset input is high (tmris in tccr is set to 1) * 3 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 * 1 these bits select the clock input to tcnt and count condition. see table 16.2. notes: 1. to use an external reset or external clock, the ddr and icr bits in the corresponding pin should be set to 0 and 1, respectively . for details, see section 13, i/o ports. 2. in unit 2 and unit 3, one interrupt signal is used for cmieb or cmiea. for details, see section 16.7, interrupt sources. 3. available only in unit 0 and unit 1. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 732 of 1340 rej09b0499-0200 16.3.5 timer counter control register (tccr) tccr selects the tcnt internal clock source and controls external reset input. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 tmris 0 r/w 2 ? 0 r 1 icks1 0 r/w 0 icks0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. it should not be set to 0. 3 tmris 0 r/w timer reset input select * selects an external reset input when the cclr1 and cclr0 bits in tcr are b'11. 0: cleared at rising edge of the external reset 1: cleared when the external reset is high 2 ? 0 r reserved this bit is always read as 0. it should not be set to 0. 1 0 icks1 icks0 0 0 r/w r/w internal clock select 1 and 0 these bits in combination with bits cks2 to cks0 in tcr select the internal clock. see table 16.2. note: * available only in unit 0 and unit 1. the writ e value should always be 0 in unit 2 and unit 3. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 733 of 1340 rej09b0499-0200 table 16.2 clock input to tcnt and count condition (unit 0) tcr tccr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description 0 0 0 ? ? clock input prohibited 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 0 0 1 1 1 uses internal clock. counts at falling edge of p /2. 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 0 1 0 1 1 uses internal clock. counts at falling edge of p /32. 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at falling edge of p /8192. 0 1 1 1 1 uses internal clock. counts at falling edge of p /1024. tmr_0 1 0 0 ? ? counts at tcnt_1 overflow signal * 1 . 0 0 0 ? ? clock input prohibited 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 0 0 1 1 1 uses internal clock. counts at falling edge of p /2. 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 0 1 0 1 1 uses internal clock. counts at falling edge of p /32. 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at falling edge of p /8192. 0 1 1 1 1 uses internal clock. counts at falling edge of p /1024. tmr_1 1 0 0 ? ? counts at tcnt_0 compare match a * 1 . 1 0 1 ? ? uses external clock. counts at rising edge * 2 . 1 1 0 ? ? uses external clock. counts at falling edge * 2 . all 1 1 1 ? ? uses external clock. counts at both rising and falling edges * 2 . notes: 1. if the clock input of channel 0 is the t cnt_1 overflow signal and that of channel 1 is the tcnt_0 compare match signal, no incrementi ng clock is generated. do not use this setting. 2. to use the external clock, the ddr and i cr bits in the corresponding pin should be set to 0 and 1, respectively. for de tails, see section 13, i/o ports. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 734 of 1340 rej09b0499-0200 table 16.3 clock input to tcnt and count condition (unit 1) tcr tccr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description 0 0 0 ? ? clock input prohibited 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 0 0 1 1 1 uses internal clock. counts at falling edge of p /2. 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 0 1 0 1 1 uses internal clock. counts at falling edge of p /32. 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at falling edge of p /8192. 0 1 1 1 1 uses internal clock. counts at falling edge of p /1024. tmr_2 1 0 0 ? ? counts at tcnt_3 overflow signal * 1 . 0 0 0 ? ? clock input prohibited 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 0 0 1 1 1 uses internal clock. counts at falling edge of p /2. 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 0 1 0 1 1 uses internal clock. counts at falling edge of p /32. 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at falling edge of p /8192. 0 1 1 1 1 uses internal clock. counts at falling edge of p /1024. tmr_3 1 0 0 ? ? counts at tcnt_2 compare match a * 1 . 1 0 1 ? ? uses external clock. counts at rising edge * 2 . 1 1 0 ? ? uses external clock. counts at falling edge * 2 . all 1 1 1 ? ? uses external clock. counts at both rising and falling edges * 2 . notes: 1. if the clock input of channel 2 is the t cnt_3 overflow signal and that of channel 3 is the tcnt_2 compare match signal, no incrementi ng clock is generated. do not use this setting. 2. to use the external clock, the ddr and i cr bits in the corresponding pin should be set to 0 and 1, respectively. for de tails, see section 13, i/o ports. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 735 of 1340 rej09b0499-0200 table 16.4 clock input to tcnt and count condition (unit 2) tcr tccr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description 0 0 0 ? ? clock input prohibited 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 0 0 1 1 1 uses internal clock. counts at falling edge of p /2. 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 0 1 0 1 1 uses internal clock. counts at falling edge of p /32. 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at rising edge of p . 0 1 1 1 1 uses internal clock. counts at falling edge of p /1024. tmr_4 1 0 0 ? ? counts at tcnt_5 overflow signal * . 0 0 0 ? ? clock input prohibited 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 0 0 1 1 1 uses internal clock. counts at falling edge of p /2. 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 0 1 0 1 1 uses internal clock. counts at falling edge of p /32. 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at rising edge of p . 0 1 1 1 1 uses internal clock. counts at falling edge of p /1024. tmr_5 1 0 0 ? ? counts at tcnt_4 compare match a *. 1 0 1 ? ? setting prohibited 1 1 0 ? ? setting prohibited all 1 1 1 ? ? setting prohibited note: * if the clock input of channel 4 is the tcnt_5 overflow signal and that of channel 5 is the tcnt_4 compare match signal, no incrementi ng clock is generated. do not use this setting. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 736 of 1340 rej09b0499-0200 table 16.5 clock input to tcnt and count condition (unit 3) tcr tccr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description 0 0 0 ? ? clock input prohibited 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 0 0 1 1 1 uses internal clock. counts at falling edge of p /2. 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 0 1 0 1 1 uses internal clock. counts at falling edge of p /32. 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at rising edge of p . 0 1 1 1 1 uses internal clock. counts at falling edge of p /1024. tmr_6 1 0 0 ? ? counts at tcnt_7 overflow signal * . 0 0 0 ? ? clock input prohibited 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 0 0 1 1 1 uses internal clock. counts at falling edge of p /2. 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 0 1 0 1 1 uses internal clock. counts at falling edge of p /32. 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at rising edge of p . 0 1 1 1 1 uses internal clock. counts at falling edge of p /1024. tmr_7 1 0 0 ? ? counts at tcnt_6 compare match a *. 1 0 1 ? ? setting prohibited 1 1 0 ? ? setting prohibited all 1 1 1 ? ? setting prohibited note: * if the clock input of channel 6 is the tcnt_7 overflow signal and that of channel 7 is the tcnt_6 compare match signal, no incrementi ng clock is generated. do not use this setting. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 737 of 1340 rej09b0499-0200 16.3.6 timer control/status register (tcsr) tcsr displays status flags, and controls compare match output. ? tcsr_0 ? tcsr_1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 2 os2 0 r/w 1 os1 0 r/w 0 os0 0 r/w 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 r 3 os3 0 r/w 2 os2 0 r/w 1 os1 0 r/w 0 os0 0 r/w bit bit name initial value r/w bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. ? tcsr_0, tcsr_4 bit bit name initial value r/w description 7 cmfb 0 r/(w) * 1 compare match flag b [setting condition] ? when tcnt matches tcorb [clearing conditions] ? when writing 0 after reading cmfb = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when the dtc is activated by a cmib interrupt while the disel bit in mrb of the dtc is 0 section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 738 of 1340 rej09b0499-0200 bit bit name initial value r/w description 6 cmfa 0 r/(w) * 1 compare match flag a [setting condition] ? when tcnt matches tcora [clearing conditions] ? when writing 0 after reading cmfa = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when the dtc is activated by a cmia interrupt while the disel bit in mrb in the dtc is 0 5 ovf 0 r/(w) * 1 timer overflow flag [setting condition] when tcnt overflows from h'ff to h'00 [clearing condition] when writing 0 after reading ovf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 4 adte 0 r/w a/d trigger enable selects enabling or disabling of a/d converter start requests by compare match a. 0: a/d converter start requests by compare match a are disabled 1: a/d converter start requests by compare match a are enabled 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 * 2 these bits select a method of tmo pin output when compare match b of tcorb and tcnt occurs. 00: no change when compare match b occurs 01: 0 is output when compare match b occurs 10: 1 is output when compare match b occurs 11: output is inverted when compare match b occurs (toggle output) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 739 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 * 2 these bits select a method of tmo pin output when compare match a of tcora and tcnt occurs. 00: no change when compare match a occurs 01: 0 is output when compare match a occurs 10: 1 is output when compare match a occurs 11: output is inverted when compare match a occurs (toggle output) notes: 1. only 0 can be written to bi ts 7 to 5, to clear these flags. 2. timer output is disabled when bits os3 to os0 are all 0. timer output is 0 until the first compare match occurs after a reset. ? tcsr_1, tcsr_5 bit bit name initial value r/w description 7 cmfb 0 r/(w) * 1 compare match flag b [setting condition] ? when tcnt matches tcorb [clearing conditions] ? when writing 0 after reading cmfb = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when the dtc is activated by a cmib interrupt while the disel bit in mrb of the dtc is 0* 3 section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 740 of 1340 rej09b0499-0200 bit bit name initial value r/w description 6 cmfa 0 r/(w) * 1 compare match flag a [setting condition] ? when tcnt matches tcora [clearing conditions] ? when writing 0 after reading cmfa = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when the dtc is activated by a cmia interrupt while the disel bit in mrb of the dtc is 0 * 3 5 ovf 0 r/(w) * 1 timer overflow flag [setting condition] when tcnt overflows from h'ff to h'00 [clearing condition] cleared by reading ovf when ovf = 1, then writing 0 to ovf (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 4 ? 1 r reserved this bit is always read as 1 and cannot be modified. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 * 2 these bits select a method of tmo pin output when compare match b of tcorb and tcnt occurs. 00: no change when compare match b occurs 01: 0 is output when compare match b occurs 10: 1 is output when compare match b occurs 11: output is inverted when compare match b occurs (toggle output) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 741 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 * 2 these bits select a method of tmo pin output when compare match a of tcora and tcnt occurs. 00: no change when compare match a occurs 01: 0 is output when compare match a occurs 10: 1 is output when compare match a occurs 11: output is inverted when compare match a occurs (toggle output) notes: 1. only 0 can be written to bi ts 7 to 5, to clear these flags. 2. timer output is disabled when bits os3 to os 0 are all 0. timer output is 0 until the first compare match occurs after a reset. 3. available only in unit 0 and unit 1. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 742 of 1340 rej09b0499-0200 16.4 operation 16.4.1 pulse output figure 16.5 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. the control bits are set as follows: 1. clear the bit cclr1 in tcr to 0 and set the bit cclr0 in tcr to 1 so that tcnt is cleared at a tcora compare match. 2. set the bits os3 to os0 in tcsr to b'0110, causing the output to change to 1 at a tcora compare match and to 0 at a tcorb compare match. with these settings, the 8-bit timer provides pulses output at a cycle determined by tcora with a pulse width determined by tcorb. no software intervention is required. the timer output is 0 until the first compare matc h occurs after a reset. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 16.5 example of pulse output section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 743 of 1340 rej09b0499-0200 16.4.2 reset input figure 16.6 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a tmri input. the control bits are set as follows: 1. set both bits cclr1 and cclr0 in tcr to 1 and set the tmris bit in tccr to 1 so that tcnt is cleared at the high level input of the tmri signal. 2. in tcsr, set bits os3 to os0 to b'0110, causing the output to change to 1 at a tcora compare match and to 0 at a tcorb compare match. with these settings, the 8-bit timer provides pulses output at a desired delay time from a tmri input determined by tcora and with a pulse width determined by tcorb and tcora. tcnt tcorb tcora h'00 tmri tmo figure 16.6 example of reset input section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 744 of 1340 rej09b0499-0200 16.5 operation timing 16.5.1 tcnt count timing figure 16.7 shows the tcnt count timing for internal clock input. figure 16.8 shows the tcnt count timing for external clock inpu t. note that the external clock pulse width must be at least 1.5 states for increment at a single edge, and at l east 2.5 states for increm ent at both edges. the counter will not increment correctly if the pulse width is less than these values. p internal clock tcnt input clock tcnt n ? 1 n n + 1 figure 16.7 count timing for internal clock input p external clock input pin tcnt input clock tcnt n ? 1 n n + 1 figure 16.8 count timing for external clock input section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 745 of 1340 rej09b0499-0200 16.5.2 timing of cmfa and cmfb setting at compare match the cmfa and cmfb flags in tcsr are set to 1 by a compare match signal generated when the tcor and tcnt values match. the compare match si gnal is generated at the last state in which the match is true, just before the timer counter is updated. therefore, when the tcor and tcnt values match, the compare match signal is not generated until the next tcnt clock input. figure 16.9 shows this timing. p tcnt n n + 1 tcor n compare match signal cmf figure 16.9 timing of cmf setting at compare match 16.5.3 timing of timer output at compare match when a compare match signal is generated, the timer output changes as specified by the bits os3 to os0 in tcsr. figure 16.10 shows the timing when the timer output is toggled by the compare match a signal. p compare match a signal timer output pin figure 16.10 timing of toggled timer output at compare match a section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 746 of 1340 rej09b0499-0200 16.5.4 timing of counter clear by compare match tcnt is cleared when compare match a or b occurs, depending on the settings of the bits cclr1 and cclr0 in tcr. figure 16.11 shows the timing of this operation. p n h'00 compare match signal tcnt figure 16.11 timing of co unter clear by compare match 16.5.5 timing of tcnt external reset* tcnt is cleared at the rising edge or high level of an external reset input, depending on the settings of bits cclr1 and cclr0 in tcr. the clear pulse width must be at least 2 states. figures 16.12 and 16.13 shows the timing of this operation. note: * clearing by an external reset is available only in units 0 and 1. p clear signal external reset input pin tcnt n h'00 n ? 1 figure 16.12 timing of clearan ce by external reset (rising edge) section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 747 of 1340 rej09b0499-0200 p clear signal external reset input pin tcnt n h'00 n ? 1 figure 16.13 timing of clearan ce by external reset (high level) 16.5.6 timing of overflow flag (ovf) setting the ovf bit in tcsr is set to 1 when tcnt overflows (changes from h'ff to h'00). figure 16.14 shows the timing of this operation. p ovf overflow signal tcnt h'ff h'00 figure 16.14 timing of ovf setting section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 748 of 1340 rej09b0499-0200 16.6 operation with cascaded connection if the bits cks2 to cks0 in either tcr_0 or tcr_1 are set to b'100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). 16.6.1 16-bit counter mode when the bits cks2 to cks0 in tcr_0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. (1) setting of compare match flags ? the cmf flag in tcsr_0 is set to 1 when a 16-bit compare match event occurs. ? the cmf flag in tcsr_1 is set to 1 when a lower 8-bit compare match event occurs. (2) counter clear specification ? if the cclr1 and cclr0 bits in tcr_0 have been set for counter clear at compare match, the 16-bit counter (tcnt_0 and tcnt_1 together) is cleared when a 16-b it compare match event occurs. the 16-bit counter (tcnt0 and tcnt1 toge ther) is cleared even if counter clear by the tmri0 pin has been set. ? the settings of the cclr1 and cclr0 bits in tcr_1 are ignored. the lower 8 bits cannot be cleared independently. (3) pin output ? control of output from the tmo0 pin by the bits os3 to os0 in tcsr_0 is in accordance with the 16-bit compare match conditions. ? control of output from the tmo1 pin by the bits os3 to os0 in tcsr_1 is in accordance with the lower 8-bit compare match conditions. 16.6.2 compare match count mode when the bits cks2 to cks0 in tcr_1 are set to b'100, tcnt_1 counts compare match a for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clear are in accordance with the settings for each channel. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 749 of 1340 rej09b0499-0200 16.7 interrupt sources 16.7.1 interrupt sources a nd dtc activation ? interrupt in unit 0 and unit 1 there are three interrupt sources for the 8-bit timer (tmr_0 or tmr_1): cmia, cmib, and ovi. their interrupt sources and priorities are shown in table 16.6. each interrupt source is enabled or disabled by the corresponding interrupt enable bit in tcr or tcsr, and independent interrupt requests are sent for each to the interrupt contro ller. it is also possibl e to activate the dtc by means of cmia and cmib interrupts (this is available in unit 0 and unit 1 only). table 16.6 8-bit timer (tmr_0 or tmr_1) interrupt sources (in unit 0 and unit 1) signal name name interrupt source interrupt flag dtc activation priority cmia0 cmia0 tcora_0 compare match cmfa possible cmib0 cmib0 tcorb_0 compare match cmfb possible high ovi0 ovi0 tcnt_0 overflow ovf not possible low cmia1 cmia1 tcora_1 compare match cmfa possible cmib1 cmib1 tcorb_1 compare match cmfb possible high ovi1 ovi1 tcnt_1 overflow ovf not possible low ? interrupt in unit 2 and unit 3 there are two interrupt sources for the 8-b it timer (tmr_4 or tmr_5): cmia, cmib. the interrupt signal is cmi only. the interrupt sources are shown in table 16.7. when enabling or disabling is set by the interrupt enable bit in tcr or tcsr, and when either cmia or cmib interrupt source is generated, cmi is sent to th e interrupt controller. to verify which interrupt source is generated, confirm by checking each flag in tcsr. no overflow-r elated interrupt signal exists. dtc cannot be activated by this interrupt. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 750 of 1340 rej09b0499-0200 table 16.7 8-bit timer (tmr_4 or tmr_5) interrupt sources (in unit 2 and unit 3) signal name name interrupt source interrupt flag dtc activation priority cmia4 tcora_4 compare match cmfa cmi4 cmib4 tcorb_4 compare match cmfb not possible ? cmia5 tcora_5 compare match cmfa cmi5 cmib5 tcorb_5 compare match cmfb not possible ? 16.7.2 a/d converter activation the a/d converter can be activated by a compare match a for the even channels of each tmr unit. * if the adte bit in tcsr is set to 1 when the cmfa flag in tcsr is set to 1 by the occurrence of a compare match a, a request to start a/d conversion is sent to the a/d converter. if the 8-bit timer conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. note: * for the corresponding a/d converter channels, see section 21, a/d converter. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 751 of 1340 rej09b0499-0200 16.8 usage notes 16.8.1 notes on setting cycle if the compare match is selected for counter clear, tc nt is cleared at the last state in the cycle in which the values of tcnt and tcor match. tcnt updates the counter value at this last state. therefore, the counter frequency is obtained by the following formula. f = / (n + 1 ) f: counter frequency : operating frequency n: tcor value 16.8.2 conflict between tcnt wr ite and counter clear if a counter clear signal is generated during the t 2 state of a tcnt write cycle, the clear takes priority and the write is not performed as shown in figure 16.15. p address tcnt address internal write signal counter clear signal tcnt n h'00 t 1 t 2 tcnt write cycle by cpu figure 16.15 conflict between tcnt write and clear section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 752 of 1340 rej09b0499-0200 16.8.3 conflict between tcnt write and increment if a tcnt input clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the counter is not incremented as shown in figure 16.16. p address tcnt address internal write signal tcnt input clock tcnt n m t 1 t 2 tcnt write cycle by cpu counter write data figure 16.16 conflict between tcnt write and increment 16.8.4 conflict between tcor write and compare match if a compare match event occurs during the t 2 state of a tcor write cycle, the tcor write takes priority and the compare match signal is inhibited as shown in figure 16.17. p address tcor address internal write signal tcnt tcor n m t 1 t 2 tcor write cycle by cpu tcor write data n n + 1 compare match signal inhibited figure 16.17 conflict between tcor write and compare match section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 753 of 1340 rej09b0499-0200 16.8.5 conflict between compare matches a and b if compare match events a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set fo r compare match a and comp are match b, as shown in table 16.8. table 16.8 timer output priorities output setting priority toggle output 1-output 0-output high no change low 16.8.6 switching of internal clocks and tcnt operation tcnt may be incremented erroneously depending on when the internal clock is switched. table 16.9 shows the relationship between the timing at which the internal clock is switched (by writing to the bits cks1 and cks0) and the tcnt operation. when the tcnt clock is generated from an internal clock, the rising or falling edge of the internal clock pulse are always monitored. table 16.9 assu mes that the falling edge is selected. if the signal levels of the clocks before and after switching change from high to low as shown in item 3, the change is considered as the falling edge. th erefore, a tcnt clock pulse is generated and tcnt is incremented. this is similar to when the rising edge is selected. the erroneous increment of tcnt can also happen when switching between rising and falling edges of the internal clock, and when swit ching between internal and external clocks. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 754 of 1340 rej09b0499-0200 table 16.9 switching of internal clock and tcnt operation no. timing to change cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt input clock tcnt cks bits changed n n + 1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt input clock tcnt cks bits changed n n + 1 n + 2 3 switching from high to low * 3 clock before switchover clock after switchover tcnt input clock tcnt cks bits changed n n + 1 n + 2 * 4 4 switching from high to high clock before switchover clock after switchover tcnt input clock tcnt cks bits changed n n + 1 n + 2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated because the chan ge of the signal levels is considered as a falling edge; tcnt is incremented. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 755 of 1340 rej09b0499-0200 16.8.7 mode setting with cascaded connection if 16-bit counter mode and compare match count mode are specified at the same time, input clocks for tcnt_0 and tcnt_1 are not generated, and the counter stops. do not specify 16-bit counter mode and compare match count mode simultaneously. 16.8.8 module stop state setting operation of the tmr can be disabled or enabled using the module stop control register. the initial setting is for operation of the tmr to be halted. register access is enabled by clearing the module stop state. for details, s ee section 27, power-down modes. 16.8.9 interrupts in module stop state if the module stop state is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. interrupts should therefore be disabled before entering the module stop state. section 16 8-bit timers (tmr) rev. 2.00 oct. 20, 2009 page 756 of 1340 rej09b0499-0200 section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 757 of 1340 rej09b0499-0200 section 17 watchdog timer (wdt) the watchdog timer (wdt) is an 8-bit timer that outputs an overflow signal ( wdtovf ) if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. at the same time, the wdt can also generate an internal reset signal. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. figure 17.1 shows a block diagram of the wdt. 17.1 features ? selectable from eight counter input clocks ? switchable between watchdog timer mode and interval timer mode ? in watchdog timer mode if the counter overflows, the wdt outputs wdtovf . it is possible to select whether or not the entire lsi is reset at the same time. ? in interval timer mode if the counter overflows, the wdt generates an interval timer interrupt (wovi). section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 758 of 1340 rej09b0499-0200 overflow interrupt control wovi (interrupt request signal) internal reset signal * wdtovf reset control rstcsr tcnt tcsr p /2 p /64 p /128 p /512 p /2048 p /8192 p /32768 p /131072 clock clock select internal clocks bus interface module bus tcsr: tcnt: rstcsr: note: * an internal reset signal can be generated by the rstcsr setting. timer control/status register timer counter reset control/status register wdt [legend] internal bus figure 17.1 block diagram of wdt 17.2 input/output pin table 17.1 shows the wdt pin configuration. table 17.1 pin configuration name symbol i/o function watchdog timer overflow * wdtovf output outputs a counter overflow signal in watchdog timer mode note: * in boundary scan valid mode, counter overflow signal output cannot be used. section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 759 of 1340 rej09b0499-0200 17.3 register descriptions the wdt has the following three registers. to prevent accidental overwriting, tcsr, tcnt, and rstcsr have to be written to in a method different from normal registers. for details, see section 17.6.1, notes on register access. ? timer counter (tcnt) ? timer control/status register (tcsr) ? reset control/status register (rstcsr) 17.3.1 timer counter (tcnt) tcnt is an 8-bit readable/writable up-counter. tc nt is initialized to h'00 when the tme bit in tcsr is cleared to 0. bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 17.3.2 timer control/status register (tcsr) tcsr selects the clock source to be input to tcnt, and the timer mode. bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 ? 1 r 3 ? 1 r 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 760 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 ovf 0 r/(w) * overflow flag indicates that tcnt has overflowed in interval timer mode. only 0 can be written to this bit, to clear the flag. [setting condition] when tcnt overflows in interval timer mode (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing condition] cleared by reading tcsr when ovf = 1, then writing 0 to ovf. (when the cpu is used to clear this flag while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 6 wt/ it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode when tcnt overflows, an interval timer interrupt (wovi) is requested. 1: watchdog timer mode when tcnt overflows, the wdtovf signal is output. 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4, 3 ? all 1 r reserved these are read-only bits and cannot be modified. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select the clock source to be input to tcnt. the overflow cycle for p = 20 mhz is indicated in parentheses. 000: clock p /2 (cycle: 25.6 s) 001: clock p /64 (cycle: 819.2 s) 010: clock p /128 (cycle: 1.6 ms) 011: clock p /512 (cycle: 6.6 ms) 100: clock p /2048 (cycle: 26.2 ms) 101: clock p /8192 (cycle: 104.9 ms) 110: clock p /32768 (cycle: 419.4 ms) 111: clock p /131072 (cycle: 1.68 s) note: * only 0 can be written to this bit, to clear the flag. section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 761 of 1340 rej09b0499-0200 17.3.3 reset control/status register (rstcsr) rstcsr controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, but not by the wdt internal reset signal caused by wdt overflows. 7 wovf 0 r/(w) * 6 rste 0 r/w 5 ? 0 r/w 4 ? 1 r 3 ? 1 r 2 ? 1 r 1 ? 1 r 0 ? 1 r bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. bit bit name initial value r/w description 7 wovf 0 r/(w) * watchdog timer overflow flag this bit is set when tcnt overflows in watchdog timer mode. this bit cannot be set in interval timer mode, and only 0 can be written. [setting condition] when tcnt overflows (changed from h'ff to h'00) in watchdog timer mode [clearing condition] reading rstcsr when wovf = 1, and then writing 0 to wovf 6 rste 0 r/w reset enable specifies whether or not this lsi is internally reset if tcnt overflows during watchdog timer operation. 0: lsi is not reset even if tcnt overflows (though this lsi is not reset, tcnt and tcsr in wdt are reset) 1: lsi is reset if tcnt overflows 5 ? 0 r/w reserved although this bit is readable/writable, reading from or writing to this bit does not affect operation. 4 to 0 ? all 1 r reserved these are read-only bits and cannot be modified. note: * only 0 can be written to this bit, to clear the flag. section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 762 of 1340 rej09b0499-0200 17.4 operation 17.4.1 watchdog timer mode to use the wdt in watchdog timer mode, set both the wt/ it and tme bits in tcsr to 1. during watchdog timer operation, if tcnt overflows without being rewritten because of a system crash or other error, the wdtovf signal is output. this ensures that tcnt does not overflow while the system is operating normally. software must prevent tcnt overflows by rewriting the tcnt value (normally h'00 is written) before overflow occurs. this wdtovf signal can be used to reset the lsi internally in watchdog timer mode. if tcnt overflows when the rste bit in rstcsr is set to 1, a signal that resets this lsi internally is generated at the same time as the wdtovf signal. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. the wdtovf signal is output for 133 cycles of p when rste = 1 in rstcsr, and for 130 cycles of p when rste = 0 in rstcsr. the internal reset signal is output for 519 cycles of p . when rste = 1, an internal reset signal is generated. since the system clock control register (sckcr) is initialized, the multiplication ratio of p becomes the initial value. when rste = 0, an internal reset signal is not generated. neither sckcr nor the multiplication ratio of p is changed. when tcnt overflows in watchdog timer mode, the wovf bit in rstcsr is set to 1. if tcnt overflows when the rste bit in rstcsr is set to 1, an internal reset signal is generated for the entire lsi. section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 763 of 1340 rej09b0499-0200 tcnt value h'00 time h'ff wt/ it = 1 tme = 1 h'00 written to tcnt wt/ it = 1 tme = 1 h'00 written to tcnt 133 states * 2 519 states wdtovf signal internal reset signal * 1 notes: 1. if tcnt overflows when the rste bit is set to 1, an internal reset signal is generated. 2. 130 states when the rste bit is cleared to 0. overflow wdtovf and internal reset are generated wovf = 1 figure 17.2 operation in watchdog timer mode section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 764 of 1340 rej09b0499-0200 17.4.2 interval timer mode to use the wdt as an interval timer, set the wt/ it bit to 0 and the tme bit to 1 in tcsr. when the wdt is used as an interval timer, an interval timer interrupt (wovi) is generated each time the tcnt overflows. therefore, an in terrupt can be generated at intervals. when the tcnt overflows in interval timer mode, an interval timer interrupt (wovi) is requested at the same time the ovf bit in the tcsr is set to 1. tcnt value h'00 time h'ff wt/ it = 0 tme = 1 wovi overflow overflow overflow overflow [legend] wovi: interval timer interrupt request wovi wovi wovi figure 17.3 operation in interval timer mode 17.5 interrupt source during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. the ovf flag must be cleared to 0 in the interrupt handling routine. table 17.2 wdt interrupt source name interrupt source interrupt flag dtc activation wovi tcnt overflow ovf impossible section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 765 of 1340 rej09b0499-0200 17.6 usage notes 17.6.1 notes on register access the watchdog timer's tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. (1) writing to tcnt, tcsr, and rstcsr tcnt and tcsr must be written to by a word transfer instruction. they cannot be written to by a byte transfer instruction. for writing, tcnt and tcsr are assigned to the same address. accordingly, perform data transfer as shown in figure 17.4. the transfer in struction writes the lower byte data to tcnt or tcsr. to write to rstcsr, execute a word transfer instruction for address h'ffa6. a byte transfer instruction cannot be used to write to rstcsr. the method of writing 0 to the wovf bit in rstcsr differs from that of writing to the rste bit in rstcsr. perform data transfer as shown in figure 17.4. at data transfer, the transfer in struction clears the wovf bit to 0, but has no effect on the rste bit. to write to the rste bit, perform data transfer as shown in figure 17.4. in this case, the transfer instruction writes the value in bit 6 of the lower byte to the rste bit, but has no effect on the wovf bit. tcnt write or writing to the rste bit in rstcsr: tcsr write: address: h'ffa4 (tcnt) h'ffa6 (rstcsr) 15 8 7 0 h'5a write data address: h'ffa4 (tcsr) 15 8 7 0 h'a5 write data writing 0 to the wovf bit in rstcsr: address: h'ffa6 (rstcsr) 15 8 7 0 h'a5 h'00 figure 17.4 writing to tcnt, tcsr, and rstcsr section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 766 of 1340 rej09b0499-0200 (2) reading from tcnt, tcsr, and rstcsr these registers can be read from in the same way as other registers. for reading, tcsr is assigned to address h'ffa4, tcnt to address h'ffa5, and rstcsr to address h'ffa7. 17.6.2 conflict between timer counter (tcnt) write and increment if a tcnt clock pulse is generated during the t2 cycle of a tcnt write cycle, the write takes priority and the timer counter is not increm ented. figure 17.5 shows this operation. n m t 1 t 2 address p internal write signal tcnt input clock tcnt tcnt write cycle counter write data figure 17.5 conflict between tcnt write and increment 17.6.3 changing values of bits cks2 to cks0 if bits cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. the watchdog timer must be stopped (by clearing the tme bit to 0) before the values of bits cks2 to cks0 are changed. 17.6.4 switching between watchdog timer mode and interval timer mode if the timer mode is switched from watchdog timer mode to interval timer mode while the wdt is operating, errors could occur in the incrementation. the watchdog timer must be stopped (by clearing the tme bit to 0) before switching the timer mode. section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 767 of 1340 rej09b0499-0200 17.6.5 internal reset in watchdog timer mode this lsi is not reset internally if tcnt ove rflows while the rste bit is cleared to 0 during watchdog timer mode operation, but tcnt and tcsr of the wdt are reset. tcnt, tcsr, and rstcr cannot be written to while the wdtovf signal is low. also note that a read of the wovf flag is not recognized during this period. to clear th e wovf flag, therefore, read tcsr after the wdtovf signal goes high, then write 0 to the wovf flag. 17.6.6 system reset by wdtovf signal if the wdtovf signal is input to the res pin, this lsi will not be initialized correctly. make sure that the wdtovf signal is not input logically to the res pin. to reset the entire system by means of the wdtovf signal, use a circuit like that shown in figure 17.6. reset input reset signal to entire system this lsi res wdtovf figure 17.6 circuit for system reset by wdtovf signal (example) 17.6.7 transition to watchdog timer mo de or software standby mode when the wdt operates in watchd og timer mode, a transition to software standby mode is not made even when the sleep instruction is executed when the ssby bit in sbycr is set to 1. instead, a transition to sleep mode is made. to transit to software standby mode, the sleep instruction must be executed after halting the wdt (clearing the tme bit to 0). when the wdt operates in interval timer mode, a transition to software standby mode is made through execution of the sleep instruction when the ssby bit in sbycr is set to 1. section 17 watchdog timer (wdt) rev. 2.00 oct. 20, 2009 page 768 of 1340 rej09b0499-0200 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 769 of 1340 rej09b0499-0200 section 18 serial communication interface (sci, irda, crc) this lsi has six independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. asynchronous serial data communication can be carried out with standard asynchronous communi cation chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). a func tion is also provided for se rial communication between processors (multiprocessor communication function). the sci also supports the smart card (smart card) interface supporting iso/ iec 7816-3 (identification card) as an extended asynchronous communication mode. sci_5 enables transmitting and receiving irda communication waveform based on the irda specifications version 1.0. this lsi incorporates the on-chip crc (cyclic redundancy check) computing unit that realizes high reliability of high-speed data transfer. since the crc computing unit is not connected to sci, operation is executed by writing data to registers. figure 18.1 shows a block diagram of the sci_0 to sci_4. figure 18.2 shows a block diagram of the sci_5 and sci_6. 18.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected the external clock can be selected as a tran sfer clock source (except for the smart card interface). ? choice of lsb-first or msb-first transfer (except in the case of asynchronous mode 7-bit data) ? four interrupt sources the interrupt sources are tran smit-end, transmit-data-empty, receive-data-full, and receive error. the transmit-data-empty and receive-data-full interrupt so urces can activate the dtc or dmac. ? module stop state specifiable section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 770 of 1340 rej09b0499-0200 asynchronous mode (sci_0, 1, 2, 4, 5, and 6): ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by r eading the rxd pin level directly in case of a framing error ? enables average transfer rate cloc k input from tmr (sci_5, sci_6) ? average transfer rate generator (sci_2) 10.667-mhz operation: 115.192 kbps or 460.784 kbps can be selected 16-mhz operation: 115.192 kbps, 460.784 kbps, or 720 kbps can be selected 32-mhz operation: 720 kbps ? average transfer rate generator (sci_5, sci_6) 8-mhz operation: 460.784 kbps can be selected 10.667-mhz operation: 115.152 kbps or 460.606 kbps can be selected 12-mhz operation: 230.263 kbps or 460.526 kbps can be selected 16-mhz operation: 115.196 kbps, 460.784 kbps, 720 kbps, or 921.569 kbps can be selected 24-mhz operation: 115.132 kbps, 460.526 kbps, 720 kbps, or 921.053 kbps can be selected 32-mhz operation: 720 kbps can be selected clocked synchronous mode (sci_0, 1, 2, and 4): ? data length: 8 bits ? receive error detecti on: overrun errors smart card interface: ? an error signal can be automatically transmitted on detection of a parity error during reception ? data can be automatically re-transmitted on r eceiving an error signal during transmission ? both direct convention and inverse convention are supported section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 771 of 1340 rej09b0499-0200 table 18.1 lists the func tions of each channel. table 18.1 function list of sci channels sci_0, 1, 4 sci_2 sci_5, sci_6 clocked synchronous mode o o ? asynchronous mode o o o tmr clock input ? ? o p = 8 mhz ? ? 460.784 kbps p = 10.667 mhz ? 460.784 kbps 115.192 kbps 460.606 kbps 115.152 kbps p = 12 mhz ? ? 460.526 kbps 230.263 kbps p = 16 mhz ? 720 kbps 460 784kbps 115.192 kbps 921.569 kbps 720 kbps 460.784 kbps 115.196 kbps p = 24 mhz ? ? 921.053 kbps 720 kbps 460.526 kbps 115.132 kbps when average transfer rate generator is used p = 32 mhz ? 720 kbps 720 kbps section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 772 of 1340 rej09b0499-0200 rxd txd sck clock p p /4 p /16 p /64 tei txi rxi eri scmr ssr scr smr semr transmission/ reception control baud rate generator brr module data bus rdr tsr rsr parity generation parity check [legend] rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register tdr bus interface internal data bus external clock scr: serial control register ssr: serial status register scmr: smart card mode register brr: bit rate register semr: serial extended mode register (available only for sci_2) average transfer rate generator (sci_2) at 10.667-mhz operation: 115.192 kbps 460.784 kbps at 16-mhz operation: 115.192 kbps 460.784 kbps 720 kbps at 32-mhz operation: 720 kbps figure 18.1 block diagram of sci_0, 1, 2, and 4 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 773 of 1340 rej09b0499-0200 rxd0 txd0 clock p p /4 p /16 p /64 tei txi rxi eri scmr ssr scr ircr * transmission/ reception control baud rate generator brr tmr tmo4, 6 tmo5, 7 module data bus rdr tsr rsr parity generation parity check [legend] rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register scmr: smart card mode register brr: bit rate register semr: serial extended mode register ircr: irda control register (available only for sci_5) note: * scl_5 only. tdr bus interface internal data bus average transfer rate generator at 8-mhz operation: 460.784 kbps at 10.667-mhz operation: 115.152 kbps 460.606 kbps at 12-mhz operation: 230.263 kbps 460.526 kbps at 16-mhz operation: 115.196 kbps 460.784 kbps 720 kbps, 921.569 kbps at 24-mhz operation: 115.132 kbps 460.526 kbps 720 kbps 921.053 kbps at 32-mhz operation: 720 kbps figure 18.2 block diagram of sci_5 and sci_6 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 774 of 1340 rej09b0499-0200 18.2 input/output pins table 18.2 lists the pin configuration of the sci. table 18.2 pin configuration channel pin name * i/o function sck0 i/o channel 0 clock input/output rxd0 input channel 0 receive data input 0 txd0 output channel 0 transmit data output sck1 i/o channel 1 clock input/output rxd1 input channel 1 receive data input 1 txd1 output channel 1 transmit data output sck2 i/o channel 2 clock input/output rxd2 input channel 2 receive data input 2 txd2 output channel 2 transmit data output sck4 i/o channel 4 clock input/output rxd4 input channel 4 receive data input 4 txd4 output channel 4 transmit data output rxd5/irrxd input channel 5 receive data input 5 txd5/irtxd output channel 5 transmit data output rxd6 input channel 6 receive data input 6 txd6 output channel 6 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 775 of 1340 rej09b0499-0200 18.3 register descriptions the sci has the following registers. some bits in the serial mode register (smr), serial status register (ssr), and serial control register (scr) have different functions in different modes ? normal serial communi cation interface mode and smart card interface mode; therefore, the bits are described separately for each mo de in the corresponding register sections. channel 0: ? receive shift register_0 (rsr_0) ? transmit shift register_0 (tsr_0) ? receive data register_0 (rdr_0) ? transmit data register_0 (tdr_0) ? serial mode register_0 (smr_0) ? serial control register_0 (scr_0) ? serial status re gister_0 (ssr_0) ? smart card mode register_0 (scmr_0) ? bit rate register_0 (brr_0) channel 1: ? receive shift register_1 (rsr_1) ? transmit shift register_1 (tsr_1) ? receive data register_1 (rdr_1) ? transmit data register_1 (tdr_1) ? serial mode register_1 (smr_1) ? serial control register_1 (scr_1) ? serial status re gister_1 (ssr_1) ? smart card mode register_1 (scmr_1) ? bit rate register_1 (brr_1) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 776 of 1340 rej09b0499-0200 channel 2: ? receive shift register_2 (rsr_2) ? transmit shift register_2 (tsr_2) ? receive data register_2 (rdr_2) ? transmit data register_2 (tdr_2) ? serial mode register_2 (smr_2) ? serial control register_2 (scr_2) ? serial status re gister_2 (ssr_2) ? smart card mode register_2 (scmr_2) ? bit rate register_2 (brr_2) ? serial extended mode register_2 (semr_2) channel 4: ? receive shift register_4 (rsr_4) ? transmit shift register_4 (tsr_4) ? receive data register_4 (rdr_4) ? transmit data register_4 (tdr_4) ? serial mode register_4 (smr_4) ? serial control register_4 (scr_4) ? serial status re gister_4 (ssr_4) ? smart card mode register_4 (scmr_4) ? bit rate register_4 (brr_4) channel 5: ? receive shift register_5 (rsr_5) ? transmit shift register_5 (tsr_5) ? receive data register_5 (rdr_5) ? transmit data register_5 (tdr_5) ? serial mode register_5 (smr_5) ? serial control register_5 (scr_5) ? serial status re gister_5 (ssr_5) ? smart card mode register_5 (scmr_5) ? bit rate register_5 (brr_5) ? serial extended mode register_5 (semr_5) ? irda control register_5 (ircr) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 777 of 1340 rej09b0499-0200 channel 6: ? receive shift register_6 (rsr_6) ? transmit shift register_6 (tsr_6) ? receive data register_6 (rdr_6) ? transmit data register_6 (tdr_6) ? serial mode register_6 (smr_6) ? serial control register_6 (scr_6) ? serial status re gister_6 (ssr_6) ? smart card mode register_6 (scmr_6) ? bit rate register_6 (brr_6) ? serial extended mode register_6 (semr_6) 18.3.1 receive shift register (rsr) rsr is a shift register which is used to receive se rial data input from the rxd pin and converts it into parallel data. when one frame of data has been received, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 18.3.2 receive data register (rdr) rdr is an 8-bit register that stores receive da ta. when the sci has received one frame of serial data, it transfers the received serial data from rsr to rdr where it is stored. this allows rsr to receive the next data. since rsr and rdr function as a double buffer in this way, continuous receive operations can be performed . after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. bit bit name initial value r/w 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 778 of 1340 rej09b0499-0200 18.3.3 transmit data register (tdr) tdr is an 8-bit register that stores transmit data. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to ts r and starts transmission. the double-buffered structures of tdr and tsr enable continuous seri al transmission. if the next transmit data has already been written to tdr when one frame of da ta is transmitted, the sc i transfers the written data to tsr to continue transmission. although tdr can be read from or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr for only once after confirming that the tdre bit in ssr is set to 1. bit bit name initial value r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 18.3.4 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first automatically transfers transmit data from tdr to tsr, and then sends the data to the txd pin. tsr cannot be directly accessed by the cpu. 18.3.5 serial mode register (smr) smr is used to set the sci's serial transfer format and select the baud rate generator clock source. some bits in smr have different functions in normal mode and smart card interface mode. ? when smif in scmr = 0 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit name initial value r/w ? when smif in scmr = 1 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 bcp1 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit name initial value r/w section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 779 of 1340 rej09b0499-0200 bit functions in normal serial communication interface mode (when smif in scmr = 0): bit bit name initial value r/w description 7 c/ a 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode * 6 chr 0 r/w character length (valid only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. lsb-first is fixed and the msb (bit 7) in tdr is not transmitted in transmission. in clocked synchronous mode, a fixed data length of 8 bits is used. 5 pe 0 r/w parity enable (valid only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. for a multiprocessor format, parity bit addition and checking are not performed regardless of the pe bit setting. 4 o/ e 0 r/w parity mode (valid only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3 stop 0 r/w stop bit length (valid only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked. if the second stop bit is 0, it is tr eated as the start bit of the next transmit frame. 2 mp 0 r/w multiprocessor mode (valid only in asynchronous mode) when this bit is set to 1, the multiprocessor function is enabled. the pe bit and o/ e bit settings are invalid in multiprocessor mode. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 780 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 1, 0 these bits select the clock source for the baud rate generator. 00: p clock (n = 0) 01: p /4 clock (n = 1) 10: p /16 clock (n = 2) 11: p /64 clock (n = 3) for the relation between the se ttings of these bits and the baud rate, see section 18.3.9, bit rate register (brr). n is the decimal display of the value of n in brr (see section 18.3.9, bit ra te register (brr)). note: * available in sci_0, 1, 2, and 4 only. setting is prohibited in sci_5 and sci_6. bit functions in smart card interface mode (when smif in scmr = 1): bit bit name initial value r/w description 7 gm 0 r/w gsm mode setting this bit to 1 allows gsm mode operation. in gsm mode, the tend set timing is put forward to 11.0 etu from the start and the clock output control function is appended. for details, see sections 18.7.6, data transmission (except in block transfer mode) and 18.7.8, clock output control (only sci_0, 1, 2, and 4). 6 blk 0 r/w setting this bit to 1 allows block transfer mode operation. for details, see section 18.7.3, block transfer mode. 5 pe 0 r/w parity enable (valid only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. set this bit to 1 in smart card interface mode. 4 o/ e 0 r/w parity mode (valid only when the pe bit is 1 in asynchronous mode) 0: selects even parity 1: selects odd parity for details on the usage of this bit in smart card interface mode, see section 18.7.2, data format (except in block transfer mode). section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 781 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 2 bcp1 bcp0 0 0 r/w r/w base clock pulse 1, 0 these bits select the number of base clock cycles in a 1- bit data transfer time in smart card interface mode. 00: 32 clock cycles (s = 32) 01: 64 clock cycles (s = 64) 10: 372 clock cycles (s = 372) 11: 256 clock cycles (s = 256) for details, see section 18.7.4, receive data sampling timing and reception margin. s is described in section 18.3.9, bit rate register (brr). 1 0 cks1 cks0 0 0 r/w r/w clock select 1, 0 these bits select the clock source for the baud rate generator. 00: p clock (n = 0) 01: p /4 clock (n = 1) 10: p /16 clock (n = 2) 11: p /64 clock (n = 3) for the relation between the se ttings of these bits and the baud rate, see section 18.3.9, bit rate register (brr). n is the decimal display of the value of n in brr (see section 18.3.9, bit ra te register (brr)). note: etu (elementary time unit): 1-bit transfer time section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 782 of 1340 rej09b0499-0200 18.3.6 serial control register (scr) scr is a register that enables/disables the follow ing sci transfer operations and interrupt requests, and selects the transfer clock source. for details on interrupt requests, see section 18.9, interrupt sources. some bits in scr have different functions in normal mode and smart card interface mode. ? when smif in scmr = 0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w bit bit name initial value r/w ? when smif in scmr = 1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w bit bit name initial value r/w ? bit functions in normal serial communicatio n interface mode (when smif in scmr = 0): bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, a txi interrupt request is enabled. a txi interrupt request can be cancelled by reading 1 from the tdre flag and then clearing the flag to 0, or by clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt requests can be cancelled by reading 1 from the rdrf, fer, per, or orer flag and then clearing the flag to 0, or by clearing the rie bit to 0. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 783 of 1340 rej09b0499-0200 bit bit name initial value r/w description 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. under this condition, serial transmi ssion is started by writing transmit data to tdr, and clearing the tdre flag in ssr to 0. note that smr should be set prior to setting the te bit to 1 in order to desig nate the transmission format. if transmission is halted by clearing this bit to 0, the tdre flag in ssr is fixed to 1. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. note that smr should be set prior to setting the re bit to 1 in order to designate the reception format. even if reception is halted by clearing this bit to 0, the rdrf, fer, per, and orer flags are not affected and the previous value is retained. 3 mpie 0 r/w multiprocessor interrupt enable (valid only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and orer status flags in ssr is disabled. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, see se ction 18.5, multiprocessor communication function. when receive data including mpb = 0 in ssr is being received, transfer of the received data from rsr to rdr, detection of reception errors, and the settings of rdrf, fer, and orer flags in ssr are not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is automatically cleared to 0, and rxi and eri interrupt requests (in the case where the tie and rie bits in scr are set to 1) and setting of the fer and orer flags are enabled. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 784 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, a tei interrupt request is enabled. a tei interrupt request can be cancelled by reading 1 from the tdre flag and then clearing the flag to 0 in order to clear the tend flag to 0, or by clearing the teie bit to 0. 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 (for sci_0, 1, and 4) these bits select the clock source and sck pin function. ? asynchronous mode 00: on-chip baud rate generator the sck pin functions as i/o port. 01: on-chip baud rate generator the clock with the same frequency as the bit rate is output from the sck pin. 1x: external clock the clock with a frequency 16 times the bit rate should be input from the sck pin. ? clocked synchronous mode 0x: internal clock the sck pin functions as the clock output pin. 1x: external clock the sck pin functions as the clock input pin. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 785 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 (for sci_2) these bits select the clock source and sck pin function. ? asynchronous mode 00: on-chip baud rate generator the sck pin functions as i/o port. 01: on-chip baud rate generator the clock with the same frequency as the bit rate is output from the sck pin. 1x: external clock or average transfer rate generator when an external clock is used, the clock with a frequency 16 times the bit rate should be input from the sck pin. when an average transfer rate generator is used. ? clocked synchronous mode 0x: internal clock the sck pin functions as the clock output pin. 1x: external clock the sck pin functions as the clock input pin. 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 (for sci_5 and sci_6) these bits select the clock source. ? asynchronous mode 00: on-chip baud rate generator 1x: tmr clock input or average transfer rate generator when an average transfer rate generator is used. when tmr clock input is used. ? clocked synchronous mode not available [legend] x: don't care section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 786 of 1340 rej09b0499-0200 ? bit functions in smart card interface mode (when smif in scmr = 1): bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1,a txi interrupt request is enabled. a txi interrupt request can be cancelled by reading 1 from the tdre flag and then clearing the flag to 0, or by clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt requests can be cancelled by reading 1 from the rdrf, fer, per, or orer flag and then clearing the flag to 0, or by clearing the rie bit to 0. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. under this condition, serial transmi ssion is started by writing transmit data to tdr, and clearing the tdre flag in ssr to 0. note that smr should be set prior to setting the te bit to 1 in order to desig nate the transmission format. if transmission is halted by clearing this bit to 0, the tdre flag in ssr is fixed 1. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. note that smr should be set prior to setting the re bit to 1 in order to designate the reception format. even if reception is halted by clearing this bit to 0, the rdrf, fer, per, and orer flags are not affected and the previous value is retained. 3 mpie 0 r/w multiprocessor interrupt enable (valid only when the mp bit in smr is 1 in asynchronous mode) write 0 to this bit in smart card interface mode. 2 teie 0 r/w transmit end interrupt enable write 0 to this bit in smart card interface mode. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 787 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 * these bits control the clock output from the sck pin. in gsm mode, clock output can be dynamically switched. for details, see section 18.7.8, clock output control (only sci_0, 1, 2, and 4). ? when gm in smr = 0 00: output disabled (sck pin functions as i/o port.) * 01: clock output 1x: reserved ? when gm in smr = 1 00: output fixed low 01: clock output 10: output fixed high 11: clock output note: * no sck pins exist in sci_5 and sci_6. 18.3.7 serial status register (ssr) ssr is a register containing status flags of th e sci and multiprocessor bi ts for transfer. tdre, rdrf, orer, per, and fer can only be cleared. some bits in ssr have different functions in normal mode and smart card interface mode. ? when smif in scmr = 0 bit bit name initial value r/w 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w note: * only 0 can be written, to clear the flag. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 788 of 1340 rej09b0499-0200 ? when smif in scmr = 1 bit bit name initial value r/w 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w note: * only 0 can be written, to clear the flag. bit functions in normal serial communication interface mode (when smif in scmr = 0): bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when a txi interrupt request is issued allowing dmac or dtc to write data to tdr section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 789 of 1340 rej09b0499-0200 bit bit name initial value r/w description 6 rdrf 0 r/(w) * receive data register full indicates whether receive data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when an rxi interrupt request is issued allowing dmac or dtc to read data from rdr the rdrf flag is not affected and retains its previous value when the re bit in scr is cleared to 0. note that when the next serial reception is completed while the rdrf flag is being set to 1, an overrun error occurs and the received data is lost. 5 orer 0 r/(w) * overrun error indicates that an overrun error has occurred during reception and the reception ends abnormally. [setting condition] ? when the next serial reception is completed while rdrf = 1 in rdr, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. when the orer flag is set to 1, subsequent serial reception cannot be performed. note that, in clocked synchronous mode, serial transmission also cannot continue. [clearing condition] ? when 0 is written to orer after reading orer = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the orer flag is not affected and retains its previous value. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 790 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 fer 0 r/(w) * framing error indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [setting condition] ? when the stop bit is 0 in 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the seco nd stop bit is not checked. note that receive data when the framing error occurs is transferred to rdr, however, the rdrf flag is not set. in addition, when the fer flag is being set to 1, the subsequent serial rece ption cannot be performed. in clocked synchronous mode, serial transmission also cannot continue. [clearing condition] ? when 0 is written to fer after reading fer = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the fer flag is not affected and retains its previous value. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 791 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 per 0 r/(w) * parity error indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [setting condition] ? when a parity error is detected during reception receive data when the parity error occurs is transferred to rdr, however, the rdrf flag is not set. note that when the per flag is being set to 1, the subsequent serial reception cannot be performed. in clocked synchronous mode, serial transmission also cannot continue. [clearing condition] ? when 0 is written to per after reading per = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the per bit is not affected and retains its previous value. 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when a txi interrupt request is issued allowing dmac or dtc to write data to tdr 1 mpb 0 r multiprocessor bit stores the multiprocessor bit value in the receive frame. when the re bit in scr is cleared to 0 its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer sets the multiprocessor bit value to be added to the transmit frame. note: * only 0 can be written, to clear the flag. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 792 of 1340 rej09b0499-0200 bit functions in smart card interface mode (when smif in scmr = 1): bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when a txi interrupt request is issued allowing dmac or dtc to write data to tdr 6 rdrf 0 r/(w) * receive data register full indicates whether receive data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when an rxi interrupt request is issued allowing dmac or dtc to read data from rdr the rdrf flag is not affected and retains its previous value even when the re bit in scr is cleared to 0. note that when the next reception is completed while the rdrf flag is being set to 1, an overrun error occurs and the received data is lost. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 793 of 1340 rej09b0499-0200 bit bit name initial value r/w description 5 orer 0 r/(w) * overrun error indicates that an overrun error has occurred during reception and the reception ends abnormally. [setting condition] ? when the next serial reception is completed while rdrf = 1 in rdr, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. when the orer flag is set to 1, subsequent serial reception cannot be performed. note that, in clocked synchronous mode, serial transmission also cannot continue. [clearing condition] ? when 0 is written to orer after reading orer = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the orer flag is not affected and retains its previous value. 4 ers 0 r/(w) * error signal status [setting condition] ? when a low error signal is sampled [clearing condition] ? when 0 is written to ers after reading ers = 1 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 794 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 per 0 r/(w) * parity error indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [setting condition] ? when a parity error is detected during reception receive data when the parity error occurs is transferred to rdr, however, the rdrf flag is not set. note that when the per flag is being set to 1, the subsequent serial reception cannot be performed. in clocked synchronous mode, serial transmission also cannot continue. [clearing condition] ? when 0 is written to per after reading per = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the per flag is not affected and retains its previous value. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 795 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 tend 1 r transmit end this bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to tdr. [setting conditions] ? when both the te and ers bits in scr are 0 ? when ers = 0 and tdre = 1 after a specified time passed after completion of 1-byte data transfer. the set timing depends on the register setting as follows: when gm = 0 and blk = 0, 2.5 etu after transmission start when gm = 0 and blk = 1, 1.5 etu after transmission start when gm = 1 and blk = 0, 1.0 etu after transmission start when gm = 1 and blk = 1, 1.0 etu after transmission start [clearing conditions] ? when 0 is written to tend after reading tend = 1 ? when a txi interrupt request is issued allowing dmac or dtc to write the next data to tdr 1 mpb 0 r multiprocessor bit not used in smart card interface mode. 0 mpbt 0 r/w multiprocessor bit transfer write 0 to this bit in smart card interface mode. note: * only 0 can be written, to clear the flag. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 796 of 1340 rej09b0499-0200 18.3.8 smart card mode register (scmr) scmr selects smart card interface mode and its format. 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 1 ? 1 ? bit bit name initial value r/w 3 sdir 0 r/w 2 sinv 0 r/w 0 smif 0 r/w bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 sdir 0 r/w smart card data transfer direction selects the serial/parallel conversion format. 0: transfer with lsb-first 1: transfer with msb-first this bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with lsb-first. 2 sinv 0 r/w smart card data invert inverts the transmit/receive data logic level. this bit does not affect the logic level of the parity bit. to invert the parity bit, invert the o/ e bit in smr. 0: tdr contents are transmitt ed as they are. receive data is stored as it is in rdr. 1: tdr contents are inverted before being transmitted. receive data is stored in inverted form in rdr. 1 ? 1 ? reserved this bit is always read as 1. 0 smif 0 r/w smart card interface mode select when this bit is set to 1, smart card interface mode is selected. 0: normal asynchronous or clocked synchronous mode 1: smart card interface mode section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 797 of 1340 rej09b0499-0200 18.3.9 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rates can be set for each channel. table 18.3 shows the relationships between the n setting in brr and bit rate b for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. the initial value of brr is h'ff, and it can be read from or written to by the cpu at all times. table 18.3 relationships between n setting in brr and bit rate b mode abcs bit bit rate error 0 n = ? 1 64 2 b 2n ? 1 p 10 6 error (%) = { ? 1 } 100 b 64 2 (n + 1) 2n ? 1 p 10 6 asynchronous mode 1 n = ? 1 32 2 b 2n ? 1 p 10 6 error (%) = { ? 1 } 100 b 32 2 (n + 1) 2n ? 1 p 10 6 clocked synchronous mode n = ? 1 8 2 b 2n ? 1 p 10 6 smart card interface mode n = ? 1 s 2 b p 10 6 2n + 1 error (%) = b s 2 (n + 1) ? 1 100 2n + 1 p 10 6 { } [legend] b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) p : operating frequency (mhz) n and s: determined by the smr settings shown in the following table. smr setting smr setting cks1 cks0 n bcp1 bcp0 s 0 0 0 0 0 32 0 1 1 0 1 64 1 0 2 1 0 372 1 1 3 1 1 256 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 798 of 1340 rej09b0499-0200 table 18.4 shows sample n settings in brr in normal asynchronous mode. table 18.5 shows the maximum bit rate settable for each operating freque ncy. tables 18.7 and 18.9 show sample n settings in brr in clocked sync hronous mode and smart card in terface mode, respectively. in smart card interface mode, the number of base clock cycles s in a 1-bit data transfer time can be selected. for details, see sectio n 18.7.4, receive data sampling timing and reception margin. tables 18.6 and 18.8 show the maximum bit rates with external clock input. when the abcs bit in the serial extended mode register_2, 5, and 6 (semr_2, 5, and 6) of sci_2, 5, and 6 are set to 1 in asynchronous mode, the bit rate is two times that of shown in table 18.4. table 18.4 examples of brr settings for various bit rates (asynchronous mode) (1) operating frequency p (mhz) 8 9.8304 10 12 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 141 0.03 2 174 ?0.26 2 177 ?0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 ?1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 ?2.34 31250 0 7 0.00 0 9 ?1.70 0 9 0.00 0 11 0.00 38400 ? ? ? 0 7 0.00 0 7 1.73 0 9 ?2.34 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 799 of 1340 rej09b0499-0200 operating frequency p (mhz) 12.288 14 14.7456 16 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 217 0.08 2 248 ?0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 ?0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 ?0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 ?1.70 0 15 0.00 38400 0 9 0.00 ? ? ? 0 11 0.00 0 12 0.16 note: in sci_2, 5, and 6, this is an example when the abcs bit in semr_2, 5, and 6 is 0. when the abcs bit is set to 1, the bit rate is two times. table 18.4 examples of brr settings for various bit rates (asynchronous mode) (2) operating frequency p (mhz) 17.2032 18 19.6608 20 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 3 75 0.48 3 79 ?0.12 3 86 0.31 3 88 ?0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.00 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 111 0.00 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 55 0.00 0 58 ?0.69 0 63 0.00 0 64 0.16 19200 0 27 0.00 0 28 1.02 0 31 0.00 0 32 ?1.36 31250 0 16 1.20 0 17 0.00 0 19 ?1.70 0 19 0.00 38400 0 13 0.00 0 14 ?2.34 0 15 0.00 0 15 1.73 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 800 of 1340 rej09b0499-0200 operating frequency p (mhz) 25 30 33 35 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 3 110 ?0.02 3 132 0.13 3 145 0.33 3 154 0.23 150 3 80 ?0.47 3 97 ?0.35 3 106 0.39 3 113 ?0.06 300 2 162 0.15 2 194 0.16 2 214 ?0.07 2 227 ?0.06 600 2 80 ?0.47 2 97 ?0.35 2 106 0.39 2 113 ?0.06 1200 1 162 0.15 1 194 0.16 1 214 ?0.07 1 227 ?0.06 2400 1 80 ?0.47 1 97 ?0.35 1 106 0.39 1 113 ?0.06 4800 0 162 0.15 0 194 0.16 0 214 ?0.07 0 227 ?0.06 9600 0 80 ?0.47 0 97 ?0.35 0 106 0.39 0 113 ?0.06 19200 0 40 ?0.76 0 48 ?0.35 0 53 ?0.54 0 56 ?0.06 31250 0 24 0.00 0 29 0 0 32 0 0 34 0.00 38400 0 19 1.73 0 23 1.73 0 26 ?0.54 0 27 1.73 note: in sci_2, 5, and 6, this is an example when the abcs bit in semr_2, 5, and 6 is 0. when the abcs bit is set to 1, the bit rate is two times. table 18.5 maximum bit rate for each operating frequency (asynchronous mode) p (mhz) maximum bit rate (bit/s) n n p (mhz) maximum bit rate (bit/s) n n 8 250000 0 0 17.2032 537600 0 0 9.8304 307200 0 0 18 562500 0 0 10 312500 0 0 19.6608 614400 0 0 12 375000 0 0 20 625000 0 0 12.288 384000 0 0 25 781250 0 0 14 437500 0 0 30 937500 0 0 14.7456 460800 0 0 33 1031250 0 0 16 500000 0 0 35 1093750 0 0 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 801 of 1340 rej09b0499-0200 table 18.6 maximum bit rate with external clock input (asynchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bit/s) p (mhz) external input clock (mhz) maximum bit rate (bit/s) 8 2.0000 125000 17.2032 4.3008 268800 9.8304 2.4576 153600 18 4.5000 281250 10 2.5000 156250 19.6608 4.9152 307200 12 3.0000 187500 20 5.0000 312500 12.288 3.0720 192000 25 6.2500 390625 14 3.5000 218750 30 7.5000 468750 14.7456 3.6864 230400 33 8.2500 515625 16 4.0000 250000 35 8.7500 546875 note: in sci_2, this is an example when the abcs bit in semr_2 is 0. when the abcs bit is set to 1, the bit rate is two times. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 802 of 1340 rej09b0499-0200 table 18.7 brr settings for various bit rates (clocked synchronous mode) * 2 operating frequency p (mhz) 8 10 16 20 25 30 33 35 bit rate (bit/s) n n n n n n n n n n n n n n n n 110 250 3 124 ? ? 3 249 500 2 249 ? ? 3 124 ? ? 3 233 1k 2 124 ? ? 2 249 ? ? 3 97 3 116 3 128 3 136 2.5k 1 199 1 249 2 99 2 124 2 155 2 187 2 205 2 218 5k 1 99 1 124 1 199 1 249 2 77 2 93 2 102 2 108 10k 0 199 0 249 1 99 1 124 1 155 1 187 1 205 1 218 25k 0 79 0 99 0 159 0 199 0 249 1 74 1 82 1 87 50k 0 39 0 49 0 79 0 99 0 124 0 149 0 164 0 174 100k 0 19 0 24 0 39 0 49 0 62 0 74 0 82 0 87 250k 0 7 0 9 0 15 0 19 0 24 0 29 0 32 0 34 500k 0 3 0 4 0 7 0 9 ? ? 0 14 ? ? ? ? 1m 0 1 0 3 0 4 ? ? ? ? ? ? ? ? 2.5m 0 0 * 1 0 1 ? ? 0 2 ? ? ? ? 5m 0 0 * 1 ? ? ? ? ? ? ? ? [legend] space: setting prohibited. ? : can be set, but there will be error. notes: 1. continuous transmission or reception is not possible. 2. no clocked synchronous mode exists in sci_5 and sci_6. table 18.8 maximum bit rate with external clock input (clocked synchronous mode) * p (mhz) external input clock (mhz) maximum bit rate (bit/s) p (mhz) external input clock (mhz) maximum bit rate (bit/s) 8 1.3333 1333333.3 20 3.3333 3333333.3 10 1.6667 1666666.7 25 4.1667 4166666.7 12 2.0000 2000000.0 30 5.0000 5000000.0 14 2.3333 2333333.3 33 5.5000 5500000.0 16 2.6667 2666666.7 35 5.8336 5833625.0 18 3.0000 3000000.0 note * no clocked synchronous mode exists in sci_5 and sci_6. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 803 of 1340 rej09b0499-0200 table 18.9 brr settings for various bit rate s (smart card interface mode, n = 0, s = 372) operating frequency p (mhz) 7.1424 10.00 10.7136 13.00 bit rate (bit/sec) n n error (%) n n error (%) n n error (%) n n error (%) 9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99 operating frequency p (mhz) 14.2848 16.00 18.00 20.00 bit rate (bit/sec) n n error (%) n n error (%) n n error (%) n n error (%) 9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.66 operating frequency p (mhz) 25.00 30.00 33.00 35.00 bit rate (bit/sec) n n error (%) n n error (%) n n error (%) n n error (%) 9600 0 3 12.49 0 3 5.01 0 4 7.59 0 4 1.99 table 18.10 maximum bit rate for each op erating frequency (smart card interface mode, s = 372) p (mhz) maximum bit rate (bit/s) n n p (mhz) maximum bit rate (bit/s) n n 7.1424 9600 0 0 18.00 24194 0 0 10.00 13441 0 0 20.00 26882 0 0 10.7136 14400 0 0 25.00 33602 0 0 13.00 17473 0 0 30.00 40323 0 0 14.2848 19200 0 0 33.00 44355 0 0 16.00 21505 0 0 35.00 47043 0 0 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 804 of 1340 rej09b0499-0200 18.3.10 serial extended mode register (semr_2) semr_2 selects the clock source in asynchronous mode of sci_2. the base clock is automatically specified when the average transfer rate operation is selected. 7 ? undefined r 6 ? undefined r 5 ? undefined r 4 ? undefined r bit bit name initial value r/w 3 abcs 0 r/w 2 acs2 0 r/w 1 acs1 0 r/w 0 acs0 0 r/w bit bit name initial value r/w description 7 to 4 ? undefined r reserved these bits are always read as undefined and cannot be modified. 3 abcs 0 r/w asynchronous mode base clock select (valid only in asynchronous mode) selects the base clock for a 1-bit period. 0: the base clock has a frequency 16 times the transfer rate 1: the base clock has a frequency 8 times the transfer rate section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 805 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 1 0 acs2 acs1 acs0 0 0 0 r/w r/w r/w asynchronous mode clock source select (valid when cke1 = 1 in asynchronous mode) these bits select the clock source for the average transfer rate function. when the average transfer rate function is enabled, the base clock is automatically specified regardless of the abcs bit value. 000: external clock input 001: 115.192 kbps of average transfer rate specific to p = 10.667 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 010: 460.784 kbps of average transfer rate specific to p = 10.667 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 011: 720 kbps of average transfer rate specific to p = 32 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 100: setting prohibited 101: 115.192 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 110: 460.784 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 111: 720 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) the average transfer rate only supports operating frequencies of 10.667 mhz, 16 mhz, and 32 mhz. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 806 of 1340 rej09b0499-0200 18.3.11 serial extended mode register 5 and 6 (semr_5 and semr_6) semr_5 and semr_6 select the clock source in asynchronous mode of sci_5 and sci_6. the base clock is automatically specified when the average transfer rate operation is selected. tmo output in tmr unit 2 and unit 3 can also be set as the serial transfer base clock. figure 18.3 describes the examples of base clock features when the average transfer rate operation is selected. figure 18.4 describes the examples of base clock features when the tmo output in tmr is selected. 7 ? undefined r 6 ? undefined r 5 ? undefined r 4 abcs 0 r/w bit bit name initial value r/w 3 acs3 0 r/w 2 acs2 0 r/w 1 acs1 0 r/w 0 acs0 0 r/w bit bit name initial value r/w description 7 to 5 ? undefined r reserved these bits are always read as undefined and cannot be modified. 4 abcs 0 r/w asynchronous mode base clock select (valid only in asynchronous mode) selects the base clock for a 1-bit period. 0: the base clock has a frequency 16 times the transfer rate 1: the base clock has a frequency 8 times the transfer rate 3 2 1 0 acs3 acs2 acs1 acs0 0 0 0 0 r/w r/w r/w r/w asynchronous mode clock source select these bits select the clock source for the average transfer rate function in the asynchronous mode. when the average transfer rate f unction is enabled, the base clock is automatically specified regardless of the abcs bit value. the average transfer rate only corresponds to 8mhz, 10.667mhz, 12mhz, 16mhz, 24mhz, and 32mhz. no other clock is available. setting of acs3 to acs0 must be done in the asynchronous mode (the c/ a bit in smr = 0) and the external clock input mode (the cke bit i scr = 1). the setting examples are in figures 18.3 and 18.4. (each number in the four-digit number below corresponds to the value in th e bits acs3 to acs0 from left to right respectively.) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 807 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 2 1 0 acs3 acs2 acs1 acs0 0 0 0 0 r/w r/w r/w r/w 0000: average transfer rate generator is not used. 0001: 115.152 kbps of average transfer rate specific to p = 10.667 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0010: 460.606 kbps of average transfer rate specific to p = 10.667 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 0011: 921.569 kbps of average transfer rate specific to p = 16 mhz is selected or 460.784 kbps of average transfer rate specific to p = 8mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 0100: tmr clock input this setting allows the tmr compare match output to be used as the base clock. the table below shows the correspondence between the sci channels and the compare match output. sci channel tmr unit compare match output sci_5 unit 2 tmo4, tmo5 sci_6 unit 3 tmo6, tmo7 0101: 115.196 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0110: 460.784 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0111: 720 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 808 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 2 1 0 acs3 acs2 acs1 acs0 0 0 0 0 r/w r/w r/w r/w 1000: 115.132 kbps of average transfer rate specific to p = 24 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1001: 460.526 kbps of average transfer rate specific to p = 24 mhz is selected or 230.263 kbps of average transfer rate specific to p = 12mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1010: 720 kbps of average transfer rate specific to p = 24 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 1011: 921.053 kbps of average transfer rate specific to p = 24 mhz is selected or 460.526 kbps of average transfer rate specific to p = 12mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 1100: 720 kbps of average transfer rate specific to p = 32 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1101: reserved (setting prohibited) 111x: reserved (setting prohibited) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 809 of 1340 rej09b0499-0200 1234567891011 12345678 12 13 14 15 16 17 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 28 29 5.333 mhz 3.6848 mhz 123 123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 22 4 5 6 7 8 9 10 11 12 13 14 15 16 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 28 29 2.667 mhz 1.8424 mhz base clock 10.667 mhz/2 = 5.333 mhz 5.333 mhz (38/55) = 3.6848 mhz (average) 1 bit = base clock 8 * base clock with 460.606-kbps average transfer rate (acs3 to 0 = b'0010) average transfer rate = 3.6848 mhz/8 = 460.606 kbps average error with 460.6 kbps = -0.043% 1 bit = base clock 16 * base clock 10.667 mhz/4= 2.667 mhz 2.667 mhz (38/55) = 1.8424 mhz (average) when = 10.667 mhz base clock with 115.152-kbps average transfer rate (acs3 to 0 = b'0001) average transfer rate = 1.8424 mhz/16 = 115.152 kbps average error with 115.2 kbps = -0.043% note: * the length of one bit varies according to the base clock synchronization. figure 18.3 examples of base clock wh en average transfer rate is selected (1) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 810 of 1340 rej09b0499-0200 12345678910 123 45 678 11 12 13 14 15 16 17 18 19 20 21 23 22 2425 1 2 5 6 7 8 9 101112131415161718 19202122232425 34 8 mhz 7.3725 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 28 29 8 mhz 8 mhz 7.3725 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 12345678 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 28 29 5.76 mhz 123 2 mhz 1.8431 mhz 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 28 29 base clock 16 mhz/2 = 8 mhz 8 mhz (18/25) = 5.76 mhz (average) base clock with 720-kbps average transfer rate (acs3 to 0 = b'0111) average transfer rate = 5.76 mhz/8 = 720 kbps average error with 720 kbps = 0% base clock 16 mhz/2 = 8 mhz 8 mhz (47/51) = 7.3725 mhz (average) base clock with 921.569-kbps average transfer rate (acs3 to 0 = b'0011) average transfer rate = 7.3725 mhz/8 = 921.569 kbps average error with 921.6 kbps = -0.003% note: * the length of one bit varies according to the base clock synchronization. base clock 16 mhz/2 = 8 mhz 8 mhz (47/51) = 7.3725 mhz (average) 1 bit = base clock 16 * 1 bit = base clock 8 * 1 bit = base clock 8 * base clock with 460.784-kbps average transfer rate (acs3 to 0 = b'0110) average transfer rate = 7.3725 mhz/16 = 460.784 kbps average error with 460.8 kbps = -0.004% 1 bit = base clock 16 * base clock 16 mhz/8 = 2 mhz 2 mhz (47/51) = 1.8431 mhz (average) when = 16 mhz base clock with 115.196-kbps average transfer rate (acs3 to 0 = b'0101) average transfer rate = 1.8431 mhz/16 = 115.196 kbps average error with 115.2 kbps = -0.004% figure 18.3 examples of base clock wh en average transfer rate is selected (2) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 811 of 1340 rej09b0499-0200 1 2 3 4 5 6 7 8 9 101112131415161718192021 23 22 2425 1 2 5 6 7 8 9 101112131415161718 19202122232425 3 4 12 mhz 5.76 mhz 123 3 mhz 1.8421 mhz 4567891011121314151617 1 18 19 20 21 23 22 24 25 26 2 3 4 5 6 7 8 9 10 11 12 14 13 15 16 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 28 29 123 12 mhz 7.3684 mhz 4567891011121314151617 1 18 19 20 21 23 22 24 25 26 2 3 4 5 6 7 8 9 10 11 12 14 13 15 16 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 28 29 123 12 mhz 7.3684 mhz 4567891011121314151617 1 18 19 20 21 23 22 24 25 26 23 45 67 8 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 28 29 base clock 24 mhz/2 = 12 mhz 12 mhz (12/25) = 5.76 mhz (average) base clock with 720-kbps average transfer rate (acs3 to 0 = b'1010) average transfer rate = 5.76 mhz/8= 720 kbps average error with 720 kbps = 0% base clock 24 mhz/2 = 12 mhz 12 mhz (35/57) = 7.3684 mhz (average) base clock with 921.053-kbps average transfer rate (acs3 to 0 = b'1011) average transfer rate = 7.3684 mhz/8= 921.053 kbps average error with 921.6 kbps = -0.059% note: * the length of one bit varies according to the base clock synchronization. base clock 24 mhz/2 = 12 mhz 12 mhz (35/57) = 7.3684 mhz (average) 1 bit = base clock 16 * 1 bit = base clock 8 * 1 bit = base clock 8 * base clock with 460.526-kbps average transfer rate (acs3 to 0 = b'1001) average transfer rate = 7.3684 mhz/16 = 460.526 kbps average error with 921.6 kbps = -0.059% 1 bit = base clock 16 * base clock 24 mhz/8 = 3 mhz 3 mhz (35/57) = 1.8421 mhz (average) when = 24 mhz base clock with 115.132-kbps average transfer rate (acs3 to 0 = b'1000) average transfer rate =1.8421 mhz/16 = 115.132 kbps average error with 115.2 kbps = -0.059% figure 18.3 examples of base clock wh en average transfer rate is selected (3) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 812 of 1340 rej09b0499-0200 base clock tmo4 output = 4 mhz clock enable tmo5 output sck5 base clock = 4 mhz 3/4 = 3 mhz (average) 1 bit = base clock 16 average transfer rate = 3 mhz/16 = 187.5 kbps example when tmr clock input is used in sci_5 187.5-kbps average transfer rate is generated by tmr when = 32 mhz (1) tmo4 is set as a base clock and generates 4 mhz. (2) tmo5 is set as tcnt_4 compare match count and generates a clock enable multiplied by 3/4. the average transfer rate will be 3 mhz/16 = 187.5 kbps. tmr and sci settings: tcr_4 = h'09 (tcnt4 cleared by tcora_4 compare match, tcnt4 incremented at rising edge of p /2) tccr_4 = h'01 tcr_5 = h'0c (tcnt5 cleared by tcora_5 compare match, tcnt5 incremented by tcnt_4 compare match a) tccr_5 = h'00 tcsr_4 = h'09 (0 output on tcora_4 compare match, 1 output on tcorb_4 compare match) tcsr_5 = h'09 (0 output on tcora_5 compare match, 1 output on tcorb_5 compare match) tcnt_4 = tcnt_5 = 0 tcora_4 = h'03, tcorb_4 = h'01 tcora_5 = h'03, tcorb_5 = h'00 semr_5 = h'04 when sci_6 is used, set tmo6 as a base clock and tmo7 as a clock enable. clock enable base clock tmr (unit 2) tmo5 tmo4 sci_5 sck5 123412341234123412341234123 123 123 123 123 123 123 123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 4 4 mhz 3 mhz figure 18.4 example of average transf er rate setting when tmr clock is input section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 813 of 1340 rej09b0499-0200 18.3.12 irda control register (ircr) ircr selects the function of sci_5. 7 ire 0 r/w 6 ircks2 0 r/w 5 ircks1 0 r/w 4 ircks0 0 r/w bit bit name initial value r/w 3 irtxinv 0 r/w 2 irrxinv 0 r/w 1 ? 0 ? 0 ? 0 ? bit bit name initial value r/w description 7 ire 0 r/w irda enable * sets the sci_5 i/o to normal sci or irda. 0: txd5/irtxd and rxd5/irrxd pins operate as txd5 and rxd5. 1: txd5/irtxd and rxd5/irrxd pins are operate as irtxd and irrxd. 6 5 4 irck2 irck1 irck0 0 0 0 r/w r/w r/w irda clock select 2 to 0 sets the pulse width of high state at encoding the irtxd output pulse when the irda function is enabled. 000: pulse-width = b 3/16 (bit rate 3/16) 001: pulse-width = p /2 010: pulse-width = p /4 011: pulse-width = p /8 100: pulse-width = p /16 101: pulse-width = p /32 110: pulse-width = p /64 111: pulse-width = p /128 3 irtxinv 0 r/w irtx data invert this bit specifies the inversion of the logic level in irtxd output. when inversion is done, the pulse width of high state specified by the bits 6 to 4 becomes the pulse width in low state. 0: outputs the transmission data as it is as irtxd output 1: outputs the inverted transmission data as irtxd output section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 814 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 irrxinv 0 r/w irrx data invert this bit specifies the inversion of the logic level in irrxd output. when inversion is done, the pulse width of high state specified by the bits 6 to 4 becomes the pulse width in low state. 0: uses the irrxd input data as it is as receive data. 1: uses the inverted irrxd input data as receive data. 1, 0 ? all 0 ? reserved these bits are always read as 0. it should not be set to 0. note: * the irda function should be used when the abcs bit in semr_5 is set to 0 and the acs3 to acs0 bits in semr_5 are set to b'0000. 18.4 operation in asynchronous mode figure 18.5 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). in asynchronous serial comm unication, the communication line is usually held in the mark state (high level). the sci monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. insi de the sci, the transmitter and receiver are independent units, en abling full-duplex communication. both the transmitter and the receiver also have a double-buffered structure, so that data can be r ead or written during transmission or reception, enabling con tinuous data transmission and reception. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 18.5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 815 of 1340 rej09b0499-0200 18.4.1 data transfer format table 18.11 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. for details on the multiprocessor bit, see section 18.5, multiprocessor communication function. table 18.11 serial transfer formats (asynchronous mode) s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop chr pe mp stop 00 00 00 01 01 00 01 01 10 00 10 01 11 00 11 01 0? 10 0? 11 1? 10 1? 11 [legend] s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 816 of 1340 rej09b0499-0200 18.4.2 receive data sampling ti ming and receptio n margin in asynchronous mode in asynchronous mode, the sci operates on a base clock with a frequency of 16 times* the bit rate. in reception, the sci samples the falling edge of the start bit using the base clock, and performs internal synchronization. since recei ve data is sampled at the rising edge of the 8th pulse* of the base clock, data is latched at the middle of each bit, as shown in figure 18.6. thus the reception margin in asynchronous mode is determined by formula (1) below. m = | (0.5 ? ) ? (l ? 0.5) f ? (1 + f ) | 100 [%] ... formula (1) 2n 1 n | d ? 0.5 | m: reception margin n: ratio of bit rate to clock (when abcs = 0, n = 16. when abcs = 1, n = 8.) d: duty cycle of clock (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock frequency deviation [legend] assuming values of f = 0 and d = 0.5 in formula (1), the receptio n margin is determined by the formula below. m = ( 0.5 ? ) 100 [%] = 46.875% 2 16 1 however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 18.6 receive data sampling timing in asynchronous mode note: * this is an example when the abcs bit in semr_2, 5, and 6 is 0. when the abcs bit is 1, a frequency of 8 times the bit rate is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base clock. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 817 of 1340 rej09b0499-0200 18.4.3 clock either an internal clock generated by the on-chip baud rate generator or an external clock input to the sck pin can be selected as the sci's transfer clock, accor ding to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. when an external clock is input to the sck pin, the clock frequency should be 16 times the bit rate (when abcs = 0) and 8 times the bit rate (when abcs = 1). in addition, when an external clock is specified, the average transfer rate or the base clock of tmr_4 to tmr_7 can be selected by the acs3 to acs0 bits in semr_5 and semr_6. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 18.7. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 sck txd figure 18.7 phase relation between output clock and transmit data (asynchronous mode) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 818 of 1340 rej09b0499-0200 18.4.4 sci initialization (asynchronous mode) before transmitting and receiving data, first clear th e te and re bits in scr to 0, then initialize the sci as described in a sample flowchart in figure 18.8 when the op erating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the rdrf, per, fer, an d orer flags, or rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 819 of 1340 rej09b0499-0200 18.4.5 serial data transmission (asynchronous mode) figure 18.9 shows an example of the operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is cleared to 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a txi interrupt request is generated. because the txi interrup t processing routine writes the ne xt transmit data to tdr before transmission of the current transmit data has fi nished, continuous transmission can be enabled. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the next transmit data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. figure 18.10 shows a sample flowchart for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt processing routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 18.9 example of operation fo r transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 820 of 1340 rej09b0499-0200 no section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 821 of 1340 rej09b0499-0200 18.4.6 serial data reception (asynchronous mode) figure 18.11 shows an example of the operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in rs r, and checks the par ity bit and stop bit. 2. if an overrun error (when reception of the next data is completed while the rdrf flag in ssr is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error (when the stop bit is 0) is detected, the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception finishes successfu lly, the rdrf bit in ssr is se t to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interr upt processing routine reads th e receive data transferred to rdr before reception of the next receive data has finished, continuous reception can be enabled. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine rxi interrupt request generated figure 18.11 example of sci operation for reception (example with 8-bit data, parity, one stop bit) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 822 of 1340 rej09b0499-0200 table 18.12 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error flag is se t to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 18.12 shows a sample flowchart for serial data reception. table 18.12 ssr status flag s and receive data handling ssr status flag rdrf * orer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the stat e it had before data reception. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 823 of 1340 rej09b0499-0200 yes section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 824 of 1340 rej09b0499-0200 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 825 of 1340 rej09b0499-0200 18.5 multiprocessor communication function use of the multiprocessor communi cation function enables data tran sfer to be performed among a number of processors sharin g communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communicati on is carried out, each receiving station is addressed by a unique id code. the serial communi cation cycle consists of two component cycles: an id transmission cycle which sp ecifies the receiving st ation, and a data transmission cycle for the specified receiving station. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 18.13 shows an example of inte r-processor communicat ion using the multiprocessor format. the transmitting station first sends data which include s the id code of the receiving station and a multiprocessor bit set to 1. it then transmits transmit data added with a multiprocessor bit cleared to 0. the receiving statio n skips data until data with a 1 multip rocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving st ation compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci uses the mpie bit in scr to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and orer in ssr to 1 are prohibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, th e mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is invalid. all other bit settings are the same as those in no rmal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 826 of 1340 rej09b0499-0200 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) communication line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa [legend] mpb: multiprocessor bit figure 18.13 example of communica tion using multip rocessor format (transmission of data h'aa to receiving station a) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 827 of 1340 rej09b0499-0200 18.5.1 multiprocessor serial data transmission figure 18.14 shows a sample flowchart for multip rocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci operations are the same as those in asynchronous mode. no section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 828 of 1340 rej09b0499-0200 18.5.2 multiprocessor serial data reception figure 18.16 shows a sample flowchart for multiproces sor serial data reception. if the mpie bit in scr is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is tr ansferred to rdr. an rxi interrupt request is generated at this time. all other sci operations are the same as in asynchronous mode. figure 18.15 shows an example of sci operatio n for multiprocessor format reception. mpie rdr value 0d0d1 d71 1 0d0d1 d7 01 1 1 data (id1) start bit mpb stop bit start bit data (data 1) mpb stop bit data (id2) start bit stop bit start bit data (data 2) stop bit rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine if not this station's id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station's id mpie rdr value 0d0d1 d71 1 0d0d1 d7 01 1 1 mpb mpb rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine matches this station's id, so reception continues, and data is received in rxi interrupt processing routine mpie bit set to 1 again id2 (b) data matches station's id data 2 id1 mpie = 0 mpie = 0 figure 18.15 example of sc i operation for reception (example with 8-bit data, multiprocessor bit, one stop bit) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 829 of 1340 rej09b0499-0200 yes section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 830 of 1340 rej09b0499-0200 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 831 of 1340 rej09b0499-0200 18.6 operation in clocked synchronous mode (sci_0, 1, 2, and 4 only) figure 18.17 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. one character in transfer data consists of 8-bit data. in data transmission, the sci outputs data from one falling edge of the synchronization clock to the next. in data rece ption, the sci receives data in synchronization with the rising edge of the synchronization clock. after 8-bit data is output, the transmission line holds the msb output state. in clocked synchronous mode, no parity bit or multiprocessor bit is adde d. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so th at the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. (setting is prohi bited in sci_5 and sci_6.) don't care don't care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * holds a high level except during continuous transfer. figure 18.17 data format in clocke d synchronous communication (lsb-first) 18.6.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck pin can be selected, according to the setting of the cke1 and cke0 bits in scr. when the sci is operated on an internal clock, the synchronization clock is output from the sck pin. eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. note that in the case of reception only, the sync hronization clock is output until an ov errun error occurs or until the re bit is cleared to 0. (setting is prohibited in sci_5 and sci_6.) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 832 of 1340 rej09b0499-0200 18.6.2 sci initialization (clocked synchronous mode) (sci_0, 1, 2, and 4 only) before transmitting and receiving data, first clear th e te and re bits in scr to 0, then initialize the sci as described in a sample flowchart in figure 18.18. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change. when the te bit is cleared to 0, the tdre flag is set to 1. however, clearing the re bit to 0 does not initialize the rdrf, per, fer, and orer flags, or rdr. wait section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 833 of 1340 rej09b0499-0200 18.6.3 serial data transmission (clocked synchronous mode) (sci_0, 1, 2, and 4 only) figure 18.19 shows an example of the operation for transmission in clocked synchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a txi interrupt request is generated. because the txi interrup t processing routine writes the ne xt transmit data to tdr before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the txd pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. the sci checks the tdre flag at the timing for sending the last bit. 5. if the tdre flag is cleared to 0, the next tr ansmit data is transferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the txd pin retains the output state of the last bit. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. the sck pin is fixed high. figure 18.20 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (o rer, fer, or per) is set to 1. make sure to clear the receive error flags to 0 be fore starting transmission. note that clearing the re bit to 0 does not clear the receive error flags. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 834 of 1340 rej09b0499-0200 transfer direction bit 0 serial data synchronization clock 1 frame tdre tend data written to tdr and tdre flag cleared to 0 in txi interrupt processing routine txi interrupt request generated bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt request generated tei interrupt request generated figure 18.19 example of operation for transmission in clocked synchronous mode no section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 835 of 1340 rej09b0499-0200 18.6.4 serial data reception (clocked synchr onous mode) (sci_0, 1, 2, and 4 only) figure 18.21 shows an example of sci operation for reception in clocked synchronous mode. in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, an d stores the receive data in rsr. 2. if an overrun error (when reception of the next data is completed while the rdrf flag in ssr is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if reception finishes successfu lly, the rdrf bit in ssr is se t to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interr upt processing routine reads th e receive data transferred to rdr before reception of the next receive data has finished, continuous reception can be enabled. bit 7 serial data synchronization clock 1 frame rdrf orer eri interrupt request generated by overrun error rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine rxi interrupt request generated bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 figure 18.21 example of operation for reception in clocked synchronous mode transfer cannot be resumed while a receive error flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming r eception. figure 18.22 shows a sample flowchart for serial data reception. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 836 of 1340 rej09b0499-0200 yes section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 837 of 1340 rej09b0499-0200 yes section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 838 of 1340 rej09b0499-0200 18.7 operation in smart card interface mode the sci supports the smart card interface, sup porting the iso/ie c 7816-3 (identification card) standard, as an extended serial communication interf ace function. smart card interface mode can be selected using the appropriate register. 18.7.1 sample connection figure 18.24 shows a sample conn ection between the smart card and this lsi. as in the figure, since this lsi communicat es with the smart card using a single transmission line, interconnect the txd and rxd pins and pull up the data transmission line to v cc using a resistor. setting the re and te bits to 1 with the smart card not connected enables closed transmission/reception allowing self diagnosis. to supply the smart card with the clock pulses generated by the sci, input the sck pin output to the clk pin of the smart card. a reset signal can be supplied via the output port of this lsi. (in sci_5 and sci-6, the clock generated in sci cannot be provided to smart cards.) txd rxd this lsi v cc i/o main unit of the device to be connected ic card data line clk rst sck rx (port) clock line reset line figure 18.24 pin connectio n for smart card interface section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 839 of 1340 rej09b0499-0200 18.7.2 data format (except in block transfer mode) figure 18.25 shows the data transfer formats in smart ca rd interface mode. ? one frame contains 8-bit data and a parity bit in asynchronous mode. ? during transmission, at least 2 et u (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. ? if a parity error is detected during reception, a lo w error signal is output for 1 etu after 10.5 etu has passed from the start bit. ? if an error signal is sampled during transmission, the same data is automatically re-transmitted after at least 2 etu. ds d0 d1 d2 d3 d4 d5 d6 d7 dp in normal transmission/reception output from the transmitting station ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error is generated output from the transmitting station de output from the receiving station [legend] ds: start bit d0 to d7: data bits dp: parity bit de: error signal figure 18.25 data formats in no rmal smart card interface mode for communication with the smart cards of the di rect convention and inverse convention types, follow the procedure below. ds azzazz z za a (z) (z) state d0 d1 d2 d3 d4 d5 d6 d7 dp figure 18.26 direct conv ention (sdir = sinv = o/ e = 0) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 840 of 1340 rej09b0499-0200 for the direct convention type, logic levels 1 and 0 correspond to states z and a, respectively, and data is transferred with lsb-first as the start character, as shown in figure 18.26. therefore, data in the start character in the figu re is h'3b. when using the direct convention type, write 0 to both the sdir and sinv bits in scmr. write 0 to the o/ e bit in smr in order to use even parity, which is prescribed by the smart card standard. ds azzaaa z aa a (z) (z) state d7 d6 d5 d4 d3 d2 d1 d0 dp figure 18.27 inverse conv ention (sdir = sinv = o/ e = 1) for the inverse convention type, logic levels 1 and 0 correspond to states a and z, respectively and data is transferred with msb-first as the star t character, as shown in fi gure 18.27. therefore, data in the start character in the figure is h'3f. when using the inverse convention type, write 1 to both the sdir and sinv bits in scmr. the parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, an d corresponds to state z. since the sniv bit of this lsi only inverts data bits d7 to d0, write 1 to the o/ e bit in smr to invert the parity bit in both transmission and reception. 18.7.3 block transfer mode block transfer mode is different from normal sm art card interface mode in the following respects. ? even if a parity error is detected during reception, no error signal is output. since the per bit in ssr is set by error detection, clear the per bit before receiving the parity bit of the next frame. ? during transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. ? since the same data is not re-transmitted during transmission, the tend flag is set 11.5 etu after transmission start. ? although the ers flag in block transfer mode di splays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 841 of 1340 rej09b0499-0200 18.7.4 receive data sampling timi ng and recept ion margin only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. in this mode , the sci can operate on a base clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the bcp1 and bcp0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mo de). at reception, the falling edge of the start bit is sampled using the base clock in order to perform internal synchronization. receive data is sampled on th e 16th, 32nd, 186th and 128t h rising edges of the base clock so that it can be latched at the mi ddle of each bit as shown in figure 18.28. the reception margin here is determin ed by the following formula. m = | (0.5 ? ) ? (l ? 0.5) f ? (1 + f ) | 100% 2n 1 n | d ? 0.5 | m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, 256) d: duty cycle of clock (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation [legend] assuming values of f = 0, d = 0.5, and n = 372 in the above formula, the reception margin is determined by the formula below. m = ( 0.5 ? ) 100% = 49.866% 2 372 1 internal basic clock 372 clock cycles 186 clock cycles receive data (rxd) synchronization sampling timing d0 d1 data sampling timing 185 371 0 371 185 0 0 start bit figure 18.28 receive data sampling timing in smart card interface mode (when clock frequency is 372 times the bit rate) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 842 of 1340 rej09b0499-0200 18.7.5 initialization before transmitting and receiving data, initia lize the sci using the following procedure. initialization is also necessary be fore switching from transmission to reception and vice versa. 1. clear the te and re bits in scr to 0. 2. set the icr bit of the corresponding pin to 1. 3. clear the error flags ers, per, and orer in ssr to 0. 4. set the gm, blk, o/ e , bcp1, bcp0, cks1, and cks0 bits in smr appropriately. also set the pe bit to 1. 5. set the smif, sdir, and sinv bits in scmr appropriately. when the ddr corresponding to the txd pin is cleared to 0, the txd and rxd pins are changed from port pins to sci pins, placing the pins into high impedance state. 6. set the value corresponding to the bit rate in brr. 7. set the cke1 and cke0 bits in scr appropri ately. clear the tie, rie, te, re, mpie, and teie bits to 0 simultaneously. when the cke0 bit is set to 1, the sck pin is allowed to output clock pulses. 8. set the tie, rie, te, and re bits in scr appropriately after waiti ng for at least a 1-bit interval. setting the te and re bits to 1 simultaneously is prohibited except for self diagnosis. to switch from reception to transmission, first verify that r eception has completed, then initialize the sci. at the end of initialization, re and te should be set to 0 and 1, respectively. reception completion can be verified by reading the rdrf, per, or orer flag. to switch from transmission to reception, first verify that transm ission has completed, then initialize the sci. at the end of initialization, te and re should be set to 0 and 1, respectively. transmission completion can be verified by reading the tend flag. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 843 of 1340 rej09b0499-0200 18.7.6 data transmission (except in block transfer mode) data transmission in smart card interface mode (exc ept in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted. figure 18.29 shows the da ta re-transfer operation during transmission. 1. if an error signal from the receiving end is sampled after one frame of data has been transmitted, the ers bit in ssr is set to 1. here , an eri interrupt request is generated if the rie bit in scr is set to 1. clear the ers bit to 0 before the next parity bit is sampled. 2. for the frame in which an error signal is receiv ed, the tend bit in ssr is not set to 1. data is re-transferred from tdr to tsr allo wing automatic data retransmission. 3. if no error signal is returned from the receivi ng end, the ers bit in ssr is not set to 1. 4. in this case, one frame of data is determined to have been transmitted including re-transfer, and the tend bit in ssr is set to 1. here, a txi in terrupt request is generated if the tie bit in scr is set to 1. writing transmit data to tdr starts transmission of the next data. figure 18.31 shows a sample flowchart for transmission. all the processing steps are automatically performed using a txi interrup t request to activate the dtc or dmac. in transmission, the tend and tdre flags in ssr are simultaneously set to 1, thus generating a txi interrupt request if the tie bit in scr has been set to 1. this activates the dtc or dmac by a txi request thus allowing transfer of transmit da ta if the txi interrupt re quest is specified as a source of dtc or dmac activation beforehand. the tdre and tend flags are automatically cleared to 0 at data transfer by the dtc or dmac. if an error occurs, the sci automatically re- transmits the same data. during re-transmission, tend remains as 0, thus not activating the dtc or dmac. therefore, the sci and dtc or dmac automatically transmit the specified number of bytes, including re-transmission in the case of er ror occurrence. however, the ers flag is not automatically cleared; the ers flag must be cleared by previously setting the rie bit to 1 to enable an eri interrupt request to be generated at error occurrence. when transmitting/receiving data using the dtc or dmac, be sure to set and enable the dtc or dmac prior to making sci settings. for dtc or dmac settings, see section 12, data transfer controller (dtc) and section 10, dma controller (dmac). section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 844 of 1340 rej09b0499-0200 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds (n + 1) th transfer frame retransfer frame nth transfer frame tdre tend [1] fer/ers transfer from tdr to tsr transfer from tdr to tsr transfer from tdr to tsr [2] [4] [3] figure 18.29 data re-transfer op eration in sci transmission mode note that the tend flag is set in different timings depending on the gm bit setting in smr. figure 18.30 shows the tend flag set timing. ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5 etu txi (tend interrupt) 11.0 etu de guard time gm = 0 gm = 1 [legend] ds: start bit d0 to d7: data bits dp: parity bit de: error signal figure 18.30 tend flag set timing during transmission section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 845 of 1340 rej09b0499-0200 initialization no yes clear te bit in scr to 0 start transmission start no no no yes yes yes yes no end write data to tdr and clear tdre flag in ssr to 0 error processing error processing tend = 1 ? all data transmitted? tend = 1 ? ers = 0 ? ers = 0 ? figure 18.31 sample transmission flowchart section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 846 of 1340 rej09b0499-0200 18.7.7 serial data reception (exc ept in block transfer mode) data reception in smart card interface mode is similar to that in normal serial communication interface mode. figure 18.32 shows the data re-transfer operatio n during reception. 1. if a parity error is detected in receive data , the per bit in ssr is set to 1. here, an eri interrupt request is generated if the rie bit in s cr is set to 1. clear the per bit to 0 before the next parity bit is sampled. 2. for the frame in which a parity error is de tected, the rdrf bit in ssr is not set to 1. 3. if no parity error is detected, the per bit in ssr is not set to 1. 4. in this case, data is determined to have be en received successfully, and the rdrf bit in ssr is set to 1. here, an rxi interrupt request is generated if the rie bit in scr is set to 1. figure 18.33 shows a samp le flowchart for receptio n. all the processing steps are automatically performed using an rxi interrupt request to activ ate the dtc or dmac. in reception, setting the rie bit to 1 allows an rxi interrupt request to be generated when the rdrf flag is set to 1. this activates the dtc or dmac by an rxi request thus allowing transfer of receive data if the rxi interrupt request is specified as a source of dt c or dmac activation beforehand. the rdrf flag is automatically cleared to 0 at data transfer by the dtc or dmac. if an error occurs during reception, i.e., either the orer or per flag is set to 1, a tran smit/receive error interrupt (eri) request is generated and the error flag must be cleared. if an error occurs, the dtc or dmac is not activated and receive data is skipped, therefor e, the number of bytes of receive data specified in the dtc or dmac is transferred. even if a pa rity error occurs and the per bit is set to 1 in reception, receive data is tr ansferred to rdr, thus allowing the data to be read. note: for operations in block transfer mode, see section 18.4, operation in asynchronous mode. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds (n + 1) th transfer frame retransfer frame nth transfer frame rdrf [1] per [2] [3] [4] figure 18.32 data re-transfer operation in sci reception mode section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 847 of 1340 rej09b0499-0200 initialization read data from rdr and clear rdrf flag in ssr to 0 clear re bit in scr to 0 start reception start error processing no no no yes yes orer = 0 and per = 0? rdrf = 1 ? all data received? yes figure 18.33 sample reception flowchart 18.7.8 clock output control (only sci_0, 1, 2, and 4) clock output can be fixed using the cke1 and cke0 bits in scr when the gm bit in smr is set to 1. specifically, the minimum width of a clock pulse can be specified. figure 18.34 shows an example of clock output fixing timing when the cke0 bit is controlled with gm = 1 and cke1 = 0. given pulse width sck cke0 given pulse width figure 18.34 clock output fixing timing section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 848 of 1340 rej09b0499-0200 at power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. ? at power-on to secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1. initially, port input is enabled in the high-impedance state. to fix the potential level, use a pull-up or pull-down resistor. 2. fix the sck pin to the specified output using the cke1 bit in scr. 3. set smr and scmr to enable smart card interface mode. set the cke0 bit in scr to 1 to start clock output. ? at mode switching a) at transition from smart card inte rface mode to software standby mode 1. set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the values for the output fixed state in software standby mode. (sci_0, 1, 2, and 4 only) 2. write 0 to the te and re bits in scr to stop transmission/recep tion. simultaneously, set the cke1 bit to the value for the output fixed state in software standby mode. 3. write 0 to the cke0 bit in scr to stop the clock. 4. wait for one cycle of the serial clock. in th e mean time, the clock output is fixed to the specified level with the duty cycle retained. 5. make the transition to software standby mode. b) at transition from software standby mode to smart card interface mode 1. clear software standby mode. 2. write 1 to the cke0 bit in scr to start clock output. a clock signal with the appropriate duty cycle is then generated. [1] [2] [3] [4] [5] [7] software standby normal operation normal operation [6] figure 18.35 clock stop and restart procedure section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 849 of 1340 rej09b0499-0200 18.8 irda operation if the irda function is enabled using the ire bit in ircr, the txd5 and rxd5 pins in sci_5 are allowed to encode and decode the waveform based on the irda specifications version 1.0 (function as the irtxd and irrxd pins)*. connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the irda specifications version 1.0. in the system defined by the irda specifications version 1.0, communication is started at a transfer rate of 9600 bps, which can be modifi ed later as required. since the irda interface provided by this lsi does not incorporate the capability of automatic modification of the transfer rate, the transfer rate must be modified through programming. figure 18.36 is the irda block diagram. pulse encoder pulse decoder ircr irda sci5 txd txd5/irtxd rxd rxd5/irrxd figure 18.36 irda block diagram note: * the irda function should be used when the abcs bit in semr_5 is set to 0 and the acs3 to acs0 bits in semr_5 are set to b'0000. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 850 of 1340 rej09b0499-0200 (1) transmission during transmission, the output signals from the sci (uart frames) are converted to ir frames using the irda interface (see figure 18.37). for serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). the high-level pulse can be selected using the ircks2 to ircks0 bits in ircr. the high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) bit rate or (3/16 bit rate) +1.08 s at maximum. for example, when the frequency of system clock is 20 mhz, a high-level pulse width of 1.6 s can be specified because it is the smallest value in the range greater than 1.41 s. for serial data of level 1, no pulses are output. uart frame data ir frame data 0000 0 11 11 1 0000 0 11 11 1 transmission reception bit cycle pulse width is 1.6 s to 3/16 bit cycle start bit stop bit stop bit start bit figure 18.37 irda transmission and reception (2) reception during reception, ir frames ar e converted to uart frames us ing the irda interface before inputting to sci. 0 is output when the high level pulse is detected while 1 is output when no pulse is detected during one bit period. note that a pulse shorter than the minimum pulse width of 1.41 s is also regarded as a 0 signal. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 851 of 1340 rej09b0499-0200 (3) high-level pulse width selection table 18.13 shows possible settings for bits ircks2 to ircks0 (minimum pulse width), and this lsi's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. table 18.13 ircks2 to ircks0 bit settings operating bit rate (bps) (upper row)/bit interval 3/16 (s) (lower row) frequency 2400 9600 19200 38400 57600 115200 p (mhz) 78.13 19.53 9.77 4.88 3.26 1.63 7.3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.288 101 101 101 101 101 101 14 101 101 101 101 101 101 14.7456 101 101 101 101 101 101 16 101 101 101 101 101 101 17.2032 101 101 101 101 101 101 18 101 101 101 101 101 101 19.6608 101 101 101 101 101 101 20 101 101 101 101 101 101 25 110 110 110 110 110 110 30 110 110 110 110 110 110 33 110 110 110 110 110 110 35 110 110 110 110 110 110 section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 852 of 1340 rej09b0499-0200 18.9 interrupt sources 18.9.1 interrupts in normal serial communication interface mode table 18.14 shows the interrupt sources in no rmal serial communication interface mode. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interr upt request is generated. a txi interrupt request can activate the dtc or dmac to allow data transfer. the tdre flag is automatically cleared to 0 at data transfer by the dtc or dmac. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri in terrupt request is generate d. an rxi interrupt can activate the dtc or dmac to allow data transfer. the rdrf flag is automatically cleared to 0 at data transfer by the dtc or dmac. a tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt has priority for acceptance. however, note that if the tdre and tend flags are cl eared to 0 simultaneously by the txi interrupt processing routine, the sci cannot branch to the tei interrupt processing routine later. note that the priority order for interrupts is different between the group of sci_0, 1, 2, and 4 and the group of sci_5 and sci_6. table 18.14 sci interrupt sou rces (sci_0, 1, 2, and 4) name interrupt source interrupt flag dtc activation dmac activation priority eri receive error orer, fer, or per not possible not possible rxi receive data full rdrf possible possible txi transmit data empty tdre possible possible high tei transmit end tend not possible not possible low section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 853 of 1340 rej09b0499-0200 table 18.15 sci interrupt so urces (sci_5 and sci_6) name interrupt source interrupt flag dtc activation dmac activation priority rxi receive data full rdrf not possible possible high txi transmit data empty t dre not possible possible eri receive error orer, fer, or per not possible not possible tei transmit end tend not possible not possible low 18.9.2 interrupts in smart ca rd interface mode table 18.16 shows the interrup t sources in smart card interf ace mode. a transmit end (tei) interrupt request cannot be used in this mode. note that the priority order for interrupts is different between the group of sci_0, 1, 2, and 4 and the group of sci_5 and sci_6. table 18.16 sci interrupt sou rces (sci_0, 1, 2, and 4) name interrupt source interrupt flag dtc activation dmac activation priority eri receive error or error signal detection orer, per, or ers not pos sible not possible high rxi receive data full rdrf possible possible txi transmit data empty tend possible possible low table 18.17 sci interrupt so urces (sci_5 and sci_6) name interrupt source interrupt flag dtc activation dmac activation priority rxi receive data full rdrf not possible possible high txi transmit data empty t dre not possible possible eri receive error or error signal detection orer, per, or ers not possible not possible low section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 854 of 1340 rej09b0499-0200 data transmission/reception using the dtc or dmac is also possible in smart card interface mode, similar to in the normal sci mode. in tr ansmission, the tend and tdre flags in ssr are simultaneously set to 1, thus generating a txi interrupt. this activates the dtc or dmac by a txi request thus allowing transfer of transmit data if the txi reque st is specified as a source of dtc or dmac activation beforehand. the tdre an d tend flags are automatically cleared to 0 at data transfer by the dtc or dmac. if an error occurs, the sci automatically re-transmits the same data. during re-transmission, the tend flag remains as 0, thus not activating the dtc or dmac. therefore, the sci and dtc or dmac au tomatically transmit th e specified number of bytes, including re-transmission in the case of er ror occurrence. however, the ers flag in ssr, which is set at error occurrence , is not automatically cleared; th e ers flag must be cleared by previously setting the rie bit in scr to 1 to enable an eri interrupt request to be generated at error occurrence. when transmitting/receiving data using the dtc or dmac, be sure to set and enable the dtc or dmac prior to making sci settings. for dtc or dmac settings, see section 12, data transfer controller (dtc) and section 10, dma controller (dmac). in reception, an rxi interrupt request is generate d when the rdrf flag in ssr is set to 1. this activates the dtc or dmac by an rxi request thus allowing transfer of receive data if the rxi request is specified as a sour ce of dtc or dmac activation beforehand. the rdrf flag is automatically cleared to 0 at da ta transfer by the dtc or dmac . if an error occurs, the rdrf flag is not set but the error flag is set. theref ore, the dtc or dmac is not activated and an eri interrupt request is issued to the cpu instead; the error flag must be cleared. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 855 of 1340 rej09b0499-0200 18.10 usage notes 18.10.1 module stop function setting operation of the sci can be disabled or enabled using the module stop control register. the initial setting is for operation of the sci to be halted. register access is enabled by clearing the module stop state. for details, see section 27, power-down modes. 18.10.2 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the per flag may also be set. note that, since th e sci continues the receive operation even after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 18.10.3 mark state and break detection when the te bit is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by dr and ddr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line in mark state (the state of 1) until te is set to 1, set both ddr and dr to 1. since the te bit is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set ddr to 1 and dr to 0, and then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. 18.10.4 receive error flags and transmit operati ons (clocked synchronous mode only) transmission cannot be started when a receive error flag (orer, fer, or rer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flag s to 0 before starting transmission. note also that the receive error flag s cannot be cleared to 0 even if the re bit is cleared to 0. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 856 of 1340 rej09b0499-0200 18.10.5 relation between writing to tdr and tdre flag the tdre flag in ssr is a status flag which indicat es that transmit data ha s been transferred from tdr to tsr. when the sci tran sfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr irrespective of the tdre flag status. however, if new data is written to tdr when the tdre flag is 0, that is, when the previous data has not been transferred to tsr yet, the previous data in tdr is lost. be sure to write transmit data to tdr after verifying that the tdre flag is set to 1. 18.10.6 restrictions on using dtc or dmac ? when the external clock source is used as a synchronization clock, update tdr by the dmac or dtc and wait for at least five p clock cycles before allowing the transmit clock to be input. if the transmit clock is input within four clock cycles after tdr modification, the sci may malfunction (see figure 18.38). ? when using the dmac or dtc to read rdr, be sure to set the receive end interrupt (rxi) as the dtc or dmac activation source. t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when external clock is supplied, t must be more than four clock cycles. tdre figure 18.38 sample transmission using dtc in clocked synchronous mode ? the dtc is not activated by the rxi or txi request by sci_5 or sci6. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 857 of 1340 rej09b0499-0200 18.10.7 sci operations during power-down state transmission: before specifying the module stop state or making a transition to software standby mode, stop the transmit operations (te = tie = teie = 0). tsr, tdr, and ssr are reset. the states of the output pins in the module stop state or in software standby mode depend on the port settings, and the pins output a high-level signal after cancellation. if the transition is made during data transmission, the data being transmitted will be undefined. to transmit data in the same transmission mode after cancellation of the power-down state, set the te bit to 1, read ssr, write to tdr, clear tdre in this order, and then start transmission. to transmit data in a different transmission mode, initialize the sci first. for using the irda function, set the ire bit in addition to setting the te bit. figure 18.39 shows a sample flowchart for transition to software standby mode during transmission. figures 18.40 and 18.41 show the port pin states during transition to software standby mode. before specifying the module stop state or making a transition to software standby mode from the transmission mode using dtc transfer, stop all transmit operations (te = tie = teie = 0). setting the te and tie bits to 1 after cancellation se ts the txi flag to start transmission using the dtc. reception: before specifying the module stop state or making a transition to software standby mode, stop the receive operations (re = 0). rsr, rdr, and ssr are reset. if transition is made during data reception, the data being received will be invalid. to receive data in the same recep tion mode after cancellation of th e power-down state, set the re bit to 1, and then start reception. to receive data in a differe nt reception mode, initialize the sci first. for using the irda function, set the ire bit in addition to setting the re bit. figure 18.42 shows a sample flowchart for mode transition during reception. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 858 of 1340 rej09b0499-0200 start transmission transmission [1] no no no yes yes yes read tend flag in ssr make transition to software standby mode cancel software standby mode te = 0 initialization te = 1 [2] [3] all data transmitted? change operating mode? tend = 1 [1] data being transmitted is lost halfway. data can be normally transmitted from the cpu by setting the te bit to 1, reading ssr, writing to tdr, and clearing the tdre bit to 0 after clearing software standby mode; however, if the dtc has been activated, the data remaining in the dtc will be transmitted when both the te and tie bits are set to 1. [2] clear the tie and teie bits to 0 when they are 1. [3] setting of the module stop state is included. figure 18.39 sample flowchart for software standby mode transition during transmission te bit sck * output pin txd output pin note: * not output in sci_5, 6. port input/output port input/output port input/output start stop high output high output transmission start transmission end transition to software standby mode software standby mode canceled sci txd output port port sci txd output figure 18.40 port pin states during software standby mode transition (internal clock, asynchronous transmission) section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 859 of 1340 rej09b0499-0200 te bit sck output pin txd output pin port input/output port input/output port input/output high output * marking output transmission start transmission end transition to software standby mode software standby mode canceled sci txd output port port sci txd output last txd bit retained note: * initialized in software standby mode figure 18.41 port pin states during software standby mode transition (internal clock, clocked synchronous transmission) (setting is prohibited in sci_5 and sci_6) start reception reception [1] no no yes yes read receive data in rdr read rdrf flag in ssr make transition to software standby mode cancel software standby mode re = 0 initialization re = 1 [2] change operating mode? rdrf = 1 [1] data being received will be invalid. [2] setting of the module stop state is included. figure 18.42 sample flowchart for softwa re standby mode transition during reception section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 860 of 1340 rej09b0499-0200 18.11 crc operation circuit the cyclic redundancy check (crc) operatio n circuit detects errors in data blocks. 18.11.1 features the features of the crc operation circuit are listed below. ? crc code generated for any desired data length in an 8-bit unit ? crc operation executed on eight bits in parallel ? one of three generating polynomials selectable ? crc code generation for lsb-first or msb-first communication selectable figure 18.43 shows a block diagram of the crc operation circuit. internal bus crc code generation circuit crccr crcdir crcdor control signal [legend] crccr: crcdir: crcdor: crc control register crc data input register crc data output register figure 18.43 block diagra m of crc operation circuit section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 861 of 1340 rej09b0499-0200 18.11.2 register descriptions the crc operation circuit has the following registers. ? crc control register (crccr) ? crc data input register (crcdir) ? crc data output register (crcdor) (1) crc control register (crccr) crccr initializes the crc operation circuit, switches the operation mode, and selects the generating polynomial. bit bit name initial value r/w 7 dorclr 0 w 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 lms 0 r/w 1 g1 0 r/w 0 g0 0 r/w bit bit name initial value r/w description 7 dorclr 0 w crcdor clear setting this bit to 1 clears crcdor to h'0000. 6 to 3 ? all 0 r reserved the initial value should not be changed. 2 lms 0 r/w crc operation switch selects crc code generation for lsb-first or msb-first communication. 0: performs crc operation for lsb-first communication. the lower byte (bits 7 to 0) is first transmitted when crcdor contents (crc code) are divided into two bytes to be transmitted in two parts. 1: performs crc operation for msb-first communication. the upper byte (bits 15 to 8) is first transmitted when crcdor contents (crc code) are divided into two bytes to be transmitted in two parts. section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 862 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 0 g1 g0 0 0 r/w r/w crc generating polynomial select: selects the polynomial. 00: reserved 01: x 8 + x 2 + x + 1 10: x 16 + x 15 + x 2 + 1 11: x 16 + x 12 + x 5 + 1 (2) crc data input register (crcdir) crcdir is an 8-bit readable/writable register, to which the bytes to be crc-operated are written. the result is obtained in crcdor. bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w (3) crc data output register (crcdor) crcdor is a 16-bit readable/writable register that contains the result of crc operation when the bytes to be crc-operated are written to cr cdir after crcdor is cleared. when the crc operation result is additionally written to the bytes to which crc operation is to be performed, the crc operation result will be h'0000 if the data c ontains no crc error. when bits 1 and 0 in crccr (g1 and g0 bits) are set to 0 and 1, respectively, the lower byte of this register contains the result. bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 863 of 1340 rej09b0499-0200 18.11.3 crc operation circuit operation the crc operation circuit generates a crc code for lsb-first/msb-first communications. an example in which a crc code for hexadecimal data h'f0 is generated using the x 16 + x 12 + x 5 + 1 polynomial with the g1 and g0 bits in crccr set to b'11 is shown below. crccr crcdorh crcdorl crcdor clearing 1. write h'83 to crccr 1 7 0 0 0 00 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 2. write h'f0 to crcdir 1 1 1 1 0 00 0 1 1 1 1 0 11 1 1 0 0 0 1 11 1 crc code = h'f78f crc code output data 3. read from crcdor 7 7 7 fff0 8 7 00 0 4. serial transmission (lsb first) 1 1 1 1 0 1 1 1 1 0 0 0 1 11 1 1 1 1 1 0 00 0 figure 18.44 lsb-first data transmission crccr crcdorh crcdorl crcdor clearing 1. write h'87 to crccr 1 7 0 0 0 01 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 2. write h'f0 to crcdir 1 1 1 1 0 00 0 1 1 1 0 1 11 1 0 0 0 1 1 11 1 crc code = h'ef1f crc code output data 3. read from crcdor 7 7 0 ff1f e 7 00 0 4. serial transmission (msb first) 1 1 1 1 0 0 0 0 1 1 1 0 1 11 1 0 0 0 1 1 11 1 figure 18.45 msb-first data transmission section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 864 of 1340 rej09b0499-0200 crccr crcdorh crcdorl crcdor clearing 2. write h'83 to crccr 1 7 0 0 0 00 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 3. write h'f0 to crcdir 1 1 1 1 0 00 0 1 1 1 1 0 11 1 1 0 0 0 1 11 1 crcdir crcdorh crcdorl crc code generation 4. write h'8f to crcdir 1 7 0 0 0 11 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 1 1 1 1 0 11 1 crcdir crcdorh crcdorl crc code generation 5. write h'f7 to crcdir 1 1 1 1 0 11 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crc code = h'0000 no error crc code input data 6. read from crcdor 7 7 7 fff0 8 7 00 0 1. serial reception (lsb first) 1 1 1 1 0 1 1 1 1 0 0 0 1 11 1 1 1 1 1 0 00 0 figure 18.46 lsb-fi rst data reception section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 865 of 1340 rej09b0499-0200 crccr crcdorh crcdorl crcdor clearing 2. write h'83 to crccr 1 7 0 0 0 01 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 3. write h'f0 to crcdir 1 1 1 1 0 00 0 1 1 1 0 1 11 1 0 0 0 1 1 11 1 crcdir crcdorh crcdorl crc code generation 4. write h'ef to crcdir 1 7 1 1 0 11 0 7 0 7 0 7 0 1 1 0 0 0 1 1 11 1 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 5. write h'1f to crcdir 0 0 0 1 1 11 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crc code = h'0000 no error crc code input data 6. read from crcdor 7 7 0 ff1f e 7 00 0 1. serial reception (msb first) 1 1 1 1 0 0 0 0 1 1 1 0 1 11 1 0 0 0 1 1 11 1 figure 18.47 msb-first data reception section 18 serial communicati on interface (sci, irda, crc) rev. 2.00 oct. 20, 2009 page 866 of 1340 rej09b0499-0200 18.11.4 note on crc operation circuit note that the sequence to transmit the crc code differs between lsb-first transmission and msb-first transmission. crcdir crcdorh crcdorl 1. crc code generation 2. transmission data (i) lsb-first transmission crc code generation after specifying the operation method, write data to crcdir in the sequence of (1) (2) (3) (4). crc code output 7 7 70 0 0 0 70 00 0 777 7 (1) (2) (3) (4) (5) (6) (1) (2) (3) (4) (6) (5) (ii) msb-first transmission crc code output 77 000000 777 7 (6) (5) (4) (3) (2) (1) figure 18.48 lsb-first a nd msb-first transmit data section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 867 of 1340 rej09b0499-0200 section 19 usb function module (usb) this lsi incorporates a usb function module (usb). 19.1 features ? the udc (usb device controller) conforming to usb2.0 and tran sceiver process usb protocol automatically. automatic processing of usb standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) ? transfer speed: supports full-speed (12 mbps) ? endpoint configuration: endpoint name abbreviation transfer type maximum packet size fifo buffer capacity (byte) dma transfer endpoint 0 ep0s setup 8 8 ? ep0i control-in 8 8 ? ep0o control-out 8 8 ? endpoint 1 ep1 bulk-out 64 128 possible endpoint 2 ep2 bulk-in 64 128 possible endpoint 3 ep3 interrupt-in 8 8 ? configuration1-interface0-alternatesetting0 endpoint1 endpoint2 endpoint3 ? interrupt requests: generates various interrupt signals necessary for usb transmission/reception ? power mode: self power mode or bus power mode can be selected by the power mode bit (pwmd) in the control register (ctlr). section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 868 of 1340 rej09b0499-0200 figure 19.1 shows the block diagram of the usb. peripheral bus interrupt requests status and control registers fifo udc transceiver usb function module d+ d- clock for usb (48 mhz) udc: usb device controller [legend] figure 19.1 block diagram of usb 19.2 input/output pins table 19.1 shows the usb pin configuration. table 19.1 pin configuration pin name i/o function vbus input usb cable connection monitor pin usd+ i/o usb data i/o pin usd- i/o usb data i/o pin drvcc input power supply pin for usb on-chip transceiver drvss input ground pin for usb on-chip transceiver section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 869 of 1340 rej09b0499-0200 19.3 register descriptions the usb has following registers. for the information on the addres ses of these registers and the state of the register in each processing condition, see section 28, list of registers. ? interrupt flag register 0 (ifr0) ? interrupt flag register 1 (ifr1) ? interrupt flag register 2 (ifr2) ? interrupt select register 0 (isr0) ? interrupt select register 1 (isr1) ? interrupt select register 2 (isr2) ? interrupt enable register 0 (ier0) ? interrupt enable register 1 (ier1) ? interrupt enable register 2 (ier2) ? ep0i data register (epdr0i) ? ep0o data register (epdr0o) ? ep0s data register (epdr0s) ? ep1 data register (epdr1) ? ep2 data register (epdr2) ? ep3 data register (epdr3) ? ep0o receive data size register (epsz0o) ? ep1 receive data si ze register (epsz1) ? trigger register (trg) ? data status register (dasts) ? fifo clear register (fclr) ? dma transfer setting register (dma) ? endpoint stall register (epstl) ? configuration value register (cvr) ? control register (ctlr) ? endpoint information register (epir) ? transceiver test register 0 (trntreg0) ? transceiver test register 1 (trntreg1) section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 870 of 1340 rej09b0499-0200 19.3.1 interrupt flag re gister 0 (ifr0) ifr0, together with interrupt flag registers 1and 2 (ifr1and ifr2), indicates interrupt status information required by the application. when an interrupt source is generated, the corresponding bit is set to 1. and then this bit, in combinatio n with interrupt enable register 0 (ier0), generates an interrupt request to the cpu. to clear, write 0 to the bit to be cleared and 1 to the other bits. however, since ep1full and ep2empty are st atus bits, these bits cannot be cleared. bit bit name initial value r/w 7 brst 0 r/w 6 ep1 full 0 r 5 ep2 tr 0 r/w 4 ep2 empty 1 r 3 setup ts 0 r/w 2 ep0o ts 0 r/w 1 ep0i tr 0 r/w 0 ep0i ts 0 r/w bit bit name initial value r/w description 7 brst 0 r/w bus reset this bit is set to 1 when a bus reset signal is detected on the usb bus. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 6 ep1 full 0 r ep1 fifo full this bit is set when endpoint 1 receives one packet of data successfully from the host, and holds a value of 1 as long as there is valid data in the fifo buffer. this is a status bit, and cannot be cleared. 5 ep2 tr 0 r/w ep2 transfer request this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 2 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 871 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 ep2 empty 1 r ep2 fifo empty this bit is set when at least one of the dual endpoint 2 transmit fifo buffers is ready for transmit data to be written. this is a status bit, and cannot be cleared. 3 setup ts 0 r/w setup command receive complete this bit is set to 1 when endpoint 0 receives successfully a setup command requiring decoding on the application side, and returns an ack handshake to the host. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 2 ep0o ts 0 r/w ep0o receive complete this bit is set to 1 when endpoint 0 receives data from the host successfully, stores t he data in the fifo buffer, and returns an ack handshake to the host. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 ep0i tr 0 r/w ep0i transfer request this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 0 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 0 ep0i ts 0 r/w ep0i transmit complete this bit is set when data is transmitted to the host from endpoint 0 and an ack handshake is returned. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 872 of 1340 rej09b0499-0200 19.3.2 interrupt flag re gister 1 (ifr1) ifr1, together with interrupt flag registers 0 and 2 (ifr0 and ifr2), indicates interrupt status information required by the application. when an interrupt source is generated, the corresponding bit is set to 1. and then this bit, in combinatio n with interrupt enable register 1 (ier1), generates an interrupt request to the cpu. to clear, write 0 to the bit to be cleared and 1 to the other bits. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 vbus mn 0 r 2 ep3 tr 0 r/w 1 ep3 ts 0 r/w 0 vbusf 0 r/w bit bit name initial value r/w description 7 6 5 4 ? ? ? ? 0 0 0 0 r r r r reserved these bits are always read as 0. the write value should always be 0. 3 vbus mn 0 r this is a status bi t which monitors the state of the vbus pin. this bit reflects the state of the vbus pin and generates no interrupt request. this bit is always 0 when the pullup_e bit in dma is 0. 2 ep3 tr 0 r/w ep3 transfer request this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 3 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 ep3 ts 0 r/w ep3 transmit complete this bit is set when data is transmitted to the host from endpoint 3 and an ack handshake is returned. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 873 of 1340 rej09b0499-0200 bit bit name initial value r/w description 0 vbusf 0 r/w usb disconnection detection when the function is connected to the usb bus or disconnected from it, this bit is set to 1. the vbus pin of this module is used for detecting connection or disconnection. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 19.3.3 interrupt flag re gister 2 (ifr2) ifr2, together with interrupt flag registers 0 an d 1 (ifr0 and ifr1), indicates interrupt status information required by the application. when an interrupt source is generated, the corresponding bit is set to 1. and then this bit, in combinatio n with interrupt enable register 2 (ier2), generates an interrupt request to the cpu. to clear, write 0 to the bit to be cleared and 1 to the other bits. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 surss 0 r 4 sursf 0 r/w 3 cfdn 0 r/w 2 ? 0 r 1 setc 0 r/w 0 seti 0 r/w bit bit name initial value r/w description 7 6 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 5 surss 0 r suspend/resume status this is a status bit that describes bus state. 0: normal state 1: suspended state this bit is a status bit and generates no interrupt request. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 874 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 sursf 0 r/w suspend/resume detection this bit is set to 1 when the state changed from normal to suspended state or vice versa. the corresponding interrupt output is resume, usbintn2, and usbintn3. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 3 cfdn 0 r/w end point information load end this bit is set to 1 when writing data in the endpoint information register to the epir register ends (load end). this module starts the usb operation after the endpoint information is completely set. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 setc 0 r/w set_configuration command detection when the set_configuration command is detected, this bit is set to 1. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 0 seti 0 r/w set_interface command detection when the set_interface command is detected, this bit is set to 1. (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 875 of 1340 rej09b0499-0200 19.3.4 interrupt select register 0 (isr0) isr0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0 (ifr0). if the usb issues an interrupt request to th e intc when a bit in isr0 is cleared to 0, the interrupt corresponding to the bit will be usbintn2. if the usb issues an in terrupt request to the intc when a bit in isr0 is set to 1, the corresponding interrupt will be usbintn3. bit bit name initial value r/w 7 brst 0 r/w 6 ep1 full 0 r/w 5 ep2 tr 0 r/w 4 ep2 empty 0 r/w 3 setup ts 0 r/w 2 ep0o ts 0 r/w 1 ep0i tr 0 r/w 0 ep0i ts 0 r/w bit bit name initial value r/w description 7 brst 0 r/w bus reset 6 ep1 full 0 r/w ep1 fifo full 5 ep2 tr 0 r/w ep2 transfer request 4 ep2 empty 0 r/w ep2 fifo empty 3 setup ts 0 r/w setup command receive complete 2 ep0o ts 0 r/w ep0o receive complete 1 ep0i tr 0 r/w ep0i transfer request 0 ep0i ts 0 r/w ep0i transmission complete section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 876 of 1340 rej09b0499-0200 19.3.5 interrupt select register 1 (isr1) isr1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1 (ifr1). if the usb issues an interrupt request to th e intc when a bit in isr1 is cleared to 0, the interrupt corresponding to the bit will be usbintn2. if the usb issues an in terrupt request to the intc when a bit in isr1 is set to 1, the corresponding interrupt will be usbintn3. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ep3 tr 1 r/w 1 ep3 ts 1 r/w 0 vbusf 1 r/w bit bit name initial value r/w description 7 6 5 4 3 ? ? ? ? ? 0 0 0 0 0 r r r r r reserved these bits are always read as 0. the write value should always be 0. 2 ep3 tr 1 r/w ep3 transfer request 1 ep3 ts 1 r/w ep3 transmission complete 0 vbusf 1 r/w usb bus connect section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 877 of 1340 rej09b0499-0200 19.3.6 interrupt select register 2 (isr2) isr2 selects the vector numbers of the interrupt requests indicated in interrupt flag register 2 (ifr2). if the usb issues an interrupt request to th e intc when a bit in isr2 is cleared to 0, the interrupt corresponding to the bit will be usbintn2. if the usb issues an in terrupt request to the intc when a bit in isr2 is set to 1, the corresponding interrupt will be usbintn3. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 surse 1 r/w 3 cfdn 1 r/w 2 ? 1 r 1 setce 1 r/w 0 setie 1 r/w bit bit name initial value r/w description 7 6 5 ? ? ? 0 0 0 r r r reserved these bits are always read as 0. the write value should always be 0. 4 surse 1 r/w suspend/resume detection 3 cfdn 1 r/w end point information load end 2 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 1 setce 1 r/w set_configuration command detection 0 setie 1 r/w set_interface command detection section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 878 of 1340 rej09b0499-0200 19.3.7 interrupt enable register 0 (ier0) ier0 enables the interrupt requests of interrupt flag register 0 (ifr0). when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the cpu. the interrupt vector number is determined by the contents of interrupt select register 0 (isr0). bit bit name initial value r/w 7 brst 0 r/w 6 ep1 full 0 r/w 5 ep2 tr 0 r/w 4 ep2 empty 0 r/w 3 setup ts 0 r/w 2 ep0o ts 0 r/w 1 ep0i tr 0 r/w 0 ep0i ts 0 r/w bit bit name initial value r/w description 7 brst 0 r/w bus reset 6 ep1 full 0 r/w ep1 fifo full 5 ep2 tr 0 r/w ep2 transfer request 4 ep2 empty 0 r/w ep2 fifo empty 3 setup ts 0 r/w setup command receive complete 2 ep0o ts 0 r/w ep0o receive complete 1 ep0i tr 0 r/w ep0i transfer request 0 ep0i ts 0 r/w ep0i transmission complete section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 879 of 1340 rej09b0499-0200 19.3.8 interrupt enable register 1 (ier1) ier1 enables the interrupt requests of interrupt flag register 1 (ifr1). when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the cpu. the interrupt vector number is determined by the contents of interrupt select register 1 (isr1). bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ep3 tr 0 r/w 1 ep3 ts 0 r/w 0 vbusf 0 r/w bit bit name initial value r/w description 7 6 5 4 3 ? ? ? ? ? 0 0 0 0 0 r r r r r reserved these bits are always read as 0. the write value should always be 0. 2 ep3 tr 0 r/w ep3 transfer request 1 ep3 ts 0 r/w ep3 transmission complete 0 vbusf 0 r/w usb bus connect 19.3.9 interrupt enable register 2 (ier2) ier2 enables the interrupt requests of interrupt flag register 2 (ifr2). when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the cpu. the interrupt vector number is determined by the contents of interrupt select register 2 (isr2). bit bit name initial value r/w 7 ssrsme 0 r/w 6 ? 0 r 5 ? 0 r 4 surse 0 r/w 3 cfdn 0 r/w 2 ? 0 r 1 setce 0 r/w 0 setie 0 r/w section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 880 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 ssrsme 0 r/w resume detection for software standby cancel for the details of the operat ion, see section 19.5.3, suspend and resume operations. 6, 5 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 4 surse 0 r/w suspend/resume detection for the details of the operat ion, see section 19.5.3, suspend and resume operations. 3 cfdn 0 r/w end point information load end 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 setce 0 r/w set_configuration command detection 0 setie 0 r/w set_interface command detection 19.3.10 ep0i data register (epdr0i) epdr0i is an 8-byte transmit fifo buffer for endpoint 0. epdr0i holds one packet of transmit data for control-in. transmit data is fixed by writing one packet of data and setting ep0ipkte in the trigger register. when an ack handshake is returned from the host after the data has been transmitted, ep0its in interrupt flag register 0 is set. this fifo buffer ca n be initialized by means of ep0iclr in the fclr register. bit bit name initial value r/w 7 d7 undefined w 6 d6 undefined w 5 d5 undefined w 4 d4 undefined w 3 d3 undefined w 2 d2 undefined w 1 d1 undefined w 0 d0 undefined w bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for control-in transfer section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 881 of 1340 rej09b0499-0200 19.3.11 ep0o data register (epdr0o) epdr0o is an 8-byte receive fi fo buffer for endpoint 0. epdr0o holds endpoint 0 receive data other than setup commands. when data is received successfully, ep0ots in in terrupt flag register 0 is set, and the number of receive bytes is indi cated in the ep0o receive data size register. after the data has been read, setting ep0ordfn in the trigger register enables the next packet to be received. this fifo bu ffer can be initialized by means of bp0oclr in the fclr register. bit bit name initial value r/w 7 d7 0 r 6 d6 0 r 5 d5 0 r 4 d4 0 r 3 d3 0 r 2 d2 0 r 1 d1 0 r 0 d0 0 r bit bit name initial value r/w description 7 to 0 d7 to d0 all 0 r data register for control-out transfer 19.3.12 ep0s data register (epdr0s) epdr0s is an 8-byte fifo buffer specifically for receiving endpoint 0 se tup commands. only the setup command to be processed by the applicati on is received. when command data is received successfully, the setupts bit in interrupt flag register 0 is set. as a latest setup command must be received in high pr iority, if data is left in this buffer, it will be overwritten with new data. if recep tion of the next command is started while the current command is being read, command reception has priority, the r ead by the application is forcibly stopped, and the read data is invalid. bit bit name initial value r/w 7 d7 0 r 6 d6 0 r 5 d5 0 r 4 d4 0 r 3 d3 0 r 2 d2 0 r 1 d1 0 r 0 d0 0 r bit bit name initial value r/w description 7 to 0 d7 to d0 all 0 r data register for storing the setup command at the control-out transfer section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 882 of 1340 rej09b0499-0200 19.3.13 ep1 data register (epdr1) epdr1 is a 128-byte receive fifo buffer for endpoint 1. epdr1 ha s a dual-buffer configuration, and has a capacity of twice the maximum packet size. when one packet of data is received successfully, ep1full in interrupt flag register 0 is set, and th e number of receive bytes is indicated in the ep1 receive data size register. after the data ha s been read, the buffer that was read is enabled to receive data again by writing 1 to the ep1rdfn bit in th e trigger register. the receive data in this fifo buffer can be transferre d by dma. this fifo bu ffer can be initialized by means of ep1clr in the fclr register. bit bit name initial value r/w 7 d7 0 r 6 d6 0 r 5 d5 0 r 4 d4 0 r 3 d3 0 r 2 d2 0 r 1 d1 0 r 0 d0 0 r bit bit name initial value r/w description 7 to 0 d7 to d0 all 0 r data register for endpoint 1 transfer 19.3.14 ep2 data register (epdr2) epdr2 is a 128-byte transmit fifo buffer for end point 2. epdr2 has a dual-buffer configuration, and has a capacity of twice the maximum packet si ze. when transmit data is written to this fifo buffer and ep2pkte in the trigger register is set, one packet of transmit data is fixed, and the dual-fifo buffer is switched over. the transmit data for this fifo buffer can be transferred by dma. this fifo buffer can be initialized by means of ep2clr in the fclr register. bit bit name initial value r/w 7 d7 undefined w 6 d6 undefined w 5 d5 undefined w 4 d4 undefined w 3 d3 undefined w 2 d2 undefined w 1 d1 undefined w 0 d0 undefined w bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for endpoint 2 transfer section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 883 of 1340 rej09b0499-0200 19.3.15 ep3 data register (epdr3) epdr3 is an 8-byte transmit fifo buffer for endpoint 3. epdr3 holds one packet of transmit data for the interrupt transfer of endpoint 3. transmit data is fixed by writing one packet of data and setting ep3pkte in the trigger register. when an ack handshake is returned from the host after one packet of data has been transmitted successfully, ep3ts in interrupt flag register 0 is set. this fifo buffer can be initialized by mean s of ep3clr in the fclr register. bit bit name initial value r/w 7 d7 undefined w 6 d6 undefined w 5 d5 undefined w 4 d4 undefined w 3 d3 undefined w 2 d2 undefined w 1 d1 undefined w 0 d0 undefined w bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for endpoint 3 transfer 19.3.16 ep0o receive data size register (epsz0o) epsz0o indicates the number of bytes received at endpoint 0 from the host. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 7 to 0 ? all 0 r number of receive data for endpoint 0 section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 884 of 1340 rej09b0499-0200 19.3.17 ep1 receive data size register (epsz1) epsz1 is a receive data size resister for endpoint 1. epsz1 indicates the number of bytes received from the host. the fifo for endpoint 1 has a dual -buffer configuration. the size of the received data indicated by this register is the size of th e currently selected side (can be read by cpu). bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 7 to 0 ? all 0 r number of received bytes for endpoint 1 19.3.18 trigger register (trg) trg generates one-shot triggers to contro l the transfer sequen ce for each endpoint. bit bit name initial value r/w 7 ? undefined ? 6 ep3 pkte undefined w 5 ep1 rdfn undefined w 4 ep2 pkte undefined w 3 ? undefined ? 2 ep0s rdfn undefined w 1 ep0o rdfn undefined w 0 ep0i pkte undefined w bit bit name initial value r/w description 7 ? undefined ? reserved the write value should always be 0. 6 ep3 pkte undefined w ep3 packet enable after one packet of data has been written to the endpoint 3 transmit fifo buf fer, the transmit data is fixed by writing 1 to this bit. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 885 of 1340 rej09b0499-0200 bit bit name initial value r/w description 5 ep1 rdfn undefined w ep1 read complete write 1 to this bit after one packet of data has been read from the endpoint 1 fi fo buffer. the endpoint 1 receive fifo buffer has a dual-buffer configuration. writing 1 to this bit initializes the fifo that was read, enabling the next packet to be received. 4 ep2 pkte undefined w ep2 packet enable after one packet of data has been written to the endpoint 2 transmit fifo buf fer, the transmit data is fixed by writing 1 to this bit. 3 ? undefined ? reserved the write value should always be 0. 2 ep0s rdfn undefined w ep0s read complete write 1 to this bit after data for the ep0s command fifo has been read. writing 1 to this bit enables transfer of data in the fo llowing data stage. a nack handshake is returned in response to transfer requests from the host in the data stage until 1 is written to this bit. 1 ep0o rdfn undefined w ep0o read complete writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit fifo buffer initializes the fifo buffer, enabling the next packet to be received. 0 ep0i pkte undefined w ep0i packet enable after one packet of data has been written to the endpoint 0 transmit fifo buf fer, the transmit data is fixed by writing 1 to this bit. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 886 of 1340 rej09b0499-0200 19.3.19 data status register (dasts) dasts indicates whether the transmit fifo buffers contain valid data. a bit is set when data is written to the corresponding fifo buffer and the pack et enable state is set, and cleared when all data has been transmitted to the host. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ep3 de 0 r 4 ep2 de 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ep0i de 0 r bit bit name initial value r/w description 7 6 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 5 ep3 de 0 r ep3 data present this bit is set when the endpoint 3 fifo buffer contains valid data. 4 ep2 de 0 r ep2 data present this bit is set when the endpoint 2 fifo buffer contains valid data. 3 2 1 ? ? ? 0 0 0 r r r reserved these bits are always read as 0. 0 ep0i de 0 r ep0i data present this bit is set when the endpoint 0 fifo buffer contains valid data. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 887 of 1340 rej09b0499-0200 19.3.20 fifo clear register (fclr) fclr is a register to initialize the fifo buff ers for each endpoint. writing 1 to a bit clears all the data in the corresponding fifo buffer. note that the corresponding interr upt flag is not cleared. do not clear a fifo bu ffer during transfer. bit bit name initial value r/w 7 ? undefined ? 6 ep3 clr undefined w 5 ep1 clr undefined w 4 ep2 clr undefined w 3 ? undefined ? 2 ? undefined ? 1 ep0o clr undefined w 0 ep0i clr undefined w bit bit name initial value r/w description 7 ? undefined ? reserved the write value should always be 0. 6 ep3 clr undefined w ep3 clear writing 1 to this bit initializes the endpoint 3 transmit fifo buffer. 5 ep1 clr undefined w ep1 clear writing 1 to this bit initializes both sides of the endpoint 1 receive fifo buffer. 4 ep2 clr undefined w ep2 clear writing 1 to this bit initializes both sides of the endpoint 2 transmit fifo buffer. 3 2 ? ? undefined ? ? reserved the write value should always be 0. 1 ep0o clr undefined w ep0o clear writing 1 to this bit initializes the endpoint 0 receive fifo buffer. 0 ep0i clr undefined w ep0i clear writing 1 to this bit initializes the endpoint 0 transmit fifo buffer. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 888 of 1340 rej09b0499-0200 19.3.21 dma transfer setting register (dma) dma transfer can be carried out between the endpoint 1 and 2 data registers and memory by means of the on-chip direct memory access c ontroller (dmac). dual address transfer is performed in bytes. to start dm a transfer, dmac settings must be made in addition to the settings in this register. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 pullup_e 0 r/w 1 ep2dmae 0 r/w 0 ep1dmae 0 r/w bit bit name initial value r/w description 7 6 5 4 3 ? ? ? ? ? 0 0 0 0 0 r r r r r reserved these bits are always read as 0. the write value should always be 0. 2 pullup_e 0 r/w pullup enable this pin performs the pull-up control for the d+ pin, with using pm4 as the pull-up control pin. 0: d+ is not pulled up. 1: d+ is pulled up. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 889 of 1340 rej09b0499-0200 bit bit name initial value r/w description 1 ep2dmae 0 r/w endpoint 2 dma transfer enable when this bit is set, dma transfer is enabled from memory to the endpoint 2 transmit fifo buffer. if there is at least one byte of open space in the fifo buffer, a dmac start interrupt signal (usbintn1) is asserted. in dma transfer, when 64 bytes are written to the fifo buffer the ep2 packet enable bit is set automatically, allowing 64 bytes of data to be transferred, and if there is st ill space in the other side of the two fifos, the dm ac start interrupt signal (usbintn1) is asserted again. however, if the size of the data packet to be transmitted is less than 64 bytes, the ep2 packet enable bit is not set automatically, and so should be set by the cpu with a dma transfer end interrupt. as ep2-related interrupt requests to the cpu are not automatically masked, inte rrupt requests should be masked as necessary in the interrupt enable register. ? operating procedure 1. write of 1 to the ep2 dmae bit in dmar 2. set the dmac to activate through usbintn1 3. transfer count setting in the dmac 4. dmac activation 5. dma transfer 6. dma transfer end interrupt generated see section 19.8.3, dma transfer for endpoint 2. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 890 of 1340 rej09b0499-0200 bit bit name initial value r/w description 0 ep1dmae 0 r/w endpoint 1 dma transfer enable when this bit is set, a dmac start interrupt signal (usbintn0) is asserted and dma transfer is enabled from the endpoint 1 receive fifo buffer to memory. if there is at least one byte of receive data in the fifo buffer, the dmac start interrupt signal (usbintn0) is asserted. in dma transfer, when all the received data is read, ep1 is automatically read and the completion trigger operates. ep1-related interrupt requests to the cpu are not automatically masked. ? operating procedure: 1. write of 1 to the ep1 dmae bit in dma 2. set the dmac to activate through usbintn0 3. transfer count setting in the dmac 4. dmac activation 5. dma transfer 6. dma transfer end interrupt generated see section 19.8.2, dma transfer for endpoint 1. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 891 of 1340 rej09b0499-0200 19.3.22 endpoint stall register (epstl) the bits in epstl are used to forcibly stall the endpoints on the application side. while a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. the stall bit for endpoint 0 is cleared automatically on reception of 8-byte command data for which decoding is performed by the function and the ep0 stl bit is cleared. when the setupts flag in the ifr0 register is set to 1, writing 1 to the ep0 stl bit is ignored. fo r detailed operation, see section 19.7, stall operations. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ep3stl 0 r/w 2 ep2stl 0 r/w 1 ep1stl 0 r/w 0 ep0stl 0 r/w bit bit name initial value r/w description 7 6 5 4 ? ? ? ? 0 0 0 0 r r r r reserved these bits are always read as 0. the write value should always be 0. 3 ep3stl 0 r/w ep3 stall when this bit is set to 1, endpoint 3 is placed in the stall state. 2 ep2stl 0 r/w ep2 stall when this bit is set to 1, endpoint 2 is placed in the stall state. 1 ep1stl 0 r/w ep1 stall when this bit is set to 1, endpoint 1 is placed in the stall state. 0 ep0stl 0 r/w ep0 stall when this bit is set to 1, endpoint 0 is placed in the stall state. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 892 of 1340 rej09b0499-0200 19.3.23 configuration value register (cvr) this register stores the configur ation, interface, or alternate set value when the set configuration or set interface command from th e host is correctly received. bit bit name initial value r/w 7 cnfv1 0 r 6 cnfv0 0 r 5 intv1 0 r 4 intv0 0 r 3 ? 0 r 2 altv2 0 r 1 altv1 0 r 0 altv0 0 r bit bit name initial value r/w description 7 6 cnfv1 cnfv0 all 0 r these bits store c onfiguration setting value when they receive set configuration command. cnfv is updated when the setc bit in ifr2 is set to 1. 5 4 intv1 intv0 all 0 r these bits store interface setting value when they receive set interface command. intv is updated when the seti bit in ifr2 is set to 1. 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 altv2 0 r 1 altv1 0 r 0 altv0 0 r these bits store alternate setting value when they receive set interface command. altv2 to altv0 are updated when the seti bit in ifr2 is set to 1. 19.3.24 control register (ctlr) this register sets functions for bits asce, pwmd, rsme, and, pwups. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 rwups 0 r 3 rsme 0 r/w 2 pwmd 0 r/w 1 asce 0 r/w 0 ? 0 r section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 893 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 6 5 ? ? ? 0 0 0 r r r reserved these bits are always read as 0. the write value should always be 0. 4 rwups 0 r remote wakeup status this status bit indicates remote wakeup command from usb host is enabled or disabled. this bit is set to 0 wh en remote wakeup command from ubm host is disabled by device_remote_wakeup due to set feature or clear feature request. this bit is set to 1 when remote wakeup command is enabled. 3 rsme 0 r/w resume enable this bit releases the suspend state (or executes remote wakeup). when rsme is set to 1, resume request starts. if rsme is once set to 1, clear this bit to 0 again afterwards. in this case, the value 1 set to rsme must be kept for at least one clock period of 12-mhz clock. 2 pwmd 0 r/w bus power mode this bit specifies the usb power mode. when pwmd is set to 0, the self-power mode is selected for this module. when set to 1, the bus-power mode is selected. 1 asce 0 r/w automatic stall clear enable setting the asce bit to 1 automatically clears the stall setting bit (the epxstl (x = 0, 1, 2, or 3) bit in epstlr0 or epstr1) of the end point that has returned the stall handshake to the host. the automatic stall clear enable is common to the all end points. thus the individual control of the end point is not possible. when the asce bit is set to 0, the stall setting bit is not automatically cleared. this bit must be released by the users. to enable this bit, make sure that the asce bit should be set to 1 before the epxstl (x = 0, 1, 2, or 3) bit in epstl is set to 1. 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 894 of 1340 rej09b0499-0200 19.3.25 endpoint information register (epir) this register sets the informat ion for each endpoint. each endpoin t needs five bytes to store the information. writing data should be done in sequence starting at logical endpoint 0. do not write data of more than 50 bytes (five bytes multip lied by ten endpoints) to this register. the information should be written to this register only once at a reset and no data should be written after that. description of writing data for one endpoint is shown below. although this register consists of one register to which data is written sequentially for one address, the write data for the endpoint 0 is described as epir00 to epir05 (epir endpoint number in write order) to make the explanation understood easier. write should start at epir00. bit bit name initial value r/w 7 d7 undefined w 6 d6 undefined w 5 d5 undefined w 4 d4 undefined w 3 d3 undefined w 2 d2 undefined w 1 d1 undefined w 0 d0 undefined w ? epir00 bit bit name initial value r/w description 7 to 4 d7 to d4 undefined w endpoint number [enable setting range] 0 to 3 3, 2 d3, d2 undefined w endpoint configuration number [enable setting range] 0 or 1 1, 0 d1, d0 undefined w endpoint interface number [enable setting range] 0 to 3 section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 895 of 1340 rej09b0499-0200 ? epir01 bit bit name initial value r/w description 7, 6 d7, d6 undefined w endpoint alternate number [possible setting range] 0 or 1 5, 4 d5, d4 undefined w endpoint transmission [possible setting range] 0: control 1: setting prohibited 2: bulk 3: interrupt 3 d3 undefined w endpoint transmission direction [possible setting range] 0: out 1: in 2 to 0 d2 to d0 undefined w reserved [possible setting range] fixed to 0. ? epir02 bit bit name initial value r/w description 7 to 1 d7 to d1 undefined w endpoint maximum packet size [possible setting range] 0 to 64 0 d0 undefined w reserved [possible setting range] fixed to 0. ? epir03 bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w reserved [possible setting range] fixed to 0. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 896 of 1340 rej09b0499-0200 ? epir04 bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w endpoint fifo number [possible setting range] 0 to 3 the endpoint number is the endpoint number the usb host uses. the endpoint fifo number corresponds to the endpoint number described in this manual. thus data transfer between the usb host and the endpoint fifo can be enabled by putting the endpoint number and the endpoint fifo number in one-to-one correspondence. note that the setting value is subject to a limitation described below. since each endpoint fifo number is optimized by the exclusive software that corresponds to the transfer system, directio n, and the maximum packet size, ma ke sure to set the endpoint fifo number to the data described in table 19.2. 1. the endpoint fifo number 1 cannot designate other than the maximum packet size of 64 bytes, bulk transfer method, and out transfer direction. 2. endpoint number 0 and the endpoint fifo number must have one-on one relationship. 3. the maximum packet size for the endpoint fifo number 0 is 8 bytes only. 4. the endpoint fifo number 0 can specify only the maximum packet size and the data for the rest should be all 0. 5. the maximum packet size for the endpoint fifo numbers 1 and 2 is limited to 64 bytes. 6. the maximum packet size for the endpoint fifo numbers 3 is limited to 8 bytes. 7. the maximum number of endpoint information setting is ten. 8. up to ten endpoint information setting should be made. 9. write 0 to the endpoints not in use. table 19.2 shows the example of limitations for the maximum packet size, the transfer method, and the transfer direction. table 19.2 example of limi tations for setting values endpoint fifo number maximum packet si ze transfer method transfer direction 0 8 bytes control ? 1 64 bytes bulk out 2 64 bytes bulk in 3 8 bytes interrupt in section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 897 of 1340 rej09b0499-0200 table 19.3 shows a specific example of setting. table 19.3 example of setting endpoint number conf. int. alt. transfer method transfer direction maximum packet size endpoint fifo number 0 ? ? ? control in/out 8 bytes 0 1 1 0 0 bulk out 64 bytes 1 2 1 0 0 bulk in 64 bytes 2 3 1 0 0 interrupt in 8 bytes 3 ? 1 1 0 ? ? ? ? ? 1 1 1 ? ? ? ? n epir[n]0 epir[n]1 epir[ n]2 epir[n]3 epir[n]4 0 00 00 10 00 00 1 14 20 80 00 01 2 24 28 80 00 02 3 34 38 10 00 03 4 00 00 00 00 00 5 00 00 00 00 00 6 00 00 00 00 00 7 00 00 00 00 00 8 00 00 00 00 00 9 00 00 00 00 00 ? 1 ? 0 ? 0 0 1 2 3 0 1 2 3 control bulkout bulkin interruptin configuration interface alternate setting endpoint number endpoint fifo number attribute section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 898 of 1340 rej09b0499-0200 19.3.26 transceiver test register 0 (trntreg0) trntreg0 controls the on-chip transceiver output signals. setting the ptste bit to 1 specifies the transceiver output signals (usd+ and usd-) arbitrarily. table 19.4 shows the relationship between trntreg0 setting and pin output. bit bit name initial value r/w 7 ptste 0 r/w 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 suspend 0 r/w 2 txenl 0 r/w 1 txse0 0 r/w 0 txdata 0 r/w bit bit name initial value r/w description 7 ptste 0 r/w pin test enable enables the test control for the on-chip transceiver output pins (usd+ and usd-). 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 suspend txenl txse0 txdata 0 0 0 0 r/w r/w r/w r/w on-chip transceiver output signal setting suspend: sets the (suspend) signal of the on-chip transceiver. txenl: sets the output enable (txenl) signal of the on-chip transceiver. txse0: sets the signal-ended 0 (txse0) signal of the on-chip transceiver. txdata: sets the (txdata) signal of the on-chip transceiver. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 899 of 1340 rej09b0499-0200 table 19.4 relationship between trntreg0 setting and pin output pin input register setting pin output vbus ptste txenl txse0 txdata usd+ usd- 0 x x x x hi-z hi-z 1 0 x x x ? ? 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 x 0 0 1 1 1 x x hi-z hi-z [legend] x: don't care. ? : cannot be controlled. indicates state in nor mal operation according to the usb operation and port settings. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 900 of 1340 rej09b0499-0200 19.3.27 transceiver test register 1 (trntreg1) trntreg1 is a test register that can m onitor the on-chip transceiver input signal. setting bits ptste and txenl in trntreg0 to 1 enables monitoring the on-chip transceiver input signal. table 19.5 shows the relationship between pin input and trntreg1 monitoring value. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 xver_data ? * r 1 dpls ? * r 0 dmns ? * r bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 xver_data dpls dmns ? * ? * ? * r r r on-chip transceiver input signal monitor xver_data: monitors the differential input level (xver_data) signal of the on-chip transceiver. dpls: monitors the usd+ (dpls) signal of the on- chip transceiver. dmns: monitors the usd- (dmns) signal of the on- chip transceiver. note: * determined by the state of pins, vbus, usd+, and usd- section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 901 of 1340 rej09b0499-0200 table 19.5 relationship between pin input and trntreg1 monitoring value register setting pin input trntreg1 monitoring value ptste suspend vbus usd+ usd- xver_data dpls dmns remarks 0 x x x x 0 0 0 cannot be monitored when ptste = 0 1 0 1 0 0 x 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 x 1 1 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 0 1 1 can be monitored when ptste = 1 1 x 0 x x 0 1 1 can be monitored when vbus = 0 [legend] x: don't care. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 902 of 1340 rej09b0499-0200 19.4 interrupt sources this module has five interrupt signals. table 19.6 shows the interrupt sources and their corresponding interrupt request signals. the usbint n interrupt signals are activated at low level. the usbintn interrupt requests can on ly be detected at low level (s pecified as level sensitive). table 19.6 interrupt sources register bit transfer mode interrupt source description interrupt request signal dtc activation dmac activation ifr0 0 ep0i_ts * ep0i transfer complete usbintn2 or usbintn3 1 control transfer (ep0) ep0i_tr * ep0i transfer request usbintn2 or usbintn3 2 ep0o_ts * ep0o receive complete usbintn2 or usbintn3 3 setup_ts * setup command receive complete usbintn2 or usbintn3 4 bulk_in transfer (ep2) ep2_empty ep2 fifo empty usbintn2 or usbintn3 usbintn1 5 ep2_tr ep2 transfer request usbintn2 or usbintn3 6 bulk_out transfer (ep1) ep1_full ep1 fifo full usbintn2 or usbintn3 usbintn0 7 status brst bus reset usbintn2 or usbintn3 ifr1 0 status vbusf usb disconnection detection usbintn2 or usbintn3 1 ep3_ts ep3 transfer complete usbintn2 or usbintn3 2 interrupt_in transfer (ep3) ep3_tr ep3 transfer request usbintn2 or usbintn3 3 status vbusmn vbus connection status ? 4 5 ? reserved ? ? ? ? 6 7 section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 903 of 1340 rej09b0499-0200 register bit transfer mode interrupt source description interrupt request signal dtc activation dmac activation 0 seti set_interface command detection usbintn2 or usbintn3 1 status setc set_configuration command detection usbintn2 or usbintn3 2 ? reserved ? ? ? ? ifr2 3 cfdn endpoint information load end usbintn2 or usbintn3 4 status sursf suspend/resume detection usbintn2, usbintn3, or resume 5 surss suspend/resume status ? 6 7 ? reserved ? ? ? ? note: * ep0 interrupts must be assigned to the same interrupt request signal. ? usbintn0 signal dmac start interrupt signal only ep1. see section 19.8, dma transfer. ? usbintn1 signal dmac start interrupt signal only ep2. see section 19.8, dma transfer. ? usbintn2 signal the usbintn2 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 2 (isr0 to isr2) are cleared to 0. the usbintn2 is driven low if a corresponding bit in the interrupt flag register is set to 1. ? usbintn3 signal the usbintn3 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 2 (isr0 to isr2) are cleared to 0. the usbintn3 is driven low if a corresponding bit in the interrupt flag register is set to 1. ? resume signal the resume signal is a resume interrupt signal for canceling software standby mode and deep software standby mode. the resume signal is driven low at the transition to the resume state for canceling software standby mo de and deep software standby mode. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 904 of 1340 rej09b0499-0200 19.5 operation 19.5.1 cable connection usb function application cable disconnected vbus pin = 0 v udc core reset usb cable connection ifr1.vbusf = 1 usb bus connection interrupt udc core reset release bus reset reception ifr0.brst = 1 bus reset interrupt wait for setup command reception complete interrupt general output port d+ pull-up enabled? usb module interrupt setting as soon as preparations are completed, enable d+ pull-up in general output port clear vbusf flag (ifr1.vbusf) firmware preparations for start of usb communication clear bus reset flag (ifr0.brst) clear fifos (ep0, ep1, ep2, ep3) yes no initial settings wait for setup command reception complete interrupt interrupt request interrupt request figure 19.2 cable connection operation the above flowchart shows the operation in the case of in section 19.9, ex ample of usb external circuitry. in applications that do not re quire usb cable connection to be detected, processing by the usb bus connection interrupt is not necessary. preparations should be made with the bus-reset interrupt. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 905 of 1340 rej09b0499-0200 19.5.2 cable disconnection usb function application cable connected vbus pin = 1 usb cable disconnection vbus pin = 0 udc core reset end figure 19.3 cable disconnection operation the above flowchart shows the operation in section 19.9, example of usb external circuitry. 19.5.3 suspend and resume operations (1) suspend operation if the usb bus enters the suspen d state from the non-suspend st ate, perform the operation as shown in figure 19.4. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 906 of 1340 rej09b0499-0200 usb cable connected bus idle of 3 ms or more occurs suspend/resume interrupt occurs (ifr2/sursf = 1) resume remote wakeup enabled? (ctlr/rwups = 1?) clear sursf in ifr2 to 0 check if surss in ifr2 is set to 1 clear surse in ier2 to 0 wait for suspend/ resume interrupt ye s ye s no no enter deep software standby mode check remote-wakeup function enabled system needs to enter power-down mode? check remote-wakeup function disabled ye s no need to enter software standby mode? usb function application set ssrsme in ier2 to 0 set ssrsme in ier2 to 1 usb module stop need to enter deep software standby mode? clear ramcut in dpstbycr to 0 set wtsts5 to wtsts0 in dpsbwcr clear dusbif in dpsifr to 0 set dusbie in dpsier to 1 set sts5 to sts0 in sbycr clear surse in ier2 to 0 enter software standby mode no ye s set surse in ier2 to 1 clear ssrsme in ier2 to 0 notes: 1. for details, see section 27, power-down modes. 2. when the usb enters deep software standby mode, the sources to cancel software standby mode may be conflicted. in this figure, the operation to cancel software standby mode is not performed. for details, see section 27.12, usage notes. 1 1 2 figure 19.4 suspend operation section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 907 of 1340 rej09b0499-0200 (2) resume operation from up-stream if the usb bus enters the non-susp end state from the suspend state by resume signal output from up-stream, perform the operatio n as shown in figure 19.5. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 908 of 1340 rej09b0499-0200 usb cable connected usb bus in suspend state resume interrupts is requested from the up-stream. suspend/resume interrupt occurs. (ifr2/sursf = 1) resume start usb operating clock oscillation usb function application cancel software standby mode clear sursf in ifr2 to 0 set surse in ier2 to 1 clear ssrsme in ier2 to 0 check if surss in ifr2 is cleared to 0 software standby mode ? usb module stopped? oscillation stabilization time has passed? no no no ye s ye s ye s cancel usb module stop return to normal state deep software standby mode ? no oscillation stabilization time has passed? cancel deep software standby mode ye s ye s no cancel usb module stop clear sursf in ifr2 to 0 check if surss in ifr2 is cleared to 0 set surse in ier2 to 1 clear ssrsme in ier2 to 0 clear dusbif in dpsifr to 0 clear dusbie in dpsier to 0 usb communications can be resumed execute reset exception handling note: * for details, see section 27.8, deep software standby mode. * figure 19.5 resume operation from up-stream section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 909 of 1340 rej09b0499-0200 (3) transition from suspend state to softwa re standby mode and canceling software standby mode if the usb bus enters from the su spend state to software standby mode, perform the operation as shown in figure 19.6. when canceling software standby mode, ensure enough time for the system clock oscillation to be settled. transition from suspend state to software standby mode (1) (2) (3) (4) (5) (6) (7) detect that usb bus is in suspend state set sursf in ifr2 to 1 usbintn interrupt clear sursf in ifr2 to 0 check if surss in ifr2 is set to 1 clear surse in ier2 to 0 set ssrsme in ier2 to 1 shift to software standby mode (execute sleep instruction) stop all clocks of lsi canceling software standby mode detect that usb bus is in resume state resume interrupt cancel software standby mode wait for system clock oscillation to be settled clear sursf in ifr2 to 0 check if surss in ifr2 is cleared to 0 set surse in ier2 to 1 clear ssrsme in ier2 to 0 usb communications can be resumed through usb registers denotation of figures : operation by firmware setting : automatic operation by lsi hardware (8) (9) (10) (11) (12) figure 19.6 flow of transition to and canceling software standby mode section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 910 of 1340 rej09b0499-0200 oscillation settling time usb bus state usbintn interrupt sursf surss ssrsme = 1 resume interrupt software standby software standby oscillator usb dedicated clock (cku) module clock (p ) normal suspend resume normal (1) (2) (5) (6) (7) (7) (9) (10) (11) (11) (12) (3) (8) (4) (4) figure 19.7 timing of transition to and canceling software standby mode section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 911 of 1340 rej09b0499-0200 (4) transition from suspend state to deep so ftware standby mode and canceling deep software standby mode if the usb bus enters from the suspend state to deep softwa re standby mode, perform the operation as shown in figure 19.8. when canceling deep software standby mode, ensure enough time for the system clock oscillation to be settled. transition from suspend state to deep software standby mode (1) (2) (3) (4) (5) (6) (7) detect that usb bus is in suspend state set sursf in ifr2 to 1 usbintn interrupt clear sursf in ifr2 to 0 check if surss in ifr2 is set to 1 clear surse in ier2 to 0 clear ssrsme in ier2 to 0* clear dusbif in dpsifr to 0 set dusbie in dpsier to 1 shift to deep software standby mode (execute sleep instruction) stop all clocks of lsi canceling deep software standby mode detect that usb bus is in resume state resume interrupt cancel deep software standby mode wait for system clock oscillation to be settled clear sursf in ifr2 to 0 check if surss in ifr2 is cleared to 0 usb communications can be resumed through usb registers denotation of figures : operation by firmware setting : automatic operation by lsi hardware (8) ( 9 ) (10) (13) (14) (11) (12) set surse in ier2 to 1 set ssrsme in ier2 to 0 clear dusbif in dpsifr to 0 clear dusbie in dpsier to 0 execute reset sequence cancel module stop note: * when the usb enters deep software standby mode, the sources to cancel software standby mode may be conflicted. in this figure, the operation to cancel software standby mode is not performed. for details, see section 27.12, usage notes. figure 19.8 flow of transition to and canceling deep software standby mode section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 912 of 1340 rej09b0499-0200 usb bus state usbintn interrupt mod ule clock ( p ) usb dedicated clock (cku) deep software standby usb module stop (mstpc11) internal reset oscillator sursf oscillation settling time deep software standby module stop period surss dusbif dusbie resume interrupt (1) (3) (2) (4) (6) (12) (11) (14) (14) (9) (10) (6) (7) (7) (7) (5) (5) (4) (13) (8) resume normal suspend normal (13) figure 19.9 timing of transition to and canceling deep software standby mode section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 913 of 1340 rej09b0499-0200 (5) remote-wakeup operation if the usb bus enters the non-su spend (resume) state from the suspend state by the remote- wakeup signal output from this function, perform the operation as shown in figure 19.10. usb cable connected usb bus in suspend state cancel software standby mode clear sursf in ifr2 to 0 check if surss in ifr2 is cleared to 0 software standby mode ? usb module stopped? oscillation stabilization time has passed? no no no ye s ye s ye s start usb operating clock oscillation cancel usb module stop remote wakeup execution (ctlr/rsme= 1) return to normal state ye s no bus wakeup source generated remote wakeup enabled? (ctlr/rwups = 1?) wait for resume from up-stream resume output signal suspend/resume interrupt occurs. (ifr2/sursf = 1) resume usb function application figure 19.10 remote-wakeup section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 914 of 1340 rej09b0499-0200 19.5.4 control transfer control transfer consists of three stages: setup, data (not always included), and status (figure 19.11). the data stage comprises a number of bus transactions. operatio n flowcharts for each stage are shown below. control-in setup stage data stage status stage control-out no data setup(0) data0 setup(0) data0 setup(0) data0 in(1) data1 out(1) data1 in(0) data0 out(0) . . . . . . data0 in(0/1) data0/1 out(0/1) data0/1 out(1) data1 in(1) data1 in(1) data1 figure 19.11 transfer st ages in control transfer section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 915 of 1340 rej09b0499-0200 (1) setup stage usb function application setup token reception receive 8-byte command data in ep0s to data stage set setup command reception complete flag (ifr0.setup ts = 1) automatic processing by this module clear setup ts flag (ifr0.setup ts = 0) clear ep0i fifo (fclr.ep0iclr = 1) clear ep0o fifo (fclr.ep0oclr = 1) read 8-byte data from ep0s decode command data determine data stage direction * 1 write 1 to ep0s read complete bit (trg.ep0s rdfn = 1) to control-in data stage to control-out data stage command to be processed by application? interrupt request yes no notes: 1. in the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). 2. when the transfer direction is control-out, the ep0i transfer request interrupt required in the status stage should be enabled here. when the transfer direction is control-in, this interrupt is not required and should be disabled. * 2 figure 19.12 setup stage operation section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 916 of 1340 rej09b0499-0200 (2) data stage (control-in) usb function application in token reception data transmission to host set ep0i transmission complete flag (ifr0.ep0i ts = 1) from setup stage write data to ep0i data register (epdr0i) write 1 to ep0i packet enable bit (trg.ep0i pkte = 1) clear ep0i transmission complete flag (ifr0.ep0i ts = 0) write 1 to ep0i packet enable bit (trg.ep0i pkte = 1) write data to ep0i data register (epdr0i) 1 written to trg.ep0s rdfn? valid data in ep0i fifo? nack nack no no yes yes ack interrupt request figure 19.13 data stag e (control-in) operation the application first analyzes comm and data from the host in the setup stage, and determines the subsequent data stage direction. if the result of co mmand data analysis is that the data stage is in- transfer, one packet of data to be sent to the host is written to the fifo. if there is more data to be sent, this data is written to the fifo after the data written first has been sent to the host (ep0its bit in ifr0 = 1). the end of the data stage is identified when the host transmits an out token and the status stage is entered. note: if the size of the data transmitted by the fu nction is smaller than the data size requested by the host, the function indicates the end of the da ta stage by returning to the host a packet shorter than the maximum packet size. if the size of the data transmitted by the function is an integral multiple of the maximum packet si ze, the function indicates the end of the data stage by transmitting a zero-length packet. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 917 of 1340 rej09b0499-0200 (3) data stage (control-out) usb function application out token reception data reception from host out token reception set ep0o reception complete flag (ifr0.ep0o ts = 1) clear ep0o reception complete flag (ifr0.ep0o ts = 0) read data from ep0o receive data size register (epsz0o) write 1 to ep0o read complete bit (trg.ep0o rdfn = 1) read data from ep0o data register (epdr0o) 1 written to trg.ep0s rdfn? 1 written to trg.ep0o rdfn? nack nack ack no yes no yes interrupt request figure 19.14 data stag e (control-out) operation the application first analyzes comm and data from the host in the setup stage, and determines the subsequent data stage direction. if the result of co mmand data analysis is that the data stage is out- transfer, the application waits fo r data from the host, and after data is received (ep0ots bit in ifr0 = 1), reads data from the fifo. next, the application writes 1 to the ep0o read complete bit, empties the receive fifo, and waits for reception of the next data. the end of the data stage is identified when the ho st transmits an in token and the status stage is entered. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 918 of 1340 rej09b0499-0200 (4) status stage (control-in) usb function application out token reception 0-byte reception from host end of control transfer set ep0o reception complete flag (ifr0.ep0o ts = 1) clear ep0o reception complete flag (ifr0.ep0o ts = 0) write 1 to ep0o read complete bit (trg.ep0o rdfn = 1) end of control transfer ack interrupt request figure 19.15 status stage (control-in) operation the control-in status stage star ts with an out token from the host. the application receives 0- byte data from the host, and ends control transfer. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 919 of 1340 rej09b0499-0200 (5) status stage (control-out) usb function application in token reception 0-byte transmission to host end of control transfer set ep0i transmission complete flag (ifr0.ep0i ts = 1) clear ep0i transfer request flag (ifr0.ep0i tr = 0) write 1 to ep0i packet enable bit (trg.ep0i pkte = 1) clear ep0i transmission complete flag (ifr0.ep0i ts = 0) end of control transfer valid data in ep0i fifo? ack yes no nack interrupt request interrupt request figure 19.16 status stage (control-out) operation the control-out status stage starts with an in token from the host. when an in-token is received at the start of the status stage, there is not yet any data in the ep0i fifo, and so an ep0i transfer request interrupt is generated. the application recognizes from this interrupt that the status stage has started. next, in order to transmit 0-byte data to the host, 1 is written to the ep0i packet enable bit but no data is written to the ep0i fifo. as a result, the next in token causes 0-byte data to be transmitted to the host, and control transfer ends. after the application has finished all processing relating to the data stage, 1 should be written to the ep0i packet enable bit. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 920 of 1340 rej09b0499-0200 19.5.5 ep1 bulk-out transfer (dual fifos) usb function application out token reception data reception from host set ep1 fifo full status (ifr0.ep1 full = 1) clear ep1 fifo full status (ifr0.ep1 full = 0) read ep1 receive data size register (epsz1) read data from ep1 data register (epdr1) write 1 to ep1 read complete bit (trg.ep1 rdfn = 1) space in ep1 fifo? no yes both ep1 fifos empty? no yes nack ack interrupt request interrupt request figure 19.17 ep1 bulk-out transfer operation ep1 has two 64-byte fifos, but the user can recei ve data and read receive data without being aware of this dual-fifo configuration. when one fifo is full afte r reception is completed, the ep1full b it in ifr0 is set. after the first receive operation into on e of the fifos when both fifos are em pty, the other fifo is empty, and so the next packet can be receiv ed immediately. when both fifos are full, nack is returned to the host automatically. wh en reading of the receive data is co mpleted following data reception, 1 is written to the ep1rdfn bit in trg. this operation empties the fifo that has just been read, and makes it ready to receive the next packet. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 921 of 1340 rej09b0499-0200 19.5.6 ep2 bulk-in transf er (dual fifos) usb function application in token reception data transmission to host clear ep2 transfer request flag (ifr0.ep2 tr = 0) enable ep2 fifo empty interrupt (ier0.ep2 empty = 1) ifr0.ep2 empty interrupt write one packet of data to ep2 data register (epdr2) write 1 to ep2 packet enable bit (trg.ep2 pkte = 1) set ep2 empty status (ifr0.ep2 empty = 1) valid data in ep2 fifo? nack ack interrupt request yes no clear ep2 empty status (ifr0.ep2 empty = 0) space in ep2 fifo? no yes interrupt request figure 19.18 ep2 bulk-in transfer operation ep2 has two 64-byte fifos, but the user can transmit data and write transmit data without being aware of this dual-fifo configuration. however, one data write is performed for one fifo. for example, even if both fifos ar e empty, it is not possible to pe rform ep2pkte at one time after consecutively writing 128 bytes of data. ep2pk te must be performed for each 64-byte write. when performing bulk-in transfer, as there is no valid data in the fifos on reception of the first in token, an ep2tr bit interrupt in ifr0 is requested. with this interrupt, 1 is written to the ep2empty bit in ier0, and the ep2 fifo empty interrupt is enabled. at first, both ep2 fifos are empty, and so an ep2 fifo empty interrupt is generated immediately. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 922 of 1340 rej09b0499-0200 the data to be transmitted is written to the data re gister using this interrupt. after the first transmit data write for one fifo, the other fifo is empty, and so the next transmit data can be written to the other fifo immediately. when both fifos are fu ll, ep2 empty is cleared to 0. if at least one fifo is empty, the ep2empty bit in ifr0 is set to 1. when ack is returned from the host after data transmission is completed, the fifo used in the data transmission becomes empty. if the other fifo contains valid transmit data at this time, transmission can be continued. when transmission of all data has been completed, write 0 to the ep2empty bit in ier0 and disable interrupt requests. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 923 of 1340 rej09b0499-0200 19.5.7 ep3 interrupt-in transfer usb function application in token reception data transmission to host set ep3 transmission complete flag (ifr1.ep3 ts = 1) write data to ep3 data register (epdr3) write 1 to ep3 packet enable bit (trg.ep3 pkte = 1) clear ep3 transmission complete flag (ifr1.ep3 ts = 0) write data to ep3 data register (epdr3) write 1 to ep3 packet enable bit (trg.ep3 pkte = 1) valid data in ep3fifo? is there data for transmission to host? is there data for transmission to host? no yes no yes no yes nack ack note: this flowchart shows just one example of interrupt transfer processing. other possibilities include an operation flow in which, if there is data to be transferred, the ep3 de bit in the data status register is referenced to confirm that the fifo is empty, and then data is written to the fifo. interrupt request figure 19.19 operation of ep3 interrupt-in transfer section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 924 of 1340 rej09b0499-0200 19.6 processing of usb standard commands and class/vendor commands 19.6.1 processing of commands transmitted by control transfer a command transmitted from the host by control tr ansfer may require decoding and execution of command processing on the application side. whether command decoding is required on the application side is indicated in table 19.7 below. table 19.7 command decoding on application side decoding not necessary on application si de decoding necessary on application side clear feature get configuration get interface get status set address set configuration set feature set interface get descriptor class/vendor command set descriptor sync frame if decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed auto matically. no processing is nece ssary by the user. an interrupt is not generated in this case. if decoding is necessary on the application side, this module stores the command in the ep0s fifo. after reception is completed successfully, the ifr0/setup ts flag is set and an interrupt request is generated. in the interrupt routine, eight bytes of data must be read from the ep0s data register (epdr0s) and de coded by firmware. the necessary data stage and status stage processing should then be carried out according to the result of the decoding operation. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 925 of 1340 rej09b0499-0200 19.7 stall operations 19.7.1 overview this section describes stall operations in this module. there are two cases in which the usb function module stall function is used: ? when the application forcibly stal ls an endpoint for some reason ? when a stall is performed automatically within the usb function module due to a usb specification violation the usb function module has internal status bits that hold the status (sta ll or non-stall) of each endpoint. when a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. these bits cannot be cleared by the application; they must be cleared with a clear feature command from the host. however, the internal status bit for ep0 is automatically cleared only when the setup command is received. 19.7.2 forcible stall by application the application uses the epstl register to issu e a stall request for the usb function module. when the application wishes to st all a specific endpoint, it sets th e corresponding bit in epstl (1- 1 in figure 19.20). the internal status bits are no t changed at this time. when a transaction is sent from the host for the endpoint for which the epstl bit was set, the usb function module references the internal status bit, and if this is not set, referen ces the corresponding bit in epstl (1-2 in figure 19.20). if the corresponding bit in epstl is set, the usb function module sets the internal status bit and returns a stall handshake to the host (1 -3 in figure 19.20). if the corresponding bit in epstl is not set, the internal status bit is not changed and the transaction is accepted. once an internal status bit is set, it remains set until cleared by a clear feature command from the host, without regard to the epstl register. even after a bit is cleared by the clear feature command (3-1 in figure 19.20), the usb function module continues to return a stall handshake while the bit in epstl is set, since the internal st atus bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 19.20) . to clear a stall, theref ore, it is necessary for the corresponding bit in epstl to be cleared by the application, and also for the internal status bit to be cleared with a clear feature command (2-1, 2-2, and 2-3 in figure 19.20). section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 926 of 1340 rej09b0499-0200 (1) transition from normal operation to stall (1-1) transaction request usb reference (1-2) stall handshake stall to (2-1) or (3-1) normal status restored (1-3) (2) when clear feature is sent after epstl is cleared (2-1) stall handshake transaction request (2-2) clear feature command clear feature command (2-3) (3) when clear feature is sent before epstl is cleared to 0 (3-1) 1. 1 written to epstl by application 1. in/out token received from host 2. epstl referenced 1. transmission of stall handshake 1. internal status bit cleared to 0 1. internal status bit cleared to 0 2. epstl not changed 1. 1 set in epstl 2. internal status bit set to 1 3. transmission of stall handshake 1. epstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. epstl not referenced 5. internal status bit not changed to (1-2) internal status bit 0 epstl 0 1 internal status bit 0 epstl 1 internal status bit 0 1 epstl 1 internal status bit 1 epstl 1 0 internal status bit 1 epstl 0 internal status bit 1 0 epstl 0 internal status bit 1 0 epstl 1 figure 19.20 forcible stall by application section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 927 of 1340 rej09b0499-0200 19.7.3 automatic stall by usb function module when a stall setting is made with the set featur e command, or in the event of a usb specification violation, the usb function module automatically sets the internal status bit for the relevant endpoint without regard to the epstl register, and returns a stall handshake (1-1 in figure 19.21). once an internal status bit is set, it remains set until cleared by a clear feature command from the host, without regard to the epstl register. afte r a bit is cleared by th e clear feature command, epstl is referenced (3-1 in figure 19.21). the usb function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2- 2 in figure 19.21). to cl ear a stall, therefore, the internal status bit must be cleared with a clear feature command (3-1 in figure 19.21). if set by the application, epstl should also be cleared (2-1 in figure 19.21). (1) transition from normal operation to stall (1-1) (2) when transaction is performed when internal status bit is set, and clear feature is sent (2-1) stall handshake transaction request stall handshake (2-2) clear feature command (3) when clear feature is sent before transaction is performed (3-1) 1. in case of usb specification violation, etc., usb function module stalls endpoint automatically 1. transmission of stall handshake 1. internal status bit cleared to 0 2. epstl not changed 1. epstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. epstl not referenced 5. internal status bit not changed normal status restored internal status bit 0 1 epstl 0 internal status bit 1 epstl 0 internal status bit 1 epstl 0 internal status bit 1 0 epstl 0 stall status maintained to (2-1) or (3-1) figure 19.21 automatic stall by usb function module section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 928 of 1340 rej09b0499-0200 19.8 dma transfer 19.8.1 overview dma transfer can be performed for endpoints 1 and 2 in this module. note that word or longword data cannot be transferred. when endpoint 1 holds at least one byte of valid receive data, a dma requ est for endpoint 1 is generated. when endpoint 2 holds no valid data , a dma request for endpoint 2 is generated. if the dma transfer is enabled by setting the ep1d mae bit in the dma transfer setting register to 1, zero-length data reception at endpoint 1 is ignored. when the dma transfer is enabled, the rdfn bit for ep1 and pkte bit for ep2 do not need to be set to 1 in trg (note that the pkte bit must be set to 1 when the transfer data is less than the maximum number of bytes). when all the data received at ep1 is read, the fifo automati cally enters the empty state. when the maximum number of bytes (64 bytes) are written to the ep 2 fifo, the fifo automatically enters the full state, and the data in the fifo can be transmitted (see figures 19.22 and 19.23). 19.8.2 dma transfer for endpoint 1 when the data received at ep1 is transferred by the dma, the usb function module automatically performs the same processing as writing 1 to the rdfn bit in trg if the currently sel ected fifo becomes empty. accordingly, in dma transfer, do not write 1 to the rdfn bit for ep1 in trg. if the user writes 1 to the rdfn bit in dma tran sfer, correct operation cannot be guaranteed. figure 19.22 shows an example of receiving 150 bytes of data from the host. in th is case, internal processing which is the same as writing 1 to the rdfn bit in trg is automatically performed three times. this internal processing is performe d when the currently sel ected data fifo becomes empty. accordingly, this processing is automatically performed both when 64-byte data is sent and when data less than 64 bytes is sent. rdfn (automatically performed) rdfn (automatically performed) rdfn (automatically performed) 64 bytes 64 bytes 22 bytes figure 19.22 rdfn bit operation for ep1 section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 929 of 1340 rej09b0499-0200 19.8.3 dma transfer for endpoint 2 when the transmit data at ep2 is transferred by the dma, the usb function module automatically performs the same processing as writing 1 to the pkte bit in trg if the cu rrently selected fifo (64 bytes) becomes full. accordingly, to transfer data of a multiple of 64 bytes, the user need not write 1 to the pkte bit in trg. to transfer data of less than 64 bytes, the user must write 1 to the pkte bit using the dma transfer end interrupt of the on-chip dmac. if the user writes 1 to the pkte bit when the maximum number of bytes (64 bytes) are transferred, correct operation cannot be guaranteed. figure 19.23 shows an example for transmitting 150 bytes of data to the host. in this case, internal processing which is the same as writing 1 to the pkte bit in trg is automatically performed twice. this internal processing is performed when the currently selected data fifo becomes full. accordingly, this processing is automatically performed only when 64-byte data is sent. when the last 22 bytes are sent, the internal processing for writing 1 to the pkte bit in trg is not performed, and the user must write 1 to the pkte bit by software. in this case, the application has no more data to transfer but the usb function module continues to output dma requests for ep2 as long as the fifo has an empty space. when all data has been transferred, write 0 to the ep2dmae bit in dmar to cancel dma requests for ep2. pkte (automatically performed) pkte (automatically performed) pkte is not performed execute by dma transfer end interrupt (user) 64 bytes 64 bytes 22 bytes figure 19.23 pkte bit operation for ep2 section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 930 of 1340 rej09b0499-0200 19.9 example of usb external circuitry 1. usb transceiver this module supports the on-chip transceive r only, not the external transceiver. 2. d+ pull-up control the general output port (pm4) is used for d+ pull-up control pin. the pm4 pin is driven high by the pullup_e bit of dma when the usb cable vbus is connected. thus, usb host/hub connection notification (d+ pull-up) is enabled. 3. detection of usb cable connection/disconnection as usb states, etc., are managed by hardware in this module, a vbus signal that recognizes connection/disconnection is necessary. the power supply signal (vbus) in the usb cable is used for this purpose. however, if the cabl e is connected to the usb host/hub when the function (system installing this lsi) power is off, a voltage (5 v) will be applied from the usb host/hub. therefore, an ic (such as an hd74lv1g08a or 2g08a) that allows voltage application when the system power is off should be connected externally. vcc regulator * 1 vcc (3.3 v) vbus (5 v) 1.5 k vcc (3.3 v) drvcc (3.3 v) usd+ d+ vbus * 3 pm4 notes: 1. 2. 3. vcc * 2 usd- drvss vss gnd d- usb connector on-chip transceiver external pull-up control circuit supporting full-speed reduce voltage to the operating voltage (vcc) of this lsi (3.3 v). to protect this lsi from being damaged, use the ic (such as hd74lv-a series) which can be applied voltage even when the system power is turned off. prevent noise from the vbus pin while the usb is performing communication. pullup_e usb figure 19.24 example of ci rcuitry in bus power mode section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 931 of 1340 rej09b0499-0200 notes: 1. 2. to protect this lsi from being damaged, use the ic (such as hd74lv-a series) which can be applied voltage even when the system power is turned off. prevent noise from the vbus pin while the usb is performing communication. vcc 3.3 v vbus (5 v) vcc (3.3 v) drvcc (3.3 v) usd+ d+ vbus * 2 pm4 vcc * 1 vcc * 1 usd- drvss vss gnd d- usb connector on-chip transceiver external pull-up control circuit supporting full-speed pullup_e usb 1.5 k figure 19.25 example of ci rcuitry in self power mode section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 932 of 1340 rej09b0499-0200 19.10 usage notes 19.10.1 receiving setup data note the following for epdr0s th at receives 8-byte setup data: 1. as a latest setup command must be received in high priority, the write from the usb bus takes priority over the read from the cpu. if the ne xt setup command reception is started while the cpu is reading data after the data is received, the read from the cpu is forcibly terminated. therefore, the data read after r eception is started becomes invalid. 2. epdr0s must always be read in 8-byte units. if the read is terminated at a midpoint, the data received at the next setup cannot be read correctly. 19.10.2 clearing the fifo if a usb cable is disconnected during data tran sfer, the data being received or transmitted may remain in the fifo. when disconn ecting a usb cable, clear the fifo. while a fifo is transferring da ta, it must not be cleared. 19.10.3 overreading and overwriting the data registers note the following when reading or writing to a data register of this module. (1) receive data registers the receive data registers must not be read exceed ing the valid amount of receive data, that is, the number of bytes indicated by the receive data size register. even for epdr1 which has double fifo buffers, the maximum data to be read at one time is 64 bytes. after the data is read from the current valid fifo buffer, be sure to write 1 to ep1rdfn in trg, which switches the valid buffer, updates the receive data si ze to the new number of bytes, and enables the next data to be received. (2) transmit data registers the transmit data registers must not be written to exceeding the maximum packet size. even for epdr2 which has double fifo buffers, write data within the maximum packet size at one time. after the data is written, write 1 to pkte in trg to switch the valid buffer and enable the next data to be written. data must not be con tinuously written to th e two fifo buffers. section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 933 of 1340 rej09b0499-0200 19.10.4 assigning interrupt sources to ep0 the ep0-related interrupt sources indicated by the in terrupt source bits (bits 0 to 3) in ifr0 must be assigned to the same interrupt signal with isr0. the other interrupt sources have no limitations. 19.10.5 clearing the fifo when dma transfer is enabled the endpoint 1 data register (epdr1) cannot be cleared when dma transfer for endpoint 1 is enabled (ep1 dmae in dmar = 1). cancel dma transfer before clearing the register. 19.10.6 notes on tr interrupt note the following when using the transfer request interrupt (tr inte rrupt) for in transfer to ep0i, ep2, or ep3. the tr interrupt flag is set if the fifo for the target ep has no data when the in token is sent from the usb host. however, at the timing shown in figure 19.26, multiple tr interrupts occur successively. take appropriate measures against malfunction in such a case. note: this module determines whether to return n akc if the fifo of the target ep has no data when receiving the in token, but the tr inte rrupt flag is set after a nakc handshake is sent. if the next in token is sent before pkte of trg is written to, the tr interrupt flag is set again. cpu host in token in token in token sets tr flag (sets the flag again) sets tr flag determines whether to return nack transmits data tr interrupt routine clear tr flag writes transmit data trg. pkte tr interrupt routine usb nack determines whether to return nack nack ack figure 19.26 tr int errupt flag set timing section 19 usb function module (usb) rev. 2.00 oct. 20, 2009 page 934 of 1340 rej09b0499-0200 19.10.7 restrictions on peripheral module clock (p ) operating frequency specify the peripheral module clock (p ) for the usb at 14 mhz or more. to set the usb dedicated clock (cku) at 48 mhz, specify the peripheral module clock (p ) as shown in table 19.8. operation cannot be guaranteed if any frequency other than in the following table is specified. table 19.8 selection of peripheral clock (p ) when usb is connected md_clk extal input clock frequency usb dedicated clock (cku: 48 mhz) p 0 12 mhz extal 4 extal 2 (24 mhz) extal 1 (16 mhz) 1 16 mhz extal 3 extal 2 (32 mhz) 19.10.8 notes on deep software standby mode when usb is used 1. unlike software standby mode, deep standby software mode is canceled from the reset state. for details, see section 27.8, deep software standby mode. 2. if the ramcut bit is set to 1 when the usb en ters deep software standby mode, the register states of the usb cannot be retained. when usb is used, set the ramcut bit to 1, and then, make the usb enter deep software standby mode. 3. set the usb module stop (mstpc11) bit to 0 after canceling deep software standby mode. 4. if the dusbie bit is set to 0 when the usb enters deep software standby mode, software standby mode cannot be canceled through usb resume interrupt. set the dusbie bit to 1, and then, make the usb enter deep software standby mode. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 935 of 1340 rej09b0499-0200 section 20 i 2 c bus interface 2 (iic2) this lsi has a two-channel i 2 c bus interface. the i 2 c bus interface conforms to and pr ovides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. figure 20.1 shows the block diagram of the i 2 c bus interface 2. figure 20.2 shows an example of i/o pin connections to external circuits. 20.1 features ? continuous transmission/reception since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmi ssion/reception can be performed. ? start and stop conditions generated automatically in master mode ? selection of acknowledge out put levels when receiving ? automatic loading of acknowledge bit when transmitting ? bit synchronization/wait function in master mode, the state of scl is monitored per bit, and the timing is synchronized automatically. if transmission or reception is not yet possible, drive the scl signal low until preparations are completed ? six interrupt sources transmit-data-empty (including slave-address match), tran smit-end, receive-data-full (including slave-address match), arbitration lost, nack detection, and stop condition detection ? direct bus drive two pins, the scl and sda pins function as nmos open-drain outputs. ? module stop state can be set. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 936 of 1340 rej09b0499-0200 scl iccra transfer clock generator address comparator interrupt generator interrupt request bus state decision circuit arbitration decision circuit noise canceler noise canceler output control output control transmission/ reception control circuit iccrb icmr icsr iceir icdrr icdrs icdrt i 2 c bus control register a i 2 c bus control register b i 2 c mode register i 2 c status register i 2 c interrupt enable register i 2 c transmit data register i 2 c receive data register i 2 c bus shift register slave address register [legend] iccra: iccrb: icmr: icsr: icier: icdrt: icdrr: icdrs: sar: sar sda internal data bus figure 20 .1 block diagram of i 2 c bus interface 2 section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 937 of 1340 rej09b0499-0200 vcc vcc scl in scl out scl sda in sda out sda scl (master) (slave 1) (slave 2) sda scl in scl out scl sda in sda out sda scl in scl out scl sda in sda out sda figure 20 .2 connections to the exte rnal circuit by the i/o pins 20.2 input/output pins table 20.1 shows the pin configuration of the i 2 c bus interface 2. table 20.1 pin configuration of the i 2 c bus interface 2 channel abbreviation i/o function scl0 i/o channel 0 serial clock i/o pin 0 sda0 i/o channel 0 serial data i/o pin scl1 i/o channel 1 serial clock i/o pin 1 sda1 i/o channel 1 serial data i/o pin note: the pin symbols are represented as scl an d sda; channel numbers are omitted in this manual. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 938 of 1340 rej09b0499-0200 20.3 register descriptions the i 2 c bus interface 2 has the following registers. channel 0: ? i 2 c bus control register a_0 (iccra_0) ? i 2 c bus control register b_0 (iccrb_0) ? i 2 c bus mode register_0 (icmr_0) ? i 2 c bus interrupt enable register_0 (icier_0) ? i 2 c bus status register_0 (icsr_0) ? slave address register_0 (sar_0) ? i 2 c bus transmit data register_0 (icdrt_0) ? i 2 c bus receive data register_0 (icdrr_0) ? i 2 c bus shift register_0 (icdrs_0) channel 1: ? i 2 c bus control register a_1 (iccra_1) ? i 2 c bus control register b_1 (iccrb_1) ? i 2 c bus mode register_1 (icmr_1) ? i 2 c bus interrupt enable register_1 (icier_1) ? i 2 c bus status register_1 (icsr_1) ? slave address register_1 (sar_1) ? i 2 c bus transmit data register_1 (icdrt_1) ? i 2 c bus receive data register_1 (icdrr_1) ? i 2 c bus shift register_1 (icdrs_1) section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 939 of 1340 rej09b0499-0200 20.3.1 i 2 c bus control register a (iccra) iccra enables or disables i 2 c bus interface, controls transmi ssion or reception, and selects master or slave mode, transmission or reception , and transfer clock frequ ency in master mode. bit bit name initial value r/w 7 ice 0 r/w 6 rcvd 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 cks3 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is halted 1: this bit is enabled for transfer operations (scl and sda pins are bus drive state) 6 rcvd 0 r/w reception disable this bit enables or disables the next operation when trs is 0 and icdrr is read. 0: enables next reception 1: disables next reception 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select when arbitration is lost in master mode, mst and trs are both reset by hardware, causing a transition to slave receive mode. modification of the trs bit should be made between transfer frames. operating modes are described below according to mst and trs combination. 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w transfer clock select 3 to 0 these bits are valid only in master mode. make setting according to the required transfer rate. for details on the transfer rate, see table 20.2. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 940 of 1340 rej09b0499-0200 table 20.2 transfer rate bit 3 bit 2 bit 1 bit 0 transfer rate cks3 cks2 cks1 cks0 clock p = 8 mhz p = 10 mhz p = 20 mhz p = 25 mhz p = 33 mhz p = 35 mhz 0 0 0 0 p /28 286 khz 357 khz 714 khz 893 khz 1179 khz 1250 khz 1 p /40 200 khz 250 khz 500 khz 625 khz 825 khz 875 khz 1 0 p /48 167 khz 208 khz 417 khz 521 khz 688 khz 729 khz 1 p /64 125 khz 156 khz 313 khz 391 khz 516 khz 546 khz 1 0 0 p /168 47.6 khz 59.5 khz 119 khz 149 khz 196 khz 208 khz 1 p /100 80.0 khz 100 khz 200 khz 250 khz 330 khz 350 khz 1 0 p /112 71.4 khz 89.3 khz 179 khz 223 khz 295 khz 312 khz 1 p /128 62.5 khz 78.1 khz 156 khz 195 khz 258 khz 273 khz 1 0 0 0 p /56 143 khz 179 khz 357 khz 446 khz 589 khz 625 khz 1 p /80 100 khz 125 khz 250 khz 313 khz 413 khz 437 khz 1 0 p /96 83.3 khz 104 khz 208 khz 260 khz 344 khz 364 khz 1 p /128 62.5 khz 78.1 khz 156 khz 195 khz 258 khz 273 khz 1 0 0 p /336 23.8 khz 29.8 khz 59.5 khz 74.4 khz 98.2 khz 104 khz 1 p /200 40.0 khz 50.0 khz 100 khz 125 khz 165 khz 175 khz 1 0 p /224 35.7 khz 44.6 khz 89.3 khz 112 khz 147 khz 156 khz 1 p /256 31.3 khz 39.1 khz 78.1 khz 97.7 khz 129 khz 136 khz section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 941 of 1340 rej09b0499-0200 20.3.2 i 2 c bus control register b (iccrb) iccrb issues start/stop condition, manipulates the sda pin, monitors the scl pin, and controls reset in the i 2 c control module. bit bit name initial value r/w 7 bbsy 0 r/w 6 scp 1 r/w 5 sdao 1 r 4 ? 1 r/w 3 sclo 1 r 2 ? 1 ? 1 iicrst 0 r/w 0 ? 1 ? bit bit name initial value r/w description 7 bbsy 0 r/w bus busy this bit indicates whether the i 2 c bus is occupied or released and to issue start and stop conditions in master mode. this bit is set to 1 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. this bit is cleared to 0 when the sda level changes from low to high under the condition of sda = high, assuming that the stop condition has been issued. follow this procedure also when re-transmitting a start condition. to issue a start or stop condition, use the mov instruction. 6 scp 1 r/w start/stop condition issue this bit controls the issuance of start or stop condition in master mode. to issue a start condition, write 1 to bbsy and 0 to scp. a re-transmit start condition is issued in the same way. to issue a stop condition, write 0 to bbsy and 0 to scp. this bit is always read as 1. if 1 is written, the data is not stored. 5 sdao 1 r this bit monitors the output level of sda. 0: when reading, the sda pin outputs a low level 1: when reading the sda pin outputs a high level section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 942 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 ? 1 r/w reserved the write value should always be 1. 3 sclo 1 r this bit monitors the scl output level. when reading and sclo is 1, the scl pin outputs a high level. when reading and sclo is 0, the scl pin outputs a low level. 2 ? 1 ? reserved this bit is always read as 0. 1 iicrst 0 r/w iic control module reset this bit reset the iic control module except the i2c registers. if hang-up occurs because of communication failure during i2c operation, by setting this bit to 1, the i2c control module can be reset without setting ports and initializing the registers. 0 ? 1 ? reserved this bit is always read as 1. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 943 of 1340 rej09b0499-0200 20.3.3 i 2 c bus mode register (icmr) icmr selects msb first or lsb first, controls the master mode wait and selects the number of transfer bits. bit bit name initial value r/w 7 ? 0 r/w 6 wait 0 r/w 5 ? 1 ? 4 ? 1 ? 3 bcwp 1 r/w 2 bc2 0 r/w 1 bc1 0 r/w 0 bc0 0 r/w bit bit name initial value r/w description 7 ? 0 r/w reserved the write value should always be 0. 6 wait 0 r/w wait insertion this bit selects whether to insert a wait after data transfer except for the acknowledge bit. when this bit is set to 1, after the falling of the clock for the last data bit, the low period is extended for two transfer clocks. when this bit is cleared to 0, data and the acknowledge bit are transferred consecutiv ely with no waits inserted. the setting of this bit is invalid in slave mode. 5 4 ? ? 1 1 ? ? reserved these bits are always read as 1. 3 bcwp 1 r/w bc write protect this bit controls the modification of the bc2 to bc0 bits. when modifying, this bit should be cleared to 0 and the mov instruction should be used. 0: when writing, the values of bc2 to bc0 are set 1: when reading, 1 is always read when writing, the settings of bc2 to bc0 are invalid. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 944 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. the settings of these bits should be made during intervals between transfer frames. when setting these bits to a value other than 000, the setting should be made while the scl line is low. the value return to 000 automatically at the end of a data transfer including the acknowledge bit. 000: 9 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8 20.3.4 i 2 c bus interrupt enable register (icier) icier enables or disables interrupt sources and the acknowledge bits, sets the acknowledge bits to be transferred, and confirms the acknowledge bit to be received. bit bit name initial value r/w 7 tie 0 r/w 6 teie 0 r/w 5 rie 0 r/w 4 nakie 0 r/w 3 stie 0 r/w 2 acke 0 r/w 1 ackbr 0 r 0 ackbt 0 r/w section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 945 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when the tdre bit in icsr is set to 1, this bit enables or disables the transmit data empty interrupt (txi) request. 0: transmit data empty interrupt (txi) request is disabled 1: transmit data empty interrupt (txi) request is enabled 6 teie 0 r/w transmit end interrupt enable this bit enables or disables the transmit end interrupt (tei) request at the rising of the ninth clock while the tdre bit in icsr is set to 1. the tei request can be canceled by clearing the tend bit or the teie bit to 0. 0: transmit end interrupt (tei) request is disabled 1: transmit end interrupt (tei) request is enabled 5 rie 0 r/w receive interrupt enable this bit enables or disables the receive full interrupt (rxi) request when receive data is transferred from icdrs to icdrr and the rdrf bit in icsr is set to 1. the rxi request can be canceled by clearing the rdrf or rie bit to 0. 0: receive data full interrupt (rxi) request is disabled 1: receive data full interrupt (rxi) request is enabled 4 nakie 0 r/w nack receive interrupt enable this bit enables or disables the nack receive interrupt (naki) request when the nackf and al bits in icsr are set to 1. the naki request can be canceled by clearing the nackf or al bit, or the nakie bit to 0. 0: nack receive interrupt (naki) request is disabled 1: nack receive interrupt (naki) request is enabled section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 946 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 stie 0 r/w stop condition detection interrupt enable 0: stop condition detection interrupt (stpi) request is disabled 1: stop condition detection interrupt (stpi) request is enabled 2 acke 0 r/w acknowledge bit decision select 0: the value of the acknowledge bit is ignored and continuous transfer is performed 1: if the acknowledge bit is 1, continuous transfer is suspended 1 ackbr 0 r receive acknowledge in transmit mode, this bit stores the acknowledge data that are returned by the receive device. this bit cannot be modified. 0: receive acknowledge = 0 1: receive acknowledge = 1 0 ackbt 0 r/w transmit acknowledge in receive mode, this bit spec ifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing 1: 1 is sent at the acknowledge timing section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 947 of 1340 rej09b0499-0200 20.3.5 i 2 c bus status register (icsr) icsr confirms the interrupt request flags and status. bit bit name initial value r/w 7 tdre 0 r/w 6 tend 0 r/w 5 rdrf 0 r/w 4 nackf 0 r/w 3 stop 0 r/w 2 al 0 r/w 1 aas 0 r/w 0 adz 0 r/w bit bit name initial value r/w description 7 tdre 0 r/w transmit data register empty [setting condition] ? when data is transferred from icdrt to icdrs and icdrt becomes empty ? when the trs bits are set ? when the start (re-transmit included) condition has been issued ? when switched from reception to transmission in slave mode [clearing conditions] ? when 0 is written to this bit after reading tdre = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when data is written to icdrt 6 tend 0 r/w transmit end [setting condition] ? when the ninth clock of scl rises while the tdre flag is 1 [clearing conditions] ? when 0 is written to this bit after reading tend = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when data is written to icdrt section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 948 of 1340 rej09b0499-0200 bit bit name initial value r/w description 5 rdrf 0 r/w receive data register full [setting condition] ? when receive data is transferred from icdrs to icdrr [clearing conditions] ? when 0 is written to this bit after reading rdrf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when data is read from icdrr 4 nackf 0 r/w no acknowledge detection flag [setting condition] ? when no acknowledge is detected from the receive device in transmission while the acke bit in icier is set to 1 [clearing condition] ? when 0 is written to this bit after reading nackf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 3 stop 0 r/w stop condition detection flag [setting condition] ? when a stop condition is detected after frame transfer [clearing condition] ? when 0 is written to this bit after reading stop = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 949 of 1340 rej09b0499-0200 bit bit name initial value r/w description 2 al 0 r/w arbitration lost flag this flag indicates that arbitration was lost in master mode. when two or more master devices attempt to seize the bus at nearly the same time, the i2c bus monitors sda, and if the i2c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. [setting conditions] ? when the internal sda and the sda pin level disagree at the rising of scl in master transmit mode ? when the sda pin outputs a high level in master mode while a start condition is detected [clearing condition] ? when 0 is written to this bit after reading al = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 aas 0 r/w slave addr ess recognition flag in slave receive mode, this flag is set to 1 when the first frame following a start condition matches bits sva6 to sva0 in sar. [setting conditions] ? when the slave address is detected in slave receive mode ? when the general call address is detected in slave receive mode [clearing condition] ? when 0 is written to this bit after reading aas = 1 section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 950 of 1340 rej09b0499-0200 bit bit name initial value r/w description 0 adz 0 r/w general call address recognition flag this bit is valid in slave receive mode. [setting condition] ? when the general call address is detected in slave receive mode [clearing condition] ? when 0 is written to this bit after reading adz = 1 20.3.6 slave address register (sar) sar is sets the slave address. in slave mode, if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the lsi operates as the slave device. bit bit name initial value r/w 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w 0 ? 0 r/w bit bit name initial value r/w description 7 to 1 sva6 to sva0 0 r/w slave address 6 to 0 these bits set a unique address differing from the addresses of other slave devices connected to the i 2 c bus. 0 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 951 of 1340 rej09b0499-0200 20.3.7 i 2 c bus transmit data register (icdrt) icdrt is an 8-bit readable/writable register that stores the transmit data. when icdrt detects a space in the i 2 c bus shift register, it transf ers the transmit data which has been written to icdrt to icdrs and starts transmitting data. if the next data is written to icdrt during transmitting data to icdrs, continuous transmission is possible. bit bit name initial value r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 20.3.8 i 2 c bus receive data register (icdrr) icdrr is an 8-bit read-only regist er that stores the receive data. when one byte of data has been received, icdrr transfers the r eceive data from icdrs to icdrr and the next data can be received. icdrr is a receive-only re gister; therefore, this register cannot be written to by the cpu. bit bit name initial value r/w 7 1 r 6 1 r 5 1 r 4 1 r 3 1 r 2 1 r 1 1 r 0 1 r 20.3.9 i 2 c bus shift register (icdrs) icdrs is an 8-bit write-only register that is used to transmit/receive data. in transmission, data is transferred from icdrt to icdrs and the data is sent from the sda pin. in reception, data is transferred from icdrs to icdrr af ter one by of data is received. this register cannot be read from or written to by the cpu. bit bit name initial value r/w 7 0 ? 6 0 ? 5 0 ? 4 0 ? 3 0 ? 2 0 ? 1 0 ? 0 0 ? section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 952 of 1340 rej09b0499-0200 20.4 operation 20.4.1 i 2 c bus format figure 20 .3 shows the i 2 c bus formats. figure 20 .4 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits. s sla r/ w a data a a/ a p 111 1 n 7 1 m (a) i 2 c bus format (b) i 2 c bus format (start condition retransmission) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 11 1 n1 7 1 m1 s sla r/ w a data a/ a p 11 1 n2 7 1 m2 1 1 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 20 .3 i 2 c bus formats sda scl s sla r/ w a 9 8 1-7 9 8 1-7 9 8 1-7 data a data a p figure 20 .4 i 2 c bus timing [legend] s: start condition. the master device drives sda from high to low while scl is high. sla: slave address r/ w : indicates the direction of data transfer; from the slave devi ce to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0. a: acknowledge. the receive device drives sda low. data: transferred data p: stop condition. the master device drives sda from low to high while scl is high. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 953 of 1340 rej09b0499-0200 20.4.2 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device return an acknowledge signal. figures 20 .5 and 20 .6 show the operating timings in master transmit mode. the transmission procedure and operations in master transmit mode are described below. 1. set the icr bit in the corresponding register to 1. set the ice bit in iccra to 1. set the wait bit in icmr and the cks3 to cks0 bits in iccra to 1. (initial setting) 2. read the bssy flag in iccrb to confirm that the bus is free. set the mst and trs bits in iccra to select master transmit mode. then, write 1 to bbsy and 0 to scp using the mov instruction. (the start condition is issued.) this generates the start condition. 3. after confirming that tdre in icsr has been set, write the transmit data (the first byte shows the slave address and r/w) to icdrt. after this , when tdre is automatically cleared to 0, data is transferred from icdrt to icdrs. tdre is set again. 4. when transmission of one byte data is completed while tdre is 1, tend in icsr is set to 1 at the rising of the ninth tran smit clock pulse. read the ackbr bit in icier to confirm that the slave device has been selected. then, write the second byte data to icdrt. when ackbr is 1, the slave device has not been acknowledged, so issue a stop condition. to issue the stop condition, write 0 to bbsy and scp using the mov instruction. scl is fixed to a low level until the transmit data is prepared or the stop condition is issued. 5. the transmit data after the second byte is written to icdrt every time tdre is set. 6. write the number of bytes to be transmitted to icdrt. wait until tend is set (the end of last byte data transmission) while tdre is 1, or wa it for nack (nackf in icsr is 1) from the receive device while acke in icier is 1. then , issue the stop condition to clear tend or nackf. 7. when the stop bit in icsr is set to 1, th e operation returns to th e slave receive mode. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 954 of 1340 rej09b0499-0200 sda (master output) sda (slave output) tdre tend icdrt icdrs 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 212 3456789 a r/w scl (master output) slave address address + r/w data 1 data 2 address + r/w data 1 [2] instruction of start condition issuance [3] write data to icdrt (first byte) [4] write data to icdrt (second byte) [5] write data to icdrt (third byte) user processing figure 20 .5 master transmit mo de operation timing 1 sda (master output) sda (slave output) tdre tend icdrt icdrs 1 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2345678 9 a a/a scl (master output) data n data n [7] set slave receive mode [5] write data to icdrt [6] issue stop condition. clear tend. user processing figure 20 .6 master transmit mo de operation timing 2 section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 955 of 1340 rej09b0499-0200 20.4.3 master receive operation in master receive mode, the master device outputs th e receive clock, receives data from the slave device, and returns an acknowledge signal. figures 20 .7 and 20 .8 show the operation timings in master receive mode. the receptio n procedure and operations in master receive mode are shown below. 1. clear the tend bit in icsr to 0, then clear the trs bit in iccra to 0 to switch from master transmit mode to master receive mode . then, clear the tdre bit to 0. 2. when icddr is read (dummy r ead), reception is started, the receive clock pulse is output, and data is received, in synchronization with the in ternal clock. the master mode outputs the level specified by the ackbt in icier to sd a, at the ninth receive clock pulse. 3. after the reception of the first frame data is completed, the rdrf bit in icsr is set to 1 at the rising of the ninth receive cloc k pulse. at this time, the received data is read by reading icdrr. at the same time, rdrf is cleared. 4. the continuous reception is performed by reading icdrr and clearing rdrf to 0 every time rdrf is set. if the eighth receive clock pulse falls after reading icdrr by other processing while rdrf is 1, scl is fixed to a low level until icdrr is read. 5. if the next frame is the last receive data, set the rcvd bit in iccra before reading icdrr. this enables the issuance of the stop condition after the next reception. 6. when the rdrf bit is set to 1 at the rising of the ninth receive clock pulse, the stop condition is issued. 7. when the stop bit in icsr is set to 1, read icdrr and clear rcvd to 0. 8. the operation returns to the slave receive mode. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 956 of 1340 rej09b0499-0200 sda (master output) sda (slave output) tdre tend icdrs icdrr 1 bit 7 a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 21 3456789 9 a scl (master output) master transmit mode master receive mode data 1 trs rdrf data 1 user processing [3] read icdrr [1] clear tend and trs, then tdre [2] read icdrr (dummy read) figure 20 .7 master receive mo de operation timing 1 section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 957 of 1340 rej09b0499-0200 sda (master output) sda (slave output) rdrf rcvd icdrs icdrr 1 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2345678 9 a a/ a scl (master output) data n-1 data n data n-1 data n user processing [8] set slave receive mode [5] set rcvd then read icdrr [6] issue stop condition [7] read icdrr and clear rcvd figure 20 .8 master receive mo de operation timing 2 20.4.4 slave transmit operation in slave transmit mode, the slave device outputs the transmit data, and the master device outputs the receive clock pulse and return s an acknowledge signal. figures 20 .9 and 20 .10 show the operation timings in slave transmit mode. the tr ansmission procedure and operations in slave transmit mode are described below. 1. set the icr bit in the corresponding register to 1, then set the ice bit in iccra to 1. set the wait in icmr and cks3 to cks0 in iccra (initial setting). set the mst and trs bits in iccra to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the firs t frame following the detection of the start condition, the slave device outputs the level specified by ackbt in icier to sda, at the rising of the ninth clock pulse. at this time, if the eighth bit data (r/ w ) is 1, trs in iccra and tdre in icsr are set to 1, and the mode changes to slave transmit mode automatically. the continuous transmission is performed by writing the transmit data to icdrt every time tdre is set. 3. if tdre is set after writing the last transmit data to icdrt, wait until tend in icsr is set to 1, with tdre = 1. when tend is set, clear tend. 4. clear trs for end proce ssing, and read icdrr (dummy read) to release scl. 5. clear tdre. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 958 of 1340 rej09b0499-0200 sda (master output) sda (slave output) tdre tend icdrs icdrr 1 bit 7 a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 21 3456789 9 a scl (master output) slave receive mode slave transmit mode data 1 data 2 data 3 data 2 data 1 scl (slave output) trs icdrt user processing [2] write data (data 3) to icdrt [2] write data (data 1) to icdrt [2] write data (data 2) to icdrt figure 20 .9 slave transmit mode operation timing 1 section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 959 of 1340 rej09b0499-0200 sda (master output) sda (slave output) tdre tend icdrs icdrr 1 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2345678 9 scl (master output) trs icdrt scl (slave output) a a/ a data n slave transmit mode slave receive mode user processing [3] clear tend [5] clear tdre [4] clear trs and read icdrr (dummy read) figure 20 .10 slave transmit mode operation timing 2 section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 960 of 1340 rej09b0499-0200 20.4.5 slave receive operation in slave receive mode, the master device outputs th e transmit clock and the transmit data, and the slave device returns an acknowledge signal. figures 20 .11 and 20 .12 show the operation timings in slave receive mode. the receptio n procedure and operations in sl ave receive mode are described below. 1. set the icr bit in the corresponding register to 1. then, set the ice bit in iccra to 1. set the wait bit in icmr or cks3 to cks0 in iccra (initial setting). set the mst and trs bits in iccra to select slave receive mode an d wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave address outputs the level specified by ackbt in icier to sda, at the rising of the ninth clock pulse. at the same time, rdrf in icsr is set to read icdrr (dummy read). (since the read data show s the slave address and r/ w , it is not used). 3. read icdrr every time rdrf is set. if the eighth clock pulse falls while rdrf is 1, scl is fixed to a low level until icdrr is read. the change of the acknowledge (ackbt) setting before reading icdrr to be returned to the ma ster device is reflected in the next transmit frame. 4. the last byte data is read by reading icdrr. sda (master output) scl (slave output) sda (slave output) icdrs icdrr 12 1 345678 9 9 a a scl (master output) data 2 data 1 rdrf data 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 user processing [2] read icdrr (dummy read) [2] read icdrr figure 20 .11 slave receive mode operation timing 1 section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 961 of 1340 rej09b0499-0200 icdrs icdrr a a rdrf sda (master output) scl (slave output) sda (slave output) 12345678 9 scl (master output) data 2 data 1 data 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 9 user processing [3] set ackbt [3] read icdrr [4] read icdrr figure 20 .12 slave receive mode operation timing 2 20.4.6 noise canceler the logic levels at the scl and sda pins are routed through the noise cancelers before being latched internally. figure 20 .13 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded latche s and a match detector. the signal input to scl (or sda) is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. c q d c q d sampling clock sampling clock scl input or sda input latch system clock period latch compare match detection circuit internal scl or internal sda sampling clock figure 20 .13 block diagram of noise canceler section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 962 of 1340 rej09b0499-0200 20.4.7 example of use sample flowcharts in resp ective modes that use the i 2 c bus interface are shown in figures 20 .14 to 20 .17. no no yes yes no yes no no no no yes yes yes yes yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] start [1] detect the state of the scl and sda lines [2] set to master transmit mode [3] issue the start condition [4] set the transmit data for the first byte (slave address + r/w) [5] wait for 1 byte of data to be transmitted [6] detect the acknowledge bit, transferred from the specified slave device [7] set the transmit data for the second and subsequent data (except for the last byte) [8] wait for icdrt empty [9] set the last byte of transmit data [10] wait for the completion of transmission of the last byte [11] clear the tend flag [12] clear the stop flag [13] issue the stop condition [14] wait for the creation of the stop condition [15] set to slave receive mode. clear tdre. initial settings read bbsy in iccrb set mst = 1 and trs = 1 in iccra bbsy = 0? write bbsy = 1 and scp = 0 write the transmit data in icdrt read tend in iscr tend = 1? read ackbr in icier ackbr = 0? transmit mode? read tdre in icsr tdre = 1? last byte? write the transmit data to icdrt read tend in icsr tend = 1? clear tend in icsr clear stop in icsr write bbsy = 0 and scp = 0 read stop in icsr stop = 1? set mst = 0 and trs = 0 in iccra clear trde in icsr end master receive mode write the transmit data to icdrt figure 20 .14 sample flowchart of master transmit mode section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 963 of 1340 rej09b0499-0200 no yes rdrf = 1? no yes rdrf = 1? no yes stop = 1? no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] master receive mode [1] clear tend, set to master receive mode, then clear tdre * 1 * 2 [2] set acknowledge to the transmitting device * 1 * 2 [3] dummy read icdrr * 1 * 2 [4] wait for 1 byte of data to be received * 2 [5] check if (last receive -1) * 2 [6] read the receive data * 2 [7] set acknowledge of the last byte. disable continuous reception (rcvd = 1). * 2 [8] read receive data of (last byte -1). * 2 [9] wait for the last byte to be received [10] clear the stop flag [11] issue the stop condition [12] wait for the creation of stop condition [13] read the receive data of the last byte [14] clear rcvd to 0 [15] set to slave receive mode clear tend in icsr set trs = 0 (iccra) clear tdre in icsr set ackbt = 0 (icier) dummy read icdrr dummy read icsr last receive -1? read icdrr set ackbt = 1 (icier) set rcvd = 1 (iccra) read icdrr read rdrf in icsr clear stop in icsr write bbsy = 0 and scp = 0 read stop in icsr read icdrr set rcvd = 0 (iccra) set mst = 0 (iccra) end note: 1. do not generate an interrupt during steps [1] to [3]. 2. for one-byte reception, steps [2] to [6] do not need to be executed. after step [1], execute step [7]. in step [8], read icdrr (dummy read). figure 20 .15 sample flowchart for master receive mode section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 964 of 1340 rej09b0499-0200 tdre = 1? yes yes no no no [1] [4] [5] [6] [7] [8] [9] [2] [3] yes tend = 1? [1] clear the aas flag. [2] set the transmit data for icdrt (except the last byte). [3] wait for icdrt empty. [4] set the last byte of transmit data. [5] wait for the last byte of data to be transmitted. [6] clear the tend flag. [7] set to slave receive mode. [8] dummy read icdrr to free the scl line. [9] clear the tdre flag. slave transmit mode clear aas in icsr write the transmit data to icdrt read trd in icsr last byte? write the transmit data to icdrt read tend in icsr clear tend in icsr set trs = 0 (iccra) dummy read icdrr clear tdre in icsr end figure 20 .16 sample flowchart for slave transmit mode section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 965 of 1340 rej09b0499-0200 no yes rdrf = 1? no yes rdrf = 1? no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] clear the aas flag. * [2] set the acknowledge for the transmit device. * [3] dummy read icdrr * [4] wait for 1 byte of data to be received * [5] detect (last reception -1) * [6] read the receive data. * [7] set the acknowledge for the last byte. * [8] read the receive data of (last byte -1). * [9] wait for the reception of the last byte to be completed. [10] read the last byte of receive data. slave receive mode clear aas in icsr set ackbt = 0 in icier dummy read icdrr read rdrf in icsr the last reception -1? read icdrr set ackbt = 1 in icier read icdrr read rdrf in icsr read icdrr end note: * for one-byte reception, steps [2] to [6] do not need to be executed. after step [1], execute step [7]. in step [8], read icdrr (dummy read). figure 20 .17 sample flowchart for slave receive mode section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 966 of 1340 rej09b0499-0200 20.5 interrupt request there are six interrupt requ ests in this module; transmit data em pty, transmit end, receive data full, nack detection, stop recognition, and arbitratio n lost. table 20.3 shows the contents of each interrupt request. table 20.3 interrupt requests interrupt request abbreviat ion interrupt condition transmit data empty txi (tdre = 1) ? (tie = 1) transmit end tei (tend = 1) ? (teie = 1) receive data full rxi (rdrf = 1) ? (rie = 1) stop recognition stpi (stop = 1) ? (stie = 1) nack detection arbitration lost naki {(nackf = 1) + (al = 1)} ? (nakie = 1) when one of the interrupt conditions in table 20.3 is 1 and the i bit in ccr is 0, the cpu executes interrupt exception handling. clear the interrupt sources during interrupt exception handling. note that the tdre and tend bits are automatically cleared to 0 by writing data to icdrt, and the rdrf bit is cleared to 0 by read ing icdrr. in particular, the tdre bit can be set again at the same time as data are for transmission written to icdrt, and 1 extra byte can be transmitted if the tdre is again cleared to 0. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 967 of 1340 rej09b0499-0200 20.6 bit synchronous circuit this module has a possibility that the high-level period is shortened in the two states described below. in master mode, ? when scl is driven low by the slave device ? when the rising speed of scl is lowered by the load on the scl line (load capacitance or pull-up resistance) therefore, this module monitors scl and communicates bit by bit in synchronization. figure 20 .18 shows the timing of the bit synchronous circuit, and table 20.4 shows the time when scl output changes from low to hi-z and the period which scl is monitored. scl monitor timing reference clock internal scl scl v ih figure 20 .18 timing of the bit synchronous circuit table 20.4 time for monitoring scl cks3 cks2 time for monitoring scl 0 7.5 tcyc 0 1 19.5 tcyc 0 17.5 tcyc 1 1 41.5 tcyc section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 968 of 1340 rej09b0499-0200 20.7 usage notes 1. confirm the ninth falling edge of the clock before issuing a stop or a repeated start condition. the ninth falling edge can be confirmed by monitoring the sclo bit in the i 2 c bus control register b (iccrb). if a stop or a repeated start condi tion is issued at certain timing in either of the following cases, the stop or repeated start cond ition may be issued incorrectly. ? the rising time of the scl signal exceeds the time given in section 20.6, bit synchronous circuit, because of the load on the scl bu s (load capacitance or pull-up resistance). ? the bit synchronous circuit is activated b ecause a slave device holds the scl bus low during the eighth clock. 2. the wait bit in the i 2 c bus mode register (icmr) must be held 0. if the wait bit is set to 1, when a slave de vice holds the scl signal low more than one transfer clock cycle during the eighth clock, the high level period of the ninth clock may be shorter than a given period. 3. restriction in transfer rate setting value in multi-master mode when the transfer rate of i 2 c transfer of this lsi is slower than that of other master, the scl signal the width of which is unexpected may be output. to avoid this phenomenon, set a transfer rate of 1/1.8 or more of the fastest rate of other master to the transfer rate of i 2 c transfer rate. for example, if the fastest rate of other masters is 400 kbps, the i 2 c transfer rate of this lsi should be 223 kbps (= 400/1.8) or more. 4. restriction in bit manipulation when the mst and trs bits are set in multi-master mode when the mst and trs bits are set to mast er slave mode by manipulating these bits sequentially, the conflict state occu rs as follows according to the timing that arbitration is lost; the al bit in icsr is set to 0, and set to master mode (mst = 1, trs = 1). there are the following methods to avoid this phenomenon. ? in multi-master mode, set the mst and trs bits by mov instruction. ? when arbitration is lost, confirm that the mst and trs bits are set to 0. if these bits are set to other than 0, set these bits to 0. 5. notes on master receive mode in master receive mode, the rdrf bit is set to 0 at the eighth rising clock, the scl signal is pulled to ?low? state. when icd rr is read near at the eighth falling clock, the scl signal level is released and the ninth clock is outputted by fixing the eighth cloc k of receive data to ?low? state. reading icdrr is not required. as a result, the failure to receive data occurs. there are the following methods to avoid this phenomenon. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 969 of 1340 rej09b0499-0200 ? in master receive mode, read ic drr by the eighth rising clock. ? in master receive mode, set the rcvd bit to 1 and process the bit by the communication of every one byte. 6. setting of the module stop function operation of the iic2 can be disabled or enabled using the module stop control register. the initial setting is for operation of the iic2 to be halted. register access is enabled by clearing module stop state. for details, s ee section 27, power-down modes. section 20 i 2 c bus interface 2 (iic2) rev. 2.00 oct. 20, 2009 page 970 of 1340 rej09b0499-0200 section 21 a/d converter rev. 2.00 oct. 20, 2009 page 971 of 1340 rej09b0499-0200 section 21 a/d converter this lsi includes two units (units 0 and 1) of successive approximation type 10-bit a/d converter. the a/d converter unit 0 allows up to ei ght analog input channels to be selected while the a/d converter unit 1 allows up to four analog input channels to be selected. figures 21.1 and 21.2 show block diagrams of the a/d converter units 0 and 1, respectively. 21.1 features ? 10-bit resolution ? eight or four input channels (total eight input channels for the two units) four channels x two units (for unit 0 and unit 1) eight channels x one unit (for unit 0) ? conversion time: 2.7 s per channel (in peripheral clock mode) 1.0 s per channel (in system clock mode* 3 ) ? two kinds of operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels, or 1 to 8 channels* 1 ? eight data registers for the a/d converter unit 0 and four data registers for unit 1 (total eight data registers for the two units) results of a/d conversion are held in a 16-bit data register for each channel. ? sample and hold functionality ? three types of conversion start conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (tpu)* 1 or 8-bit timer (tmr)* 2 , or an external trigger signal. ? function of starting units simultaneously a/d conversion for multiple units can be started by external trigger ( adtrg0 ). ? interrupt source a/d conversion end interrupt (adi) request can be generated. ? module stop state specifiable notes: 1. only supported in the a/d converter unit 0. 2. for unit 0, a/d conversion can be started by a conversion start trigger by the tmr units 0 and 1 whereas for unit 1 a/d conversion can be started by a conversion start trigger by the tmr units 2 and 3. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 972 of 1340 rej09b0499-0200 3. the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a- usb) is usable. adcsr_0 adcr_0 adsstr_0 admosel_0 adtrg0 + avcc vref avss an0 addra_0 addrb_0 addrc_0 addrd_0 addre_0 addrf_0 addrg_0 addrh_0 an1 an2 an3 an4 an5 an6 an7 10-bit d/a successive approximation register module data bus internal data bus bus interface sample-and- hold circuit multiplexer control circuit comparator adi0 interrupt signal synchronization circuit conversion start trigger from the tpu or tmr (units 0, 1) [legend] adcr_0: a/d control register_0 adcsr_0: a/d control/status register_0 adsstr_0: a/d sampling state register_0 admosel_0: a/d mode selection register_0 addra_0: a/d data register a_0 addrb_0: a/d data register b_0 addrc_0: a/d data register c_0 addrd_0: a/d data register d_0 addre_0: a/d data register e_0 addrf_0: a/d data register f_0 addrg_0: a/d data register g_0 addrh_0: a/d data register h_0 figure 21.1 block diagram of a/d converter unit 0 (ad_0) section 21 a/d converter rev. 2.00 oct. 20, 2009 page 973 of 1340 rej09b0499-0200 addra_1 addrb_1 addrc_1 addrd_1 addre_1 addrf_1 addrg_1 addrh_1 adcsr_1 adcr_1 adsstr_1 admosel_1 adtrg1 adtrg0 + avcc vref avss an4 an5 an6 an7 10-bit d/a successive approximation register module data bus internal data bus sample-and- hold circuit multiplexer control circuit comparator synchronization circuit adi1 interrupt signal conversion start trigger from the tmr (units 2, 3) [legend] adcr_1: a/d control register_1 adcsr_1: a/d control/status register_1 adsstr_1: a/d sampling state register_1 admosel_1: a/d mode selection register_1 addra_1: a/d data register a_1 addrb_1: a/d data register b_1 addrc_1: a/d data register c_1 addrd_1: a/d data register d_1 addre_1: a/d data register e_1 addrf_1: a/d data register f_1 addrg_1: a/d data register g_1 addrh_1: a/d data register h_1 bus interface figure 21.2 block diagram of a/d converter unit 1 (ad_1) section 21 a/d converter rev. 2.00 oct. 20, 2009 page 974 of 1340 rej09b0499-0200 21.2 input/output pins table 21.1 shows the pin configuration of the a/d converter. table 21.1 pin configuration unit abbr. pin name symbol i/o function analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input analog inputs 0 ad_0 a/d external trigger input pin 0 adtrg0 input external trigger input for starting a/d conversion * analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input analog inputs a/d external trigger input pin 0 adtrg0 input external trigger input pin for starting a/d conversion * 1 ad_1 a/d external trigger input pin 1 adtrg1 input external trigger input pin for starting a/d conversion * analog power supply pin av cc input analog block power supply analog ground pin av ss input analog block ground common reference voltage pin vref input a/d conversion reference voltage note: * selectable by setting of the trgs1, trgs0, and extrgs bits in adcr. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 975 of 1340 rej09b0499-0200 21.3 register descriptions the a/d converter has the following registers. unit 0 (a/d_0) registers: ? a/d data register a_0 (addra_0) ? a/d data register b_0 (addrb_0) ? a/d data register c_0 (addrc_0) ? a/d data register d_0 (addrd_0) ? a/d data register e_0 (addre_0) ? a/d data register f_0 (addrf_0) ? a/d data register g_0 (addrg_0) ? a/d data register h_0 (addrh_0) ? a/d control/status register_0 (adcsr_0) ? a/d control register_0 (adcr_0) ? a/d mode selection register_0 (admosel_0) ? a/d sampling state regi ster_0 (adsstr_0) unit 1 (a/d_1) registers: ? a/d data register a_1 (addra_1) ? a/d data register b_1 (addrb_1) ? a/d data register c_1 (addrc_1) ? a/d data register d_1 (addrd_1) ? a/d data register e_1 (addre_1) ? a/d data register f_1 (addrf_1) ? a/d data register g_1 (addrg_1) ? a/d data register h_1 (addrh_1) ? a/d control/status register_1 (adcsr_1) ? a/d control register_1 (adcr_1) ? a/d mode selection register_1 (admosel_1) ? a/d sampling state regi ster_1 (adsstr_1) section 21 a/d converter rev. 2.00 oct. 20, 2009 page 976 of 1340 rej09b0499-0200 21.3.1 a/d data registers a to h (addra to addrh) there are eight 16-bit read-only addr registers, addra to addrh, used to store the results of a/d conversion. the addr registers, which store a conversion result for each channel, are shown in table 21.2. the converted 10-bit data is stored in bits 15 to 6. the lower 6-bit data is always read as 0. the data bus between the cpu an d the a/d converter has a 16-bit width. the data can be read directly from the cpu. addr must not be accessed in 8-bit units and must be accessed in 16-bit units. 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w table 21.2 analog input channels and corresponding addr registers a/d data register storing conversion result analog input channel unit 0 unit 1 * 2 an0 addra_0 (unit 0) ? an1 addrb_0 (unit 0) ? an2 addrc_0 (unit 0) ? an3 addrd_0 (unit 0) ? an4 addre_0 (unit 0) * 1 addre_1 (unit 1) * 1 an5 addrf_0 (unit 0) * 1 addrf_1 (unit 1) * 1 an6 addrg_0 (unit 0) * 1 addrg_1 (unit 1) * 1 an7 addrh_0 (unit 0) * 1 addrh_1 (unit 1) * 1 notes: 1. a/d conversion should not be perfo rmed on the same channel by multiple units. 2. the addra_1 to addrd_1 registers for unit 1 are not used. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 977 of 1340 rej09b0499-0200 21.3.2 a/d control/status register_0 (adcsr_0) for unit 0 adcsr controls a/d conversion operations. 7 adf 0 r/(w) * 1 6 adie 0 r/w 5 adst 0 r/w 4 excks 0 r/w * 2 3 ch3 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 adf 0 r/(w) * 1 a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? completion of a/d conversion in single mode ? completion of a/d conversion on all specified channels in scan mode [clearing conditions] ? writing of 0 after reading adf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? reading from addr after activation of the dmac or dtc by an adi interrupt 6 adie 0 r/w a/d interrupt enable setting this bit to 1 enables adi interrupts by adf. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 978 of 1340 rej09b0499-0200 bit bit name initial value r/w description 5 adst 0 r/w a/d start clearing this bit to 0 stops a/d conversion, and the a/d converter enters wait state. setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when a/d conversion on the specified channel ends. in scan mode, a/d conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. in addition, when the adstclr bit in adcr is 1, t he adst bit is automatically cleared to 0 upon completion of a/d conversion for all of the selected channels to stop a/d conversion. the adst bit is automatically cleared at a different time from that of setting the ad f bit. the adst bit is cleared before setting the adf bit. 4 excks * 2 0 r/w extended clock selection sets the a/d conversion time in accord with bits cks1 and cks0 in adcr and the icksel bit in admosel. for details, see section 21.3.4, a/d control register_0 (adcr_0) for unit 0. write to the excks bit at the same time as bits cks1 and cks0 in adcr. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 979 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 3 to 0 selects analog input together with bits scane and scans in adcr. ? when scane = 0 and scans = x 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1xxx: setting prohibited ? when scane = 1 and scans = 0 0000: an0 0001: an0 and an1 0010: an0 to an2 0011: an0 to an3 0100: an4 0101: an4 and an5 0110: an4 to an6 0111: an4 to an7 1xxx: setting prohibited ? when scane = 1 and scans = 1 0000: an0 0001: an0 and an1 0010: an0 to an2 0011: an0 to an3 0100: an0 to an4 0101: an0 to an5 0110: an0 to an6 0111: an0 to an7 1xxx: setting prohibited [legend] x: don't care notes: 1. only 0 can be written to this bit, to clear the flag. 2. the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a- usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 980 of 1340 rej09b0499-0200 21.3.3 a/d control/status register 1 (adcsr_1) for unit 1 adcsr controls a/d conversion operations. 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 excks 0 r/w 3 ch3 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. bit bit name initial value r/w description 7 adf 0 r/(w) * a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? completion of a/d conversion in single mode ? completion of a/d conversion on all specified channels in scan mode [clearing conditions] ? writing of 0 after reading adf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? reading from addr after activation of the dmac or dtc by an adi interrupt 6 adie 0 r/w a/d interrupt enable setting this bit to 1 enables adi interrupts by adf. 5 adst 0 r/w a/d start clearing this bit to 0 stops a/d conversion, and the a/d converter enters wait state. setting this bit to 1 starts a/d c onversion. in single mode, this bit is cleared to 0 automatica lly when a/d conversion on the specified channel ends. in scan mode, a/d conversion continues sequentially on the specified channel s until this bit is cleared to 0 by software, a reset, or hardware standby mode. in addition, when the adstclr bit in adcr is 1, the adst bit is automatically cleared to 0 upon completion of a/d conversion for all of the selected channels to stop a/d conversion. the adst bit is automatically cl eared at a different time from that of setting the adf bit. t he adst bit is cleared before setting the adf bit. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 981 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 excks 0 r/w extended clock selection sets the a/d conversion time in accord with bits cks1 and cks0 in adcr and the icksel bit in admosel. for details, see section 21.3.5, a/d control re gister_1 (adcr_1) for unit 1. write to the excks bit at the same time as bits cks1 and cks0 in adcr. 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 3 to 0 selects analog input together with bits scane and scans in adcr. ? when scane = 0 and scans = x 00xx: setting prohibited 0100: an4 0101: an5 0110: an6 0111: an7 1xxx: setting prohibited ? when scane = 1 and scans = 0 00xx: setting prohibited 0100: an4 0101: an4 and an5 0110: an4 to an6 0111: an4 to an7 1xxx: setting prohibited ? when scane = 1 and scans = 1 xxxx: setting prohibited [legend] x: don't care note: * only 0 can be written to this bit, to clear the flag. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 982 of 1340 rej09b0499-0200 21.3.4 a/d control register_0 (adcr_0) for unit 0 adcr enables a/d conversion to be star ted by an external trigger input. 7 trgs1 0 r/w 6 trgs0 0 r/w 5 scane 0 r/w 4 scans 0 r/w 3 cks1 0 r/w 2 cks0 0 r/w 1 adstclr 0 r/w 0 extrgs 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 0 trgs1 trgs0 extrgs 0 0 0 r/w r/w r/w timer trigger select 1 and 0, extended trigger select these bits select enabling or di sabling of the start of a/d conversion by a trigger signal. 000: disables starting of a/d c onversion by external trigger 010: a/d conversion is started by conversion trigger from tpu (unit 0) 100: a/d conversion is started by conversion trigger from tmr (units 0 and 1) 110: a/d conversion is started by the adtrg0 signal * 1 001: external trigger is invalid 011: setting prohibited 101: setting prohibited 111: a/d conversion is started by the adtrg0 signal * 1 (starts units simultaneously) 5 4 scane scans 0 0 r/w r/w scan mode these bits select the a/ d conversion operating mode. 0x: single mode 10: scan mode. a/d conversion is performed continuously for channels 1 to 4. 11: scan mode. a/d conversion is performed continuously for channels 1 to 8. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 983 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 2 cks1 cks0 0 0 r/w r/w clock select 1 and 0 in conjunction with the excks * 2 bit in adcsr and the icksel * 3 bit in admosel, these bits set the a/d conversion time. make settings for the a/d conversi on time while the adst bit in adcsr is 0, and then set th e mode of a/d conversion. furthermore, for transitions to software standby mode and module-stop mode, set these bits to b'11 beforehand. excks * 2 , icksel * 3 , cks1, cks0 0000: a/d conversion time = 528 states * 4 (max.) 0001: a/d conversion time = 268 states * 4 (max.) 0010: a/d conversion time = 138 states * 4 (max.) 0011: a/d conversion time = 73 states * 4 (max.) 01xx: prohibited setting 1000: a/d conversion time = 336 states * 4 (max.) 1001: a/d conversion time = 172 states * 4 (max.) 1010: a/d conversion time = 90 states * 4 (max.) 1011: a/d conversion time = 49 states * 4 (max.) 11xx: a/d conversion time = 34 states * 4 * 5 (max.) this setting applies when p = i /2 * 6 . 1 adstclr * 2 0 r/w a/d start clear enables or disables automatic cl earing of the adst bit in scan mode. 0: the adst bit is not automatic ally cleared to 0 in scan mode. 1: the adst bit is cleared to 0 upon completion of a/d conversion for all of the selected channels in scan mode. [legend] x: don't care notes: 1. to set a/d conversion to start by the adtrg pin, the ddr bit and icr bit for the corresponding pin should be set to 0 and 1, re spectively. for details, see section 13, i/o ports. 2. the full-spec emulator (e6000h) should no t be used, but the on-chip emulator (e10a- usb) is usable. 3. icksel = 1: the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a-usb) is usable. 4. cycles of p 5. set the number of "states" (clock cycles ) for sampling to 25 (adsstr_0 = d'25). 6. when p = i , i /4, or i /8, settings of the form 11xx are prohibited. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 984 of 1340 rej09b0499-0200 21.3.5 a/d control register_1 (adcr_1) for unit 1 adcr enables a/d conversion to be started by an external trigger input. 7 trgs1 0 r/w 6 trgs0 0 r/w 5 scane 0 r/w 4 scans 0 r/w 3 cks1 0 r/w 2 cks0 0 r/w 1 adstclr 0 r/w 0 extrgs 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 0 trgs1 trgs0 extrgs 0 0 0 r/w r/w r/w timer trigger select 1 and 0, extended trigger select these bits select enabling or di sabling of the start of a/d conversion by a trigger signal. 000: disables starting of a/d c onversion by external trigger 010: setting prohibited 100: setting prohibited 110: a/d conversion is started by the adtrg1 signal * 1 001: setting prohibited 011: external trigger is invalid 101: a/d conversion is started by conversion trigger from tmr (units 2 and 3) 111: a/d conversion is started by the adtrg0 signal * 1 (starts units simultaneously) 5 4 scane scans 0 0 r/w r/w scan mode these bits select the a/ d conversion operating mode. 0x: single mode 10: scan mode. a/d conversion is performed continuously for channels 1 to 4. 11: setting prohibited section 21 a/d converter rev. 2.00 oct. 20, 2009 page 985 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 2 cks1 cks0 0 0 r/w r/w clock select 1 and 0 in conjunction with the excks bit in adcsr and the icksel * 2 bit in admosel, these bits set the a/d conversion time. make settings for the a/d conversion time while the adst bit in adcsr is 0, and then set t he mode of a/d conversion. furthermore, for transitions to software standby mode and module-stop mode, set these bits to b'11 beforehand. excks, icksel * 2 , cks1, cks0 0000: a/d conversion time = 528 states * 3 (max.) 0001: a/d conversion time = 268 states * 3 (max.) 0010: a/d conversion time = 138 states * 3 (max.) 0011: a/d conversion time = 73 states * 3 (max.) 01xx: prohibited setting 1000: a/d conversion time = 336 states * 3 (max.) 1001: a/d conversion time = 172 states * 3 (max.) 1010: a/d conversion time = 90 states * 3 (max.) 1011: a/d conversion time = 49 states * 3 (max.) 11xx: a/d conversion time = 34 states * 3 * 4 (max.) this setting applies when p = i /2 * 5 . 1 adstclr 0 r/w a/d start clear enables or disables automatic clearing of the adst bit in scan mode. 0: the adst bit is not automatically cleared to 0 in scan mode. 1: the adst bit is cleared to 0 upon completion of a/d conversion for all of the selected channels in scan mode. [legend] x: don't care notes: 1. to set a/d conversion to start by the adtrg pin, the ddr bit and icr bit for the corresponding pin should be set to 0 and 1, re spectively. for details, see section 13, i/o ports. 2. icksel = 1: access to the full-spec emulator (e6000h) is prohibited but the on-chip emulator (e10a-usb) is usable. 3. cycles of p 4. set the number of "states" (clock cycles ) for sampling to 25 (adsstr_1 = d'25). 5. when pf = if, if/4, or if/8, settings of the form 11xx are prohibited. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 986 of 1340 rej09b0499-0200 21.3.6 a/d mode selection register_0 (admosel_0 * 1 ) for unit 0 admosel* 1 is used to select the system clock mode. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 icksel 0 r/w 0 ? 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 4 3 2 ? ? ? ? ? ? 0 0 0 0 0 0 r r r r r r reserved these bits are always read as 0. the write value should always be 0. 1 icksel * 1 0 r/w system clock mode selection this bit is used to select the system clock mode. 0: peripheral clock mode 1: system clock mode * 2 for details, see section 21.4.5, setting the system clock mode. 0 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. notes: 1. the full-spec emulator (e6000h) shou ld not be used, but the on-chip emulator (e10a- usb) is usable. 2. in system clock mode, operate all units with the system clock. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 987 of 1340 rej09b0499-0200 21.3.7 a/d mode selection register_1 (admosel_1 * 1 ) for unit 1 admosel* 1 is used to select the system clock mode. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 icksel 0 r/w 0 ? 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 4 3 2 ? ? ? ? ? ? 0 0 0 0 0 0 r r r r r r reserved these bits are always read as 0. the write value should always be 0. 1 icksel * 1 0 r/w system clock mode selection this bit is used to select the system clock mode. 0: peripheral clock mode 1: system clock mode * 2 for details, see section 21.4.5, setting the system clock mode. 0 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. notes: 1. access to the full-spec emulator (e 6000h) is prohibited, but the on-chip emulator (e10a-usb) is usable. 2. in system clock mode, operate all units with the system clock. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 988 of 1340 rej09b0499-0200 21.3.8 a/d sampling state register_0 (adsstr_0 * ) for unit 0 adsstr* is used to set the sampling period for the analog input as a nu mber of states (clock cycles). 7 smp7 0 r/w 6 smp6 0 r/w 5 smp5 0 r/w 4 smp4 0 r/w 3 smp3 1 r/w 2 smp2 1 r/w 1 smp1 1 r/w 0 smp0 1 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 4 3 2 1 0 smp7 smp6 smp5 smp4 smp3 smp2 smp1 smp0 0 0 0 0 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w ? when excks = 0 set these bits to h'0f. ? when excks = 1 if icksel = 0, set these bits to h'0f. if icksel = 1 * , set these bits to h'19. note: * the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a- usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 989 of 1340 rej09b0499-0200 21.3.9 a/d sampling state register_1 (adsstr_1 * ) for unit 1 adsstr* is used to set the sampling period for th e analog input as a numb er of states (clock cycles). 7 smp7 0 r/w 6 smp6 0 r/w 5 smp5 0 r/w 4 smp4 0 r/w 3 smp3 1 r/w 2 smp2 1 r/w 1 smp1 1 r/w 0 smp0 1 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 4 3 2 1 0 smp7 smp6 smp5 smp4 smp3 smp2 smp1 smp0 0 0 0 0 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w ? when excks = 0 set these bits to h'0f. ? when excks = 1 if icksel = 0, set these bits to h'0f. if icksel = 1 * , set these bits to h'19. note: * access to the full-spec emulator (e6000h) is prohibited but the on-chip emulator (e10a- usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 990 of 1340 rej09b0499-0200 21.4 operation the a/d converter has two operating modes: single mode and scan mode. first select the clock for a/d conversion (adclk). when changing the operating mode or analog input channel, to prevent incorrect operation, first clear the adst bit in adcsr to 0. the adst bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 21.4.1 single mode in single mode, a/d conversion is to be performed only once on the analog input of the specified single channel. 1. a/d conversion for the selected channel is started when the adst bit in adcsr is set to 1 by software, tpu* 1 , tmr* 2 , or an external trigger input. 2. when a/d conversion is completed, the a/d conversion result is transferred to the corresponding a/d data register of the channel. 3. when a/d conversion is completed, the adf b it in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi in terrupt request is generated. 4. the adst bit remains at 1 during a/d conver sion, and is automatically cleared to 0 when a/d conversion ends. the a/d converter enters wait state. if the adst bit is cleared to 0 during a/d conversion, a/d conversion stops and the a/d converter enters a wait state. notes: 1. only possible in unit 0. 2. as conversion start trigger, units 0 and 1 of tmr, and units 2 and 3 of tmr are available in unit 0, and unit 1, respectively. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 991 of 1340 rej09b0499-0200 adie adst adf addra addrb addrc addrd channel 0 (an0) operation state channel 1 (an1) operation state channel 2 (an2) operation state channel 3 (an3) operation state set * set * set * a/d conversion start clear * clear * waiting for conversion waiting for conversion waiting for conversion waiting for conversion waiting for conversion reading a/d conversion result reading a/d conversion result a/d conversion 1 a/d conversion 2 a/d conversion result 1 a/d conversion result 2 waiting for conversion note: * indicates the timing of instruction execution by software. figure 21.3 example of a/d converter op eration (single mode, channel 1 selected) 21.4.2 scan mode in scan mode, a/d conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight* 1 channels. two types of scan mode are provided, that is, continuous scan mode where a/d conversion is repeat edly performed and one-cycle scan mode* 2 where a/d conversion is performed for the sp ecified channels for one cycle. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 992 of 1340 rej09b0499-0200 (1) continuous scan mode 1. when the adst bit in adcsr is set to 1 by software, tpu* 1 , tmr* 3 , or an external trigger input, a/d conversion starts on the first channel in the specified channel group. consecutive a/d conversion* 1 on a maximum of four channels (scane and scans = b'10) or on a maximum of eight channels (scane and scans = b'11) can be selected. when consecutive a/d conversion is performed on four channels, a/d conversion starts on an0 when ch3 and ch2 of unit 0 = b'00, on an4 when ch3 and ch2 of units 0 and 1 = b'01. when consecutive a/d conversion* 1 is performed on eight channels, a/d conversion starts on an0 when ch3 = b'0. 2. when a/d conversion for each channel is comple ted, the a/d conversion result is sequentially transferred to the corresponding addr of each channel. 3. when a/d conversion of all selected channels is completed, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. a/d conversion of the first channel in the group starts again. 4. the adst bit is not cleared au tomatically, and steps 2 to 3 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops and the a/d converter enters wait state. if the adst bit is la ter set to 1, a/d conversion starts again from the first channel in the group. notes: 1. consecutive a/d conversion on eight channels is only possible in unit 0. 2. unit 0: the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a-usb) is usable. 3. as conversion start trigger, units 0 and 1 of tmr, and units 2 and 3 of tmr are available in unit 0, and unit 1, respectively. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 993 of 1340 rej09b0499-0200 adst adf addra addrb addrc addrd set * 1 clear * 1 clear * 1 * 2 waiting for conversion channel 0 (an0) operation state channel 1 (an1) operation state channel 2 (an2) operation state channel 3 (an3) operation state waiting for conversion a/d conver- sion 1 a/d conversion result 3 waiting for conversion waiting for conversion waiting for conversion a/d conversion result 2 a/d conversion result 4 a/d conver- sion 5 a/d conver- sion 4 a/d conversion time waiting for conversion a/d conver- sion 3 waiting for conversion waiting for conversion waiting for conversion a/d conver- sion 2 a/d conversion result 1 transfer a/d conversion consecutive execution notes: 1. 2. indicates the timing of instruction execution by software. data being converted is ignored. figure 21.4 example of a/d conversion (continuous scan mode, three chan nels (an0 to an2) selected) section 21 a/d converter rev. 2.00 oct. 20, 2009 page 994 of 1340 rej09b0499-0200 (2) one-cycle scan mode * 1. set the adstclr bit in adcr to 1. 2. when the adst bit in adcsr is set to 1 by software, tpu, tmr (units 2 and 3), or an external trigger input, a/d conversion starts on the first channel in the specified channel group. consecutive a/d conversion on a maximum of four channels (scane and scans = b'10) can be selected. for unit 1, a/d conver sion starts on an4 when ch3 and ch2 = b'01. 3. when a/d conversion for each channel is comple ted, the a/d conversion result is sequentially transferred to the corresponding addr of each channel. 4. when a/d conversion of all selected channels is completed, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 5. the adst bit is automatical ly cleared when a/d conversion is completed for all of the channels that have been selected. a/d conver sion stops and the a/d converter enters a wait state. note: * for unit 0, the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a-usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 995 of 1340 rej09b0499-0200 a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion time a/d conversion one-cycle execution adst adf addre addrf addrg addrh channel 4 (an4) operation state channel 5 (an5) operation state channel 6 (an6) operation state channel 7 (an7) operation state set * clear * waiting for conversion waiting for conversion waiting for conversion waiting for conversion waiting for conversion waiting for conversion transfer waiting for conversion a/d conversion 1 a/d conversion 2 a/d conversion 3 note: indicates the timing of instruction execution by software. figure 21.5 example of a/d conversion (one-cycle scan mode, three channels (an4 to an6) selected) section 21 a/d converter rev. 2.00 oct. 20, 2009 page 996 of 1340 rej09b0499-0200 21.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) passes after the adst bit in adcsr is set to 1, then starts a/d conversion. figure 21.6 shows the periods of a/d conversion. tables 21.3 to 21.5 show the timing of a/d conversion. as shown in figure 21.6, the a/d conversion time (t conv ) includes the a/d conversion start delay time (t d ) and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcsr. total conversion times ther efore vary within the ranges indicated in tables 21.3 to 21.5. in scan mode, the values given in tables 21.3 to 21.5 apply to the first conversion time. the values given in table 21.6 apply to the second and subsequent rounds of conversion. in either case, the cks1 and cks0 bits in adcr, the icksel* 1 bit in admosel, and the excks* 2 bit in adcsr should be set so that the conversion tim e is within the ranges indicated by the a/d conversion characteristics. notes: 1. unit 0: the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a-usb) is usable. unit 1: access to the full- spec emulator (e6000h) is prohibited but the on-chip emulator (e10a-usb) is usable. 2. unit 0: the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a-usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 997 of 1340 rej09b0499-0200 (1) (2) t d t spl t conv p address write signal input sampling timing adf [legend] (1): adcsr write cycle (2): adcsr address t d: a/d conversion start delay time t spl : input sampling time t conv : a/d conversion time figure 21.6 periods of a/d conversion table 21.3 characteristics of a/ d conversion (unit 0: when excks * = 0, icksel = 0, and adsstr * = h'0f) (1) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay time t d 3 ? 14 3 ? 10 3 ? 8 3 ? 7 input sampling time t spl ? 312 ? ? 156 ? ? 78 ? ? 39 ? a/d conversion time t conv 517 ? 528 261 ? 268 133 ? 138 69 ? 73 notes: values in the tabl e are numbers of states. * the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a- usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 998 of 1340 rej09b0499-0200 table 21.3 characteristics of a/ d conversion (unit 0: when excks * = 1, icksel = 0, and adsstr * = h'0f) (2) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay time t d 3 ? 14 3 ? 10 3 ? 8 3 ? 7 input sampling time t spl ? 120 ? ? 60 ? ? 30 ? ? 15 ? a/d conversion time t conv 325 ? 336 165 ? 172 85 ? 90 45 ? 49 notes: values in the tabl e are numbers of states. * the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a- usb) is usable. table 21.4 characteristics of a/d conversion (unit 1: when excks = 0, icksel = 0, and adsstr * = h'0f) (1) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay time t d 4 ? 14 4 ? 10 4 ? 8 4 ? 7 input sampling time t spl ? 312 ? ? 156 ? ? 78 ? ? 39 ? a/d conversion time t conv 518 ? 528 262 ? 268 134 ? 138 70 ? 73 notes: values in the tabl e are numbers of states. * access to the full-spec emulator (e6000h) is prohibited but the on-chip emulator (e10a- usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 999 of 1340 rej09b0499-0200 table 21.4 characteristics of a/d conversion (unit 1: when excks = 1, icksel = 0, and adsstr * = h'0f) (2) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay time t d 4 ? 14 4 ? 10 4 ? 8 4 ? 7 input sampling time t spl ? 120 ? ? 60 ? ? 30 ? ? 15 ? a/d conversion time t conv 326 ? 336 166 ? 172 86 ? 90 46 ? 49 notes: values in the tabl e are numbers of states. * access to the full-spec emulator (e6000h) is prohibited but the on-chip emulator (e10a- usb) is usable. table 21.5 characteristics of a/d conversion (when excks * 1 = 1, icksel * 1 = 0, and adsstr * 2 = h'19) i :p = 1:1/2 unit 0 unit 1 item symbol min. typ. max. min. typ. max. a/d conversion start delay time t d 2.5 ? 6.5 3.5 ? 6.5 input sampling time t spl ? 12.5 ? ? 12.5 ? a/d conversion time t conv 30 ? 34 31 ? 34 notes: values in the table are numbers of states (cycles of p ). make the sampling setting 25 (adssrt = d'25). 1. unit 0: the full-spec em ulator (e6000h) should not be us ed, but the on-chip emulator (e10a-usb) is usable. 2. unit 0: the full-spec em ulator (e6000h) should not be us ed, but the on-chip emulator (e10a-usb) is usable. unit 1: access to the full-spec emulator (e6000h) is prohibited but the on-chip emulator (e10a-usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1000 of 1340 rej09b0499-0200 table 21.6 period of a/d conversion (scan mode) (units 0 and 1) excks * 3 icksel cks1 cks0 conversion time in states (cycles of p ) 0 512 (fixed) 0 1 256 (fixed) 0 128 (fixed) 0 1 1 64 (fixed) 0 1 * 3 * 4 ? ? setting prohibited 0 320 * 1 0 1 160 * 1 0 80 * 1 0 1 1 40 * 1 1 1 * 3 * 4 ? ? 25 * 2 notes: 1. make the sampling setting15 (adssrt = d'15). 2. when p = i /2, make the sampling setting 25 (adssrt = d'25). 3. unit 0: the full-spec em ulator (e6000h) should not be us ed, but the on-chip emulator (e10a-usb) is usable. 4. unit 1: access to the full-spec emulator (e6000h) is prohibited but the on-chip emulator (e10a-usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1001 of 1340 rej09b0499-0200 21.4.4 timing of external trigger input a/d conversion can be externally triggered. for unit 0, an external trigger is input from the adtrg0 pin when the trgs1, trgs0, and extrgs bits are set to b'110 in adcr_0. for unit 1, an external trigger is input from the adtrg1 pin when the trgs1, trgs0, and extrgs bits are set to b'110 in adcr_1. a/d conversion starts when the adst bit in adcsr is set to 1 on the falling edge of the adtrg pin. other operations, in both si ngle and scan modes, are the same as when the adst bit has been set to 1 by software. figure 21.7 shows the timing. also, a/d conversion for multiple units can be externally triggered (multiple units can start simultaneously). for units 0 and 1, an external trigger is input from the adtrg0 pin when the trgs1, trgs0, and extrgs bits are set to b'111 in adcr_0 and adcr_1. a/d conversion starts when the adst bit in adcsr is set to 1 on the falling edge of the adtrg0 pin. the timing is different from the one when multiple un its do not start simultaneously. figure 21.8 shows the timing. a/d conversion adst p adtrg internal trigger signal figure 21.7 external trigger inpu t timing (trgs1, trgs0, and extrgs b'111) section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1002 of 1340 rej09b0499-0200 p adtrg0 internal trigger signal adst a/d conversion figure 21.8 external trigg er input timing when multiple units start simultaneously (trsg1, trgs0, and extrgs = b'111) 21.4.5 setting the system clock mode in system clock mode, set i = 50 mhz, p = i /2, and make the sampling setting 25. a/d conversion* 1 with a conversion time of 1 s per channel is possible. for information on controlling the frequency of the system clock relative to the input clock, see section 26, clock pulse generator. when the adst bit is cleared to 0, start a/d conversion following the procedures shown below. 1. set p = i /2. 2. release the a/d converter fr om the module-stopped state. 3. set the excks* 2 bit in adcsr to 1 (making setting of the number of states for sampling in adsstr* 2 * 3 effective). 4. set* 2 * 3 the icksel bit in admodsel* 2 * 3 to 1 (selecting system clock mode). 5. write h'19 to adsstr* 2 * 3 (setting the number of states for sampling to 25). 6. start a/d conversion (set the adst bit to 1 or have the trigger signal initiate conversion). notes: 1. the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a- usb) is usable. 2. for unit 0, the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a-usb) is usable. 3. for unit 1, access to the full-spec emulator (e6000h) is prohibited, but the on-chip emulator (e10a-usb) is usable. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1003 of 1340 rej09b0499-0200 21.5 interrupt source the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. setting the adie bit to 1 when the adf bit in adcsr is set to 1 after a/d conversion is completed enables adi interrupt requests. th e data transfer controller (dtc)* and dma controller (dmac) can be activated by an adi interrupt. having the converted data read by the dtc* or dmac in response to an adi interrupt enables continuous conversion to be achieved without imposing a load on software. note: * only possible in unit 0. table 21.7 a/d converter interrupt source name interrupt source interrupt fl ag dtc activation dmac activation adi a/d conversion end adf possible * possible note: * only possible in unit 0. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1004 of 1340 rej09b0499-0200 21.6 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes. ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 21.9). ? offset error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 21.10). ? full-scale error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 21.10). ? nonlinearity error the error with respect to the ideal a/d convers ion characteristic between the zero voltage and the full-scale voltage. does not in clude the offset error, full-scal e error, or qu antization error (see figure 21.10). ? absolute accuracy the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1005 of 1340 rej09b0499-0200 1111111111 1111111110 1111111101 1111111100 0000000011 0000000010 0000000001 0000000000 1 1024 2 1024 1022 1024 1023 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage figure 21.9 a/d conversion accuracy definitions fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 21.10 a/d conversion accuracy definitions section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1006 of 1340 rej09b0499-0200 21.7 usage notes 21.7.1 module stop function setting operation of the a/d converter can be disabled or enabled using the module stop control register. the initial setting is for operation of the a/d conver ter to be halted. register access is enabled by clearing the module stop state. set the cks1 and cks2 bits to 1 and clear the adst, trgs1, trgs0, and extrgs bits all to 0 to disable a/d conversion when entering module stop state after operation of the a/d converter. after that, set the module stop control register after executing a dummy read from adcsr. for details, see section 27, power-down modes. 21.7.2 a/d input hold function in software standby mode when this lsi enters software standby mode with a/d conversion enabled, the analog inputs are retained, and the analog power supply current is equal to as during a/d conversion. if the analog power supply current needs to be reduced in software standby mode, set the cks1 and cks2 bits to 1 and clear the adst, trgs1, trgs0, and extrgs bits all to 0 to disable a/d conversion. after that, enter software standby mode af ter executing a dummy read from adcsr. 21.7.3 notes on stopping the a/d converter when the a/d start bit (adst) is cleared during a/d conversion by software, a/d conversion results may be stored incorrectly (addr), or when a/d conversion restarts, the interrupt flag may be misset. to avoid these events, fo llow the steps below. (1) in single mode or scan mo de (one-cycle scan mode) as the adst bit is automatically cleared when a/ d conversion is completed, do not clear the bit during a/d conversion. (2) in scan mode (continuous scan mode) ? when the a/d converter is activated by software do not clear the adst bit during a/d conv ersion. to stop a/d conversion, rewrite the scane bit to change modes from scan mode to single mode. by rewriting the scane bit, the a/d converter is stopped without clearing the adst bit by software. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1007 of 1340 rej09b0499-0200 however, after rewriting the scane bit, it may take up to 1.5-channel a/d conversion time to stop a/d conversion and set the a/d end flag (adf) to 1. moreover, the addr value after a/d conversion is completed should not be used. for details of settings, see figure 21.11. no start switch to single mode (unit 0: adcr_0_scane = 0) (unit 1: adcr_1_scane = 0) adst is automatically cleared after a/d conversion is completed adf = 1? end hardware processing ye s figure 21.11 stopping continuous scan mode activated by software ? when the a/d converter is activ ated by an external trigger do not clear the adst bit duri ng a/d conversion. to stop a/d conversion, disable external triggers and then rewrite the scane bit to change modes from scan mode to single mode. this stops a/d conversion without clearing the adst bit by software. however, after rewriting the scane bit, it may take up to 1.5-channel a/d conversion time to stop a/d conversion and set the a/d end flag (adf) to 1. moreover, the addr value after a/d conversion is completed should not be used. for details of settings, see figure 21.12. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1008 of 1340 rej09b0499-0200 no ye s start switch to single mode (unit 0: adcr_0_scane = 0) (unit 1: adcr_1_scane = 0) disable external trigger input unit 0 (adcr_0_trgs1, trgs0, extrgs) = 001 unit 1 (adcr_1_trgs1, trgs0, extrgs) = 011 adf = 1? external trigger stopped? end ye s no adst is automatically cleared after a/d conversion is completed hardware processing figure 21.12 stopping continuous scan mode activated by external trigger 21.7.4 notes in system clock mode 1. for board design, see section 21.7.8, notes on board design. 2. in system clock mode, operate all units with the system clock (i ). the system clock and the peripheral module clock should not be used together. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1009 of 1340 rej09b0499-0200 21.7.5 permissible signal source impedance this lsi's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less when excks* 1 = 0 and icksel = 0 or 1 k or less when excks* 1 = 1 and icksel = 0, or when icksel = 1* 1 * 2 . this specification is provided to enable the a/d co nverter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance ex ceeds the permissible signal source impedance, charging may be insufficient and it may not be possible to guarantee the a/d conversion accuracy. however, if a large capacita nce is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 10 k , and the signal source impedance is ignored. however, since a low-pass filter effect is obtained in this case, it may not be possible to follow an anal og signal with a large di fferential coefficient (e.g., 5 mv/ s or greater) (see figure 21.13). when converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. notes: 1. unit 0: the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a-usb) is usable. 2. unit 1: access to the full-spec emulator (e6000h) is prohibited, but the on-chip emulator (e10a-usb) is usable. equivalent circuit of the a/d converter this lsi 20 pf cin = 15 pf 10 k low-pass filter c 0.1 f sensor output impedance excks = 0, icksel = 0 : r 5 k excks = 1, icksel = 0 : 1 k or less icksel = 1 : 1 k or less sensor input figure 21.13 example of analog input circuit section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1010 of 1340 rej09b0499-0200 21.7.6 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefor e noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, acting as antennas. 21.7.7 setting range of analog power supply and other pins if the conditions shown below are not met, the reliability of the lsi may be adversely affected. ? analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range av ss v an v ref . ? relation between av cc , av ss and v cc , v ss as the relationship between av cc , av ss and v cc , v ss , set av cc = v cc 0.3 v and av ss = v ss . if the a/d converter is not used, set av cc = v cc and av ss = v ss . ? vref setting range the reference voltage at the vref pin should be set in the range v ref av cc . section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1011 of 1340 rej09b0499-0200 21.7.8 notes on board design in board design, follow the notes below. 1. digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversel y affecting a/d conversion values. moreover, digital circuitry must be isolated from the analog reference power supply pin (v ref ), analog power supply pin (av cc ), and analog ground pin (av ss ) by shielding the analog input pins (an0 to an7) with the analog ground pin (av ss ). 2. lines should be connected with the analog reference power supply pin (av cc ), analog power supply pin (v ref ), and analog ground pin (av ss ) with low impedance as possible. 3. the analog ground pin (av ss ) should be connected at one point to a stable ground (v ss ) on the board. 21.7.9 notes on noise countermeasures a protection circuit connected to prevent damage du e to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an7) should be connected to av cc and av ss as shown in figure 21.14. also, the bypa ss capacitors connected to av cc and v ref and the filter capacitor connected to the an0 to an7 pins must be connected to av ss . the bypass capacitors between av cc and av ss , or v ref and av ss should be placed as close to pins as possible. if a filter capacitor is connected, the input currents at the an0 to an7 pins are averaged, and so an error may arise. also, when a/d conversion is performed frequen tly, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the current in put via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding the circuit constants. section 21 a/d converter rev. 2.00 oct. 20, 2009 page 1012 of 1340 rej09b0499-0200 av cc * 1 * 1 vref an0 to an7 av ss notes: values are reference values. 1. 2. r in : input impedance r in * 2 100 0.1 f 0.01 f 10 f figure 21.14 example of analog input protection circuit table 21.8 analog pin specifications item min. max. unit analog input capacitance ? 20 pf excks = 0, icksel = 0 ? 5 excks = 1, icksel = 0 ? 1 permissible signal source impedance icksel = 1 ? 1 k 20 pf to a/d converter an0 to an11 10 k note: values are reference values. figure 21.15 analog input pin equivalent circuit section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1013 of 1340 rej09b0499-0200 section 22 d/a converter 22.1 features ? 8-bit or 10-bit resolution ? two output channels ? maximum conversion time of 10 s (with 20 pf load) ? output voltage of 0 v to v ref ? d/a output hold function in software standby mode ? module stop state specifiable module data bus internal data bus [legend] dadr0h/l: d/a data register 0 h/l dadr1h/l: d/a data register 1 h/l dadr01t: d/a data register 01t dacr01: d/a control register 01 avss vref avcc dadr0h dadr0l dadr1h dadr1l dadr01t dacr01 da0 da1 10-bit d/a control circuit bus interface figure 22.1 block diagram of the 10-bit d/a converter section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1014 of 1340 rej09b0499-0200 22.2 input/output pins table 22.1 shows the pin configuration of the d/a converter. table 22.1 pin configuration pin name symbol i/o function analog power supply pin av cc input analog block power supply analog ground pin av ss input analog block ground reference voltage pin v ref input d/a conversion reference voltage analog output pin 0 da0 output channel 0 analog output analog output pin 1 da1 output channel 1 analog output 22.3 register descriptions the d/a converter has the following registers. ? d/a data register 0h (dadr0h) ? d/a data register 0l (dadr0l) ? d/a data register 1h (dadr1h) ? d/a data register 1l (dadr1l) ? d/a data register 01t (dadr01t) ? d/a control register 01 (dacr01) section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1015 of 1340 rej09b0499-0200 22.3.1 d/a data registers 0 and 1 (dadr0, dadr1) a d/a data register, dadr, is internally a 10-bit register that holds data to be d/a converted. when analog output is enabled, the value held by dadr is converted and output on the analog- output pins. in the memory map, each dadr is configured of two registers, dadrnh and dadrnl (n = 0, 1). the eight higher-order bits of the corresponding dadr are stored in dadr0h or dadr1h. dadr0h and dadr1h are directly r eadable and writable registers. the two lower-order bits of the dadr are stored in dadr0l or dadr1l. dadr0l and dadr1l are non-readable registers. writing is accomplished by transferring values from the temporary register, dadr01t. when the value in a dadr is to be updated, the new lower-order two bits of the value must previously have been written to dadr01t. the corresponding dadr is actually updated at the same time as a new value is written to dadr0h or dadr1h. the eight higher-order bits are reflected as written in dadr0h or dadr1h, while the two lower-order bits are updated by transfer from dadr01t to dadr0l or dadr1l. 22.3.2 d/a data registers 0h and 1h (dadr0h and dadr1h) dadr0h and dadr1h are 8-bit readable/writabl e registers. when a value is written to dadr0h or dadr1h, the corresponding bits of dadr01t are simultaneously transferred to dadr0l or dadr1l. 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w bit bit name initial value r/w section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1016 of 1340 rej09b0499-0200 22.3.3 d/a data registers 0l and 1l (dadr0l and dadr1l) registers dadr0l and dadr1l are for storing the two lower-order bits of the ten-bit value for d/a conversion held by the corresponding dadr. dadr0l and dadr1l are non-readable registers. writing is accomplished by transferring values from the temporary register, dadr01t. when writing proceeds, the value must have been set beforehand in dadr01t. transfer from dadr01t to dadr0l proceeds when a value is written to dadr0h. transfer from dadr01t to dadr1l proceeds when a value is written to dadr1h. 7 0 ? 6 0 ? 5 ? ? ? 4 ? ? ? 3 ? ? ? 2 ? ? ? 1 ? ? ? 0 ? ? ? bit bit name initial value r/w 22.3.4 d/a data register 01t (dadr01t) dadr01t is an 8-bit temporary register that is used to transfer data to dadr0l and dadr1l. writing is only valid for bits 7 and 6. values written to bits 5 to 0 are ignored. in reading, the most recent setting (of bits 7 and 6) and the values for the two lo wer-order bits held in dadr0l and dadr1l can be read. the value for the two lower-order bits of dadr1 can be read in bits 5 and 4. the value for the two lower-order bits of dadr0 can be read in bits 3 and 2. bits 1 and 0 are reserved. in read ing, these bits are read as 1. bits 7 and 6 of dadr01t are used to store the two lower-order bits of a 10-bit value for d/a conversion. 7 dadt1 0 r/w 6 dadt0 0 r/w 5 dad1l1 0 r 4 dad1l0 0 r 3 dad0l1 0 r 2 dad0l0 0 r 1 ? 1 r 0 ? 1 r bit bit name initial value r/w section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1017 of 1340 rej09b0499-0200 22.3.5 d/a control register 01 (dacr01) dacr01 controls the operatio n of the d/a converter. 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 r 3 ? 1 r 2 ? 1 r 1 ? 1 r 0 ? 1 r bit bit name initial value r/w bit bit name initial value r/w description 7 daoe1 0 r/w d/a output enable 1 controls d/a conversion and analog output. 0: analog output of channel 1 (da1) is disabled 1: d/a conversion of channel 1 is enabled. analog output of channel 1 (da1) is enabled. 6 daoe0 0 r/w d/a output enable 0 controls d/a conversion and analog output. 0: analog output of channel 0 (da0) is disabled 1: d/a conversion of channel 0 is enabled. analog output of channel 0 (da0) is enabled. 5 dae 0 r/w d/a enable used together with the daoe0 and daoe1 bits to control d/a conversion. when this bit is cleared to 0, d/a conversion is controlled independently for channels 0 and 1. when this bit is set to 1, d/a conversion for channels 0 and 1 is controlled together. output of conversion results is always controlled by the daoe0 and daoe1 bits. for details, see table 22.2, control of d/a conversion. 4 to 0 ? all 1 r reserved these are read-only bits and cannot be modified. section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1018 of 1340 rej09b0499-0200 table 22.2 control of d/a conversion bit 5 dae bit 7 daoe1 bit 6 daoe0 description 0 d/a conversion is disabled. 0 1 d/a conversion of channel 0 is enabled and d/a conversion of channel 1 is disabled. analog output of channel 0 (da0) is enabled and analog output of channel 1 (da1) is disabled. 0 d/a conversion of channel 0 is disabled and d/a conversion of channel 1 is enabled. analog output of channel 0 (da0) is disabled and analog output of channel 1 (da1) is enabled. 0 1 1 d/a conversion of channels 0 and 1 is enabled. analog output of channels 0 and 1 (da0 and da1) is enabled. 0 d/a conversion of channels 0 and 1 is enabled. analog output of channels 0 and 1 (da0 and da1) is disabled. 0 1 d/a conversion of channels 0 and 1 is enabled. analog output of channel 0 (da0) is enabled and analog output of channel 1 (da1) is disabled. 0 d/a conversion of channels 0 and 1 is enabled. analog output of channel 0 (da0) is disabled and analog output of channel 1 (da1) is enabled. 1 1 1 d/a conversion of channels 0 and 1 is enabled. analog output of channels 0 and 1 (da0 and da1) is enabled. 22.3.6 usage as an 8-bit d/a converter in advance of usage as an 8-bit d/a converter, fix the lower-order two bits to 0 by clearing the dadt1 and dadt0 bits in dadr01t to 0. by clearing these bits in dadr01t to 0 in advance, the d/a converter is made to function by simply setting dadr0h or dadr1h. that is, d/a conversion of the eight higher-order bits proceed s when the two lower-order bits remain fixed to 0. section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1019 of 1340 rej09b0499-0200 22.4 operation the d/a converter includes d/a conversion circuits for two channels, each of which can operate independently. when the daoe bit in dacr01 is set to 1, d/a conversion is enabled and the conversion result is output. an operation example of d/a conversion on channel 0 is shown below. figure 22.2 shows the timing of this operation. 1. write the conversion data to dadr0. 2. set the daoe0 bit in dacr01 to 1 to start d/a conversion. the conversion result is output from the analog output pin da0 after the conversion time t dconv has elapsed. the conversion result continues to be output until dadr0 is writte n to again or the daoe0 bit is cleared to 0. output values are expressed by the following formulae. ? formula for 8-bit conversion contents of dadr 256 x vref ? formula for 10-bit conversion contents of dadr 1024 x vref 3. if dadr0 is written to again, the conversion is immediately started. the conversion result is output after the conversion time t dconv has elapsed. 4. if the daoe0 bit is cleared to 0, analog output is disabled. section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1020 of 1340 rej09b0499-0200 conversion data 1 conversion result 1 high-impedance state t dconv dadr0 write cycle da0 daoe0 dadr0 address p dacr01 write cycle conversion data 2 conversion result 2 t dconv [legend] t dconv : d/a conversion time dadr0 write cycle dacr01 write cycle figure 22.2 example of d/a converter operation section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1021 of 1340 rej09b0499-0200 22.5 usage notes 22.5.1 module stop state setting operation of the d/a converter can be disabled or enabled using the module stop control register. the initial setting is for operation of the d/a conver ter to be halted. register access is enabled by clearing the module stop stat e. for details, refer to section 27, power-down modes. 22.5.2 d/a output hold function in software standby mode when this lsi makes a transition to software standby mode with d/a conversion enabled, the d/a outputs are retained, and the flow of current from the analog power supply remains the same as during d/a conversion. if the analog power-supply current has to be reduced in software standby mode, clear the daoe0, daoe1, and dae bits to 0 to disable d/a conversion. 22.5.3 notes on deep soft ware standby mode when this lsi makes a transition to deep software standby mode with d/a conversion enabled, the d/a outputs enter high-impedance state. 22.5.4 limitations on emulators the limitations described below apply to emulation of the 10-bit d/a converter. in emulation with the full-spec emulator (e6000h ), the resolution of the analog output becomes eight bits, and the precision of d/a conversion is not guaranteed. furtherm ore, when dadr01t is read, the values in emulation differ from those for the actual product. thus, as a precondition for emulation with the full-spec emulator (e6000h), do not read dadr01t. no particular limitations apply to emula tion with the on-chip emulator (e10a-usb). the above notes are summarized in table 22.3 below. section 22 d/a converter rev. 2.00 oct. 20, 2009 page 1022 of 1340 rej09b0499-0200 table 22.3 limitations on emulators detail of operation subject to the limitation operation of the actual product operation with the e10a-usb operation with the e6000h writing to dadr01t setting of the two lower- order bits of a 10-bit value for d/a conversion as at left even if writing is executed, the value written will be ignored. reading dadr01t ability to read the two lower-order bits of a 10-bit value for d/a conversion as at left reading is not possible. values read out are not defined. analog output: resolution 10 bits as at left 8 bits (two lower-order bits are ignored) analog output: precision d/a precision is guaranteed as at left d/a precision is not guaranteed section 23 ram rev. 2.00 oct. 20, 2009 page 1023 of 1340 rej09b0499-0200 section 23 ram this lsi has a high-speed static ram. the ram is connected to the cpu by a 32-bit data bus, enabling one-state access by the cpu to all byte data, word data, and longword data. the ram can be enabled or disabled by means of the rame bit in the sy stem control register (syscr). for details on syscr, refer to section 3.2.2, system control register (syscr). the ram size is 40 kbytes in the h8sx/1655, h8sx/1655m, h8sx/1652, and h8sx/1652m. product classification ram size ram addresses h8sx/1652 h8sx/1655 flash memory version h8sx/1652m h8sx/1655m 40 kbytes h'ff2000 to h'ffbfff section 23 ram rev. 2.00 oct. 20, 2009 page 1024 of 1340 rej09b0499-0200 section 24 flash memory rev. 2.00 oct. 20, 2009 page 1025 of 1340 rej09b0499-0200 section 24 flash memory the flash memory has the followin g features. figure 24.1 is a bloc k diagram of the flash memory. 24.1 features ? rom size product classification part no. rom size rom address h8sx/1652 r5f61652 r5f61652m 384 kbytes h'000000 to h'05ffff (modes 1, 2, 3, 6, and 7) h8sx/1655 r5f61655 r5f61655m 512 kbytes h'000000 to h'07ffff (modes 1, 2, 3, 6, and 7) ? two memory mats the start addresses of two memory spaces (memor y mats) are allocated to the same address. the mode setting in the initiation determines which memory mat is initiated first. the memory mats can be switched by using the bank-switching method after initiation. ? user mat initiated at a reset in user mode: 384 kbytes/512 kbytes ? user boot mat is initiated at reset in user boot mode: 16 kbytes ? programming/erasing interface by the download of on-chip program this lsi has a programming/erasing program. after downloading this program to the on-chip ram, programming/erasure can be performed by setting the parameters. ? programming/erasing time programming time: 1 ms (typ.) for 128-byte simultaneous programming erasing time: 600 ms (typ.) per 1 block (64 kbytes) ? number of programming the number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.) ? three on-board programming modes sci boot mode: using the on-chip sci_4, the user mat and user boot mat can be programmed/erased. in sci boot mode, the bit rate between the host and this lsi can be adjusted automatically. usb boot mode: using the on-chip usb module, the user mat can be programmed/erased. user programming mode: using a desired interf ace, the user mat can be programmed/erased. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1026 of 1340 rej09b0499-0200 user boot mode: using a desired interface, the user boot program can be made and the user mat can be programmed/erased. ? off-board programming mode programmer mode: using a prom programmer, the user mat and user boot mat can be programmed/erased. ? programming/erasing protection protection against programming/erasure of the flash memory can be set by hardware protection, software protection, or error protection. ? flash memory emulation function using the on-chip ram realtime emulation of the flash memory progra mming can be performed by overlaying parts of the flash memory (user mat) area and the on-chip ram. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1027 of 1340 rej09b0499-0200 fccs fpcs fecs fkey fmats ftdar ramer control unit memory mat unit flash memory user mat: 384 kbytes (h8sx/1652) 512 kbytes (h8sx/1655) user boot mat: 16 kbytes operating mode module bus mode pins internal data bus (32 bits) internal address bus [legend] fccs: flash code control/status register fpcs: flash program code select register fecs: flash erase code select register fkey: flash key code register fmats: flash mat select register ftdar: flash transfer destination address register ramer: ram emulation register figure 24.1 block diagram of flash memory section 24 flash memory rev. 2.00 oct. 20, 2009 page 1028 of 1340 rej09b0499-0200 24.2 mode transition diagram when the mode pins are set in the reset state an d reset start is performed, this lsi enters each operating mode as shown in figure 24.2. although the flash memory can be read in user mode, it cannot be programmed or erased. the flash memory can be programmed or erased in boot mode, user programming mode, user boot mode, and programmer mode. the differences between boot mode, user programming mode, user boot mode, and programmer mode are shown in table 24.1. reset state programmer mode user mode user program mode user boot mode sci boot mode usb boot mode rom disabled mode notes: 1. programming and erasure is started. 2. programing and erasure is completed. on-board programming mode ram emulation can be available * 2 * 1 res = 0 user mode setting user boot mode se tting res = 0 res = 0 sci boot mode setting res = 0 usb boot mode setting res = 0 res = 0 res = 0 programmer mode setting rom disabled mode setting figure 24.2 mode transition of flash memory section 24 flash memory rev. 2.00 oct. 20, 2009 page 1029 of 1340 rej09b0499-0200 table 24.1 differences between boot mode , user programming mode, user boot mode, and programmer mode item sci boot mode usb boot mode user programming mode user boot mode programmer mode programming/ erasing environment on-board programming on-board programming on-board programming on-board programming off-board programming programming/ erasing enable mat ? user mat ? user boot mat ? user mat ? user mat ? user mat ? user mat ? user boot mat programming/ erasing control command command programming/ erasing interface programming/ erasing interface command all erasure o (automatic) o (automatic) o o o (automatic) block division erasure o * 1 o * 1 o o program data transfer from host via sci from host via usb from desired device via ram from desired device via ram via programmer ram emulation o o reset initiation mat embedded program storage area embedded program storage area user mat user boot mat * 2 ? transition to user mode changing mode and reset changing mode and reset completing programming/ erasure * 3 changing mode and reset ? notes: 1. all-erasure is performed. afte r that, the specified block can be erased. 2. first, the reset vector is fetched from the embedded program storage area. after the flash memory related registers are checked, the reset vector is fetched from the user boot mat. 3. in this lsi, the user programming mode is defined as the period from the timing when a program concerning programming and erasur e is started to the timing when the program is completed. for details on a program concerning programming and erasure, see section 24.8.3, user programming mode. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1030 of 1340 rej09b0499-0200 24.3 memory mat configuration the memory mats of flash memory in this lsi consists of the 384-kbyte/512-kbyte user mat and 16-kbyte user boot mat. th e start addresses of the user mat and user boot mat are allocated to the same address. therefore, when the program execu tion or data access is performed between the two memory mats, the memory mats must be switched by the flash mat select register (fmats). the user mat or user boot mat can be read in all modes. however, the user boot mat can be programmed or erased only in boot mode and programmer mode. the size of the user mat is different from that of the user boot mat. addresses which exceed the size of the 16-kbyte user boot mat should not be accessed. if an attempt is made, data is read as an undefined value. user mat user boot mat h'000000 h'07ffff * 2 notes: 1. 384 kbytes in the h8sx/1652. 2. h'05ffff in the h8sx/1655. h'000000 h'003fff 512 kbytes * 1 16 kbytes figure 24.3 memory mat configuration (h8sx/1655) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1031 of 1340 rej09b0499-0200 24.4 block structure 24.4.1 block diagram of h8sx/1652 figure 24.4 (1) shows the block structure of the 384-kbyte user mat. the heavy-line frames indicate the erase blocks. the thin-line frames indicate the programming units and the values inside the frames stand for the addresses. the user mat is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. the user mat can be erased in these divided block units. programming is done in 128-byte units st arting from where the lower address is h'00 or h'80. ram emulation can be performed in the eight 4-kbyte blocks. eb0 erase unit: 4 kbytes eb1 erase unit: 4 kbytes eb2 erase unit: 4 kbytes eb3 erase unit: 4 kbytes eb4 erase unit: 4 kbytes eb5 erase unit: 4 kbytes eb6 erase unit: 4 kbytes eb7 erase unit: 4 kbytes eb8 erase unit: 32 kbytes eb9 erase unit: 64 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'004fff h'00507f h'005fff h'001fff h'002fff h'003fff h'01ffff h'00607f h'006fff h'00707f h'007fff h'00807f h'00ffff h'01007f programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'005000 h'005001 h'005002 h'006000 h'006001 h'006002 h'007000 h'007001 h'007002 h'008000 h'008001 h'008002 h'010000 h'010001 h'010002 h'000f80 h'000f81 h'000f82 h'001f80 h'001f81 h'001f82 h'002f80 h'002f81 h'002f82 h'003f80 h'003f81 h'003f82 h'004f80 h'004f81 h'004f82 h'00ff80 h'00ff81 h'00ff82 h'01ff80 h'01ff81 h'01ff82 h'005f80 h'005f81 h'005f82 h'006f80 h'006f81 h'006f82 h'007f80 h'007f81 h'007f82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? eb10 eb13 erase unit: 64 kbytes h'05ffff h'02007f h'05007f programming unit: 128 bytes programming unit: 128 bytes h'020000 h'020001 h'020002 h'050000 h'050001 h'050002 h'04ff80 h'04ff81 h'04ff82 h'05ff80 h'05ff81 h'05ff82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? h'0affff figure 24.4 (1) user mat block structure of h8sx/1652 section 24 flash memory rev. 2.00 oct. 20, 2009 page 1032 of 1340 rej09b0499-0200 24.4.2 block diagram of h8sx/1655 figure 24.4 (2) shows the block structure of the 512-kbyte user mat. the heavy-line frames indicate the erase blocks. the thin-line frames indicate the programming units and the values inside the frames stand for the addresses. the user mat is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. the user mat can be erased in these divided block units. programming is done in 128-byte units starting from where the lower address is h'00 or h'80. ram emulation can be performed in the eight 4-kbyte blocks. eb0 erase unit: 4 kbytes eb1 erase unit: 4 kbytes eb2 erase unit: 4 kbytes eb3 erase unit: 4 kbytes eb4 erase unit: 4 kbytes eb5 erase unit: 4 kbytes eb6 erase unit: 4 kbytes eb7 erase unit: 4 kbytes eb8 erase unit: 32 kbytes eb9 erase unit: 64 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'004fff h'00507f h'005fff h'001fff h'002fff h'003fff h'01ffff h'00607f h'006fff h'00707f h'007fff h'00807f h'00ffff h'01007f programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'005000 h'005001 h'005002 h'006000 h'006001 h'006002 h'007000 h'007001 h'007002 h'008000 h'008001 h'008002 h'010000 h'010001 h'010002 h'000f80 h'000f81 h'000f82 h'001f80 h'001f81 h'001f82 h'002f80 h'002f81 h'002f82 h'003f80 h'003f81 h'003f82 h'004f80 h'004f81 h'004f82 h'00ff80 h'00ff81 h'00ff82 h'01ff80 h'01ff81 h'01ff82 h'005f80 h'005f81 h'005f82 h'006f80 h'006f81 h'006f82 h'007f80 h'007f81 h'007f82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? eb10 eb15 erase unit: 64 kbytes h'07ffff h'02007f h'07007f programming unit: 128 bytes programming unit: 128 bytes h'020000 h'020001 h'020002 h'070000 h'070001 h'070002 h'06ff80 h'06ff81 h'06ff82 h'07ff80 h'07ff81 h'07ff82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 24.4 (2) user mat block structure of h8sx/1655 section 24 flash memory rev. 2.00 oct. 20, 2009 page 1033 of 1340 rej09b0499-0200 24.5 programming/erasing interface programming/erasure of the flash memory is done by downloading an on-chip programming/ erasing program to the on-chip ram and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming /erasing interface parameters. the procedure program for user programming mode and user boot mode is made by the user. figure 24.5 shows the procedure for creating the procedure program. for details, see section 24.8.3, user programming mode. download on-chip program by setting vbr, fkey, and sco bit in fccs yes no execute initialization (downloaded program execution) select on-chip program to be downloaded and specify destination programming (in 128-byte units) or erasing (in 1-block units) (downloaded program execution) start procedure program for programming/erasing end procedure program programming/erasing completed? figure 24.5 procedure for creating procedure program (1) selection of on-chip prog ram to be downloaded this lsi has programming/erasing programs which can be downloaded to the on-chip ram. the on-chip program to be downloaded is selected by the programming /erasing interface registers. the start address of the on-chip ram where an on-chip program is downloaded is specified by the flash transfer destination address register (ftdar). section 24 flash memory rev. 2.00 oct. 20, 2009 page 1034 of 1340 rej09b0499-0200 (2) download of on-chip program the on-chip program is automatically downloaded by setting the flash key code register (fkey) and the sco bit in the flash code control/status register (fccs) after initializing the vector base register (vbr). the memory mat is replaced w ith the embedded progra m storage area during download. since the memory mat cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip ram). since the download result is returned to the programming/erasing interface parameter, whether download is normally executed or not can be confirmed. the vbr contents can be changed after completion of download. (3) initialization of programming/erasure a pulse with the specified period must be applied when programming or erasing. the specified pulse width is made by the method in which wa it loop is configured by the cpu instruction. accordingly, the operating frequency of the cpu needs to be set before programming/erasure. the operating frequency of the cpu is set by th e programming/erasing interface parameter. (4) execution of programming/erasure the start address of the programming destination and the program data are specified in 128-byte units when programming. the block to be erased is specified with the erase block number in erase-block units when erasing. specifications of the start address of the programming destination, program data, and erase block number are performed by the programming/erasing interface parameters, and the on-chip program is initiated. the on-chip program is executed by using the jsr or bsr instruction and executing the subroutin e call of the specified address in the on-chip ram. the execution result is returned to the programming/erasing interface parameter. the area to be programmed must be erased in advance when programming flash memory. all interrupts are disabled duri ng programming/erasure. (5) when programming/erasure is executed consecutively when processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasure can be reali zed by updating the st art address of the programming destination and program data, or the erase block number. since the downloaded on-chip program is left in the on-chip ram even after programming/erasure completes, download and initialization are not required when the same processing is executed consecutively. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1035 of 1340 rej09b0499-0200 24.6 input/output pins the flash memory is controlled through the input/output pins shown in table 24.2. table 24.2 pin configuration abbreviation i/o function res input reset emle input on-chip emulator enable pin (emle = 0 for flash memory programming/erasure) md2 to md0 input set operating mode of this lsi pm2 input sci boot/usb boot mode setting (valid when boot mode is selected by the md2 to md0 pins) txd4 output serial transmit dat a output (used in sci boot mode) rxd4 input serial receive data input (used in sci boot mode) usd+, usd- input/output usb data in put/output (used in usb boot mode) vbus input usb cable connect/disconnect detection (used in usb boot mode) pm3 input usb bus-power/self-power mode setting (used in usb boot mode) pm4 output d+ pull-up control (used in usb boot mode) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1036 of 1340 rej09b0499-0200 24.7 register descriptions the flash memory has th e following registers. programming/erasing interface registers: ? flash code control/status register (fccs) ? flash program code sel ect register (fpcs) ? flash erase code select register (fecs) ? flash key code register (fkey) ? flash mat select register (fmats) ? flash transfer destination address register (ftdar) programming/erasing interface parameters: ? download pass and fail result parameter (dpfr) ? flash pass and fail result parameter (fpfr) ? flash program/erase frequency parameter (fpefeq) ? flash multipurpose address area parameter (fmpar) ? flash multipurpose data destination area parameter (fmpdr) ? flash erase block select parameter (febs) ? ram emulation register (ramer) there are several operating modes for accessing th e flash memory. respecti ve operating modes, registers, and parameters are assigned to the user mat and user boot mat. the correspondence between operating modes and registers/parameters for use is shown in table 24.3. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1037 of 1340 rej09b0499-0200 table 24.3 registers/parameters and target modes register/parameter down- load initiali- zation program- ming erasure read ram emulation fccs o ? ? ? ? ? fpcs o ? ? ? ? ? fecs o ? ? ? ? ? fkey o ? o o ? ? fmats ? ? o * 1 o * 1 o * 2 ? programming/ erasing interface registers ftdar o ? ? ? ? ? dpfr o ? ? ? ? ? fpfr ? o o o ? ? fpefeq ? o ? ? ? ? fmpar ? ? o ? ? ? fmpdr ? ? o ? ? ? programming/ erasing interface parameters febs ? ? ? o ? ? ram emulation ramer ? ? ? ? ? o notes: 1. the setting is required when programming or erasing the user mat in user boot mode. 2. the setting may be required according to the combination of initiation mode and read target memory mat. 24.7.1 programming/erasing interface registers the programming/erasing interface re gisters are 8-bit registers that can be accessed only in bytes. these registers are initialized by a reset. (1) flash code control/status register (fccs) fccs monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip ram. 7 ? 1 r 6 ? 0 r 5 ? 0 r 4 fler 0 r 3 ? 0 r 0 sco 0 (r)/w * 2 ? 0 r 1 ? 0 r bit bit name initial value r/w note: * this is a write-only bit. this bit is always read as 0. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1038 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 6 5 ? ? ? 1 0 0 r r r reserved these are read-only bits and cannot be modified. 4 fler 0 r flash memory error indicates that an error has occurred during programming or erasing the flash memory. when this bit is set to 1, the flash memory enters the error protection state. when this bit is set to 1, high voltage is applied to the internal flash memory. to reduce the damage to the flash memory, the reset must be released after the reset input period (period of res = 0) of at least 100 s. 0: flash memory operates normally (error protection is invalid) [clearing condition] ? at a reset 1: an error occurs during programming/erasing flash memory (error protection is valid) [setting conditions] ? when an interrupt, such as nmi, occurs during programming/erasure. ? when the flash memory is read during programming/erasure (including a vector read and an instruction fetch). ? when the sleep instruction is executed during programming/erasure (including software standby mode). ? when a bus master other than the cpu, such as the dmac and dtc, obtains bus mastership during programming/erasure. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1039 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 to 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 sco 0 (r)/w * source program copy operation requests the on-chip programming/erasing program to be downloaded to the on-chip ram. when this bit is set to 1, the on-chip program which is selected by fpcs or fecs is automatically downloaded in the on-chip ram area specified by ftdar. in order to set this bit to 1, the ram emulation mode must be canceled, h'a5 mu st be written to fkey, and this operation must be executed in the on-chip ram. dummy read of fccs must be executed twice immediately after setting this bit to 1. all interrupts must be disabled during download. this bit is cleared to 0 when download is completed. during program download initiated with this bit, particular processing which accompanies bank- switching of the program storage area is executed. before a download request, initialize the vbr contents to h'00000000. after download is completed, the vbr contents can be changed. 0: download of the program ming/erasing program is not requested. [clearing condition] ? when download is completed 1: download of the progr amming/erasing program is requested. [setting conditions] (when all of the following conditions are satisfied) ? not in ram emulation mode (the rams bit in ramer is cleared to 0) ? h'a5 is written to fkey ? setting of this bit is executed in the on-chip ram note: * this is a write-only bit. this bit is always read as 0. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1040 of 1340 rej09b0499-0200 (2) flash program code select register (fpcs) fpcs selects the programming program to be downloaded. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 0 ppvs 0 r/w 2 ? 0 r 1 ? 0 r bit bit name initial value r/w bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 ppvs 0 r/w program pulse verify selects the programming program to be downloaded. 0: programming program is not selected. [clearing condition] when transfer is completed 1: programming program is selected. (3) flash erase code select register (fecs) fecs selects the erasing program to be downloaded. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 0 epvb 0 r/w 2 ? 0 r 1 ? 0 r bit bit name initial value r/w bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 epvb 0 r/w erase pulse verify block selects the erasing program to be downloaded. 0: erasing program is not selected. [clearing condition] when transfer is completed 1: erasing program is selected. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1041 of 1340 rej09b0499-0200 (4) flash key code register (fkey) fkey is a register for software protection that enables to download the on-chip program and perform programming/erasure of the flash memory. 7 k7 0 r/w 6 k6 0 r/w 5 k5 0 r/w 4 k4 0 r/w 3 k3 0 r/w 0 k0 0 r/w 2 k2 0 r/w 1 k1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 4 3 2 1 0 k7 k6 k5 k4 k3 k2 k1 k0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w key code when h'a5 is written to fkey, writing to the sco bit in fccs is enabled. when a value other than h'a5 is written, the sco bit cannot be set to 1. therefore, the on-chip program cannot be downloaded to the on-chip ram. only when h'5a is written can programming/erasure of the flash memory be executed. when a value other than h'5a is written, even if the programming/erasing program is executed, progr amming/erasure cannot be performed. h'a5: writing to the sco bit is enabled. (the sco bit cannot be set to 1 when fkey is a value other than h'a5.) h'5a: programming/erasure of the flash memory is enabled. (when fkey is a value other than h'a5, the software protecti on state is entered.) h'00: initial value section 24 flash memory rev. 2.00 oct. 20, 2009 page 1042 of 1340 rej09b0499-0200 (5) flash mat select register (fmats) fmats selects the user mat or user boot mat. writing to fmats should be done when a program in the on-chip ram is being executed. 7 ms7 0/1 * r/w 6 ms6 0 r/w 5 ms5 0/1 * r/w 4 ms4 0 r/w 3 ms3 0/1 * r/w 0 ms0 0 r/w 2 ms2 0 r/w 1 ms1 0/1 * r/w bit bit name initial value r/w note: * this bit is set to 1 in user boot mode, otherwise cleared to 0. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 0/1 * 0 0/1 * 0 0/1 * 0 0/1 * 0 r/w r/w r/w r/w r/w r/w r/w r/w mat select the memory mats can be switched by writing a value to fmats. when h'aa is written to fmats, the user boot mat is selected. when a value other than h'aa is written, the user mat is selected. switch the mats following the memory mat switching procedure in section 24.11, switching between user mat and user boot mat. the user boot mat cannot be selected by fmats in user programming mode. the user boot mat can be selected in boot mode or programmer mode. h'aa: the user boot mat is selected. (the user mat is selected when fmats is a value other than h'aa.) (initial value when initiated in user boot mode.) h'00: the user mat is selected. (initial value when initiated in a mode except for user boot mode.) note: * this bit is set to 1 in user boot mode, otherwise cleared to 0. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1043 of 1340 rej09b0499-0200 (6) flash transfer destination address register (ftdar) ftdar specifies the start address of the on-chip ram at which to download an on-chip program. ftdar must be set before setting the sco bit in fccs to 1. 7 tder 0 r/w 6 tda6 0 r/w 5 tda5 0 r/w 4 tda4 0 r/w 3 tda3 0 r/w 0 tda0 0 r/w 2 tda2 0 r/w 1 tda1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 tder 0 r/w transfer destination address setting error this bit is set to 1 when an error has occurred in setting the start address specified by bits tda6 to tda0. a start address error is determined by whether the value set in bits tda6 to tda0 is within the range of h'00 to h'02 when download is executed by setting the sco bit in fccs to 1. make sure t hat this bit is cleared to 0 before setting the sco bit to 1 and the value specified by bits tda6 to tda0 should be within the range of h'00 to h'02. 0: the value specified by bits tda6 to tda0 is within the range. 1: the value specified by bits tda6 to tda0 is between h'03 and h'ff and down load has stopped. 6 5 4 3 2 1 0 tda6 tda5 tda4 tda3 tda2 tda1 tda0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w transfer destination address specifies the on-chip ram start address of the download destination. a value between h'00 and h'02, and up to 4 kbytes can be specified as the start address of the on-chip ram. h'00: h'ff9000 is specifi ed as the start address. h'01: h'ffa000 is specifi ed as the start address. h'02: h'ffb000 is specifi ed as the start address. h'03 to h'7f: setting prohibited. (specifying a value from h'03 to h'7f sets the tder bit to 1 and stops download of the on-chip program.) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1044 of 1340 rej09b0499-0200 24.7.2 programming/erasing interface parameters the programming/erasing interface parameters speci fy the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. these parameters use the general registers of the cpu (er0 and er1) or the on-chip ram area. the initial values of programming/erasing interface parameters are undefined at a reset or a transition to software standby mode. since registers of the cpu except for er0 and er1 are saved in the stack area during download of an on-chip program, initialization, programming, or erasing, allocate the stack area before performing these operations (the maximum stack size is 128 bytes). the return value of the processing result is written in r0. the programmi ng/erasing interface parameters are used in download control, initialization before programming or erasing, programming, and erasing. table 24.4 shows the usable parameters and target modes. the meaning of the bits in the flash pass and fail result parameter (fpfr) varies in in itialization, programming, and erasure. table 24.4 parameters and target modes parameter download initialization programming erasure r/w initial value allocation dpfr o ? ? ? r/w undefined on-chip ram * fpfr o o o o r/w undefined r0l of cpu fpefeq ? o ? ? r/w undefined er0 of cpu fmpar ? ? o ? r/w undefined er1 of cpu fmpdr ? ? o ? r/w undefined er0 of cpu febs ? ? ? o r/w undefined er0 of cpu note: * a single byte of the start address of the on-chip ram specified by ftdar download control: the on-chip program is automatically downloaded by setting the sco bit in fccs to 1. the on-chip ram area to download th e on-chip program is th e 4-kbyte area starting from the start address specified by ftdar. download is set by the programming/e rasing interface registers, and the download pass and fail result parameter (dpfr) indicates the return value. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1045 of 1340 rej09b0499-0200 initialization before programming/erasure: the on-chip program includes the initialization program. a pulse with the specified period must be applied when programming or erasing. the specified pulse width is made by the method in which wait loop is configured by the cpu instruction. accordingly, the operating frequency of the cpu must be set. the initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings. programming: when the flash memory is programmed , the start address of the programming destination on the user mat and the program data must be passed to the programming program. the start address of the programming destination on the user mat must be stored in general register er1. this parameter is called the flas h multipurpose address ar ea parameter (fmpar). the program data is always in 128-byte units. when the program data does not satisfy 128 bytes, 128-byte program data is prepared by filling th e dummy code (h'ff). the boundary of the start address of the programming destination on the user mat is aligned at an address where the lower eight bits (a7 to a0) are h'00 or h'80. the program data for the user mat must be prep ared in consecutive areas. the program data must be in a consecutive space which can be accessed using the mov.b in struction of the cpu and is not in the flash memory space. the start address of the area that stores the data to be written in the user mat must be set in general register er0. this parameter is called the flash multipurpose data destination area parameter (fmpdr). for details on the programming procedure, see section 24.8.3, user programming mode. erasure: when the flash memory is erased, the eras e block number on the user mat must be passed to the erasing program which is downloaded. the erase block number on the user mat must be set in general register er0. this parameter is called the flash erase block select parameter (febs). one block is selected from the block numbers of 0 to 19 as the erase block number. for details on the erasing procedure, s ee section 24.8.3, user programming mode. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1046 of 1340 rej09b0499-0200 (1) download pass and fail result parameter (dpfr: single byte of start address in on- chip ram specified by ftdar) dpfr indicates the return value of the download result. the dpfr value is used to determine the download result. 7 ? 6 ? 5 ? 4 ? 3 ? 0 sf 2 ss 1 fk bit bit name bit bit name initial value r/w description 7 to 3 ? ? ? unused these bits return 0. 2 ss ? r/w source select error detect only one type can be specified for the on-chip program which can be downloaded. when the program to be downloaded is not selected, more than two types of programs are selected, or a program which is not mapped is selected, an error occurs. 0: download program selection is normal 1: download program selection is abnormal 1 fk ? r/w flash key register error detect checks the fkey value (h'a5) and returns the result. 0: fkey setting is normal (h'a5) 1: fkey setting is abnormal (value other than h'a5) 0 sf ? r/w success/fail returns the download result. reads back the program downloaded to the on-chip ram and determines whether it has been transferred to the on-chip ram. 0: download of the program has ended normally (no error) 1: download of the program has ended abnormally (error occurs) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1047 of 1340 rej09b0499-0200 (2) flash pass and fail parameter (fpfr: general register r0l of cpu) fpfr indicates the return values of the initia lization, programming, and erasure results. the meaning of the bits in fpfr varies depending on the processing. (a) initialization before programming/erasure fpfr indicates the return value of the initialization result. 7 ? 6 ? 5 ? 4 ? 3 ? 0 sf 2 ? 1 fq bit bit name bit bit name initial value r/w description 7 to 2 ? ? ? unused these bits return 0. 1 fq ? r/w frequency error detect compares the specified cp u operating frequency with the operating frequencies supported by this lsi, and returns the result. 0: setting of operating frequency is normal 1: setting of operating frequency is abnormal 0 sf ? r/w success/fail returns the initialization result. 0: initialization has ended normally (no error) 1: initialization has ended abnormally (error occurs) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1048 of 1340 rej09b0499-0200 (b) programming fpfr indicates the return valu e of the programming result. 7 ? 6 md 5 ee 4 fk 3 ? 0 sf 2 wd 1 wa bit bit name bit bit name initial value r/w description 7 ? ? ? unused returns 0. 6 md ? r/w programming mode related setting error detect detects the error protection state and returns the result. when the error protection state is entered, this bit is set to 1. whether the error prot ection state is entered or not can be confirmed with the fler bit in fccs. for conditions to enter the error protection state, see section 24.9.3, error protection. 0: normal operation (fler = 0) 1: error protection state, and programming cannot be performed (fler = 1) 5 ee ? r/w programming execution error detect writes 1 to this bit when t he specified data could not be written because the user mat was not erased. if this bit is set to 1, there is a high possibility that the user mat has been written to partially. in this case, after removing the error factor, erase the user mat. if fmats is set to h'aa and the user boot mat is selected, an error occurs when programming is performed. in this case, both the user mat and user boot mat have not been written to. programming the user boot mat should be performed in boot mode or programmer mode. 0: programming has ended normally 1: programming has ended abnormally (programming result is not guaranteed) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1049 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 fk ? r/w flash key register error detect checks the fkey value (h'5a) before programming starts, and returns the result. 0: fkey setting is normal (h'5a) 1: fkey setting is abnormal (value other than h'5a) 3 ? ? ? unused returns 0. 2 wd ? r/w write data address detect when an address not in the flash memory area is specified as the start addres s of the storage destination for the program data, an error occurs. 0: setting of the start addres s of the storage destination for the program data is normal 1: setting of the start addres s of the storage destination for the program data is abnormal 1 wa ? r/w write address error detect when the following items are specified as the start address of the programming destination, an error occurs. ? an area other than flash memory ? the specified address is not aligned with the 128- byte boundary (lower eight bits of the address are other than h'00 and h'80) 0: setting of the start address of the programming destination is normal 1: setting of the start address of the programming destination is abnormal 0 sf ? r/w success/fail returns the programming result. 0: programming has ended normally (no error) 1: programming has ended abnormally (error occurs) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1050 of 1340 rej09b0499-0200 (c) erasure fpfr indicates the return value of the erasure result. 7 ? 6 md 5 ee 4 fk 3 eb 0 sf 2 ? 1 ? bit bit name bit bit name initial value r/w description 7 ? ? ? unused returns 0. 6 md ? r/w erasure mode related setting error detect detects the error protection state and returns the result. when the error protection state is entered, this bit is set to 1. whether the error prot ection state is entered or not can be confirmed with the fler bit in fccs. for conditions to enter the error protection state, see section 24.9.3, error protection. 0: normal operation (fler = 0) 1: error protection state, and programming cannot be performed (fler = 1) 5 ee ? r/w erasure execution error detect returns 1 when the user mat could not be erased or when the flash memory related register settings are partially changed. if this bit is set to 1, there is a high possibility that the user mat has been erased partially. in this case, afte r removing the error factor, erase the user mat. if fmats is set to h'aa and the user boot mat is selected, an error occurs when erasure is performed. in this case, both the user mat and user boot mat have not been erased. erasing of the user boot mat should be performed in boot mode or programmer mode. 0: erasure has ended normally 1: erasure has ended abnormally section 24 flash memory rev. 2.00 oct. 20, 2009 page 1051 of 1340 rej09b0499-0200 bit bit name initial value r/w description 4 fk ? r/w flash key register error detect checks the fkey value (h'5a) before erasure starts, and returns the result. 0: fkey setting is normal (h'5a) 1: fkey setting is abnormal (value other than h'5a) 3 eb ? r/w erase block select error detect checks whether the specified erase block number is in the block range of the user mat, and returns the result. 0: setting of erase block number is normal 1: setting of erase block number is abnormal 2, 1 ? ? ? unused these bits return 0. 0 sf ? r/w success/fail indicates the erasure result. 0: erasure has ended normally (no error) 1: erasure has ended abnormally (error occurs) (3) flash program/erase frequency parameter (fpefeq: general register er0 of cpu) fpefeq sets the operating frequency of the cpu. the operating frequency available in this lsi ranges from 8 mhz to 50 mhz. 31 ? 30 ? 29 ? 28 ? 27 ? 24 ? 26 ? 25 ? bit bit name 23 ? 22 ? 21 ? 20 ? 19 ? 16 ? 18 ? 17 ? bit bit name 15 f15 14 f14 13 f13 12 f12 11 f11 8 f8 10 f10 9 f9 bit bit name 7 f7 6 f6 5 f5 4 f4 3 f3 0 f0 2 f2 1 f1 bit bit name section 24 flash memory rev. 2.00 oct. 20, 2009 page 1052 of 1340 rej09b0499-0200 bit bit name initial value r/w description 31 to 16 ? ? ? unused these bits should be cleared to 0. 15 to 0 f15 to f0 ? r/w frequency set these bits set the operating frequency of the cpu. when the pll multiplication function is used, set the multiplied frequency. the setting value must be calculated as follows: 1. the operating frequency shown in mhz units must be rounded in a number of three decimal places and be shown in a number of two decimal places. 2. the value multiplied by 100 is converted to the binary digit and is written to fpefeq (general register er0). for example, when the oper ating frequency of the cpu is 35.000 mhz, the value is as follows: 1. the number of three decim al places of 35.000 is rounded. 2. the formula of 35.00 100 = 3500 is converted to the binary digit and b'0000 1101 1010 1100 (h'0dac) is set to er0. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1053 of 1340 rej09b0499-0200 (4) flash multipurpose address area paramet er (fmpar: general register er1 of cpu) fmpar stores the start address of the programming destination on the user mat. when an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. the error occurrence is indicated by the wa bit in fpfr. 31 moa31 30 moa30 29 moa29 28 moa28 27 moa27 24 moa24 26 moa26 25 moa25 23 moa23 22 moa22 21 moa21 20 moa20 19 moa19 16 moa16 18 moa18 17 moa17 15 moa15 14 moa14 13 moa13 12 moa12 11 moa11 8 moa8 10 moa10 9 moa9 7 moa7 6 moa6 5 moa5 4 moa4 3 moa3 0 moa0 2 moa2 1 moa1 bit bit name bit bit name bit bit name bit bit name bit bit name initial value r/w description 31 to 0 moa31 to moa0 ? r/w these bits store the st art address of the programming destination on the user mat. consecutive 128-byte programming is executed star ting from the specified start address of the user mat. therefore, the specified start address of the program ming destination becomes a 128-byte boundary, and moa6 to moa0 are always cleared to 0. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1054 of 1340 rej09b0499-0200 (5) flash multipurpose data destination pa rameter (fmpdr: general register er0 of cpu) fmpdr stores the start address in the area which st ores the data to be programmed in the user mat. when the storage destination for the program data is in flash memory, an error occurs. the error occurrence is indicated by the wd bit in fpfr. 31 mod31 30 mod30 29 mod29 28 mod28 27 mod27 24 mod24 26 mod26 25 mod25 23 mod23 22 mod22 21 mod21 20 mod20 19 mod19 16 mod16 18 mod18 17 mod17 15 mod15 14 mod14 13 mod13 12 mod12 11 mod11 8 mod8 10 mod10 9 mod9 7 mod7 6 mod6 5 mod5 4 mod4 3 mod3 0 mod0 2 mod2 1 mod1 bit bit name bit bit name bit bit name bit bit name bit bit name initial value r/w description 31 to 0 mod31 to mod0 ? r/w these bits store the st art address of the area which stores the program data for the user mat. consecutive 128-byte data is programmed to the user mat starting from the specified start address. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1055 of 1340 rej09b0499-0200 (6) flash erase block select parameter (febs: general register er0 of cpu) ? h8sx/1652 febs specifies the erase block number. settable values range from 0 to 13 (h'0000 to h'000d). a value of 0 corresponds to block eb0 and a value of 13 corresponds to block eb13. an error occurs when a value other than 0 to 13 is set. ? h8sx/1655 febs specifies the erase block number. settable values range from 0 to 15 (h'0000 to h'000f). a value of 0 corresponds to block eb0 and a value of 15 corresponds to block eb15. an error occurs when a value other than 0 to 15 is set. bit bit name initial value r/w bit bit name initial value r/w bit bit name initial value r/w 7 ? r/w 6 ? r/w 5 ? r/w 4 ? r/w 3 ? r/w 0 ? r/w 2 ? r/w 1 ? r/w bit bit name initial value r/w 15 ? r/w 14 ? r/w 13 ? r/w 12 ? r/w 11 ? r/w 8 ? r/w 10 ? r/w 9 ? r/w 23 ? r/w 22 ? r/w 21 ? r/w 20 ? r/w 19 ? r/w 16 ? r/w 18 ? r/w 17 ? r/w 31 ? r/w 30 ? r/w 29 ? r/w 28 ? r/w 27 ? r/w 24 ? r/w 26 ? r/w 25 ? r/w section 24 flash memory rev. 2.00 oct. 20, 2009 page 1056 of 1340 rej09b0499-0200 24.7.3 ram emulation register (ramer) ramer specifies the user mat area overlaid w ith part of the on-chip ram (h'ffa000 to h'ffafff) when performing emulation of programming the user mat. ramer should be set in user mode or user programming mode. to ensure dependable emulation, the memory mat to be emulated must not be accessed immediately after changing the ramer contents. when accessed at such a timing, correct operation is not guaranteed. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 rams 0 r/w 0 ram0 0 r/w 2 ram2 0 r/w 1 ram1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 to 4 ? 0 r reserved these are read-only bits and cannot be modified. 3 rams 0 r/w ram select selects the function which emulates the flash memory using the on-chip ram. 0: disables ram emulation function 1: enables ram emulation function (all blocks of the user mat are protected against programming and erasing) 2 1 0 ram2 ram1 ram0 0 0 0 r/w r/w r/w flash memory area select these bits select the user mat area overlaid with the on-chip ram when rams = 1. the following areas correspond to the 4-kbyte erase blocks. 000: h'000000 to h'000fff (eb0) 001: h'001000 to h'001fff (eb1) 010: h'002000 to h'002fff (eb2) 011: h'003000 to h'003fff (eb3) 100: h'004000 to h'004fff (eb4) 101: h'005000 to h'005fff (eb5) 110: h'006000 to h'006fff (eb6) 111: h'007000 to h'007fff (eb7) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1057 of 1340 rej09b0499-0200 24.8 on-board programming mode when the mode pins (md0, md1, and md2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. on-board programming mode has four operating modes: user boot mode, sci boot mode and usb boot mode, which are selected by pm2 setting, and user programming mode. table 24.5 shows the pin setting for each operatin g mode. for details on the state transition of each operating mode for flash memory, see figure 24.2. table 24.5 on-board prog ramming mode setting mode setting emle md2 md1 md0 pm2 user boot mode 0 0 0 1 ? sci boot mode 0 0 1 0 0 usb boot mode 0 0 1 0 1 user programming mode 0 1 1 0 ? 0 1 1 1 ? 24.8.1 sci boot mode sci boot mode executes programming/erasing of the user mat by means of the control command and program data transmitted from the externally connected host via the on-chip sci_4. in sci boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. the serial communication mode is set to asynchronous mode. the system configuration in sci boot mode is shown in figure 24.6. interrupts are ignored in sci boot mode. configure the user system so that interrupts do not occur. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1058 of 1340 rej09b0499-0200 rxd4 t xd4 software for analyzing control commands (on-chip) flash memory on-chip ram sci_4 this lsi pm2 md2 to md0 0 010 host programming tool and program data control command, program data response figure 24.6 system configuration in sci boot mode (1) serial interface setting by host the sci_4 is set to asynchronous mode, and the seri al transmit/receive format is set to 8-bit data, one stop bit, and no parity. when a transition to sci boot mode is made, the boot program embedded in this lsi is initiated. when the boot program is initiated, this lsi m easures the low period of asynchronous serial communication data (h'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the sci_4 to match that of the host. when bit rate adjustment is completed, this lsi transmits 1 byte of h'00 to the host as the bit adjustment end sign. when the ho st receives this bit adjustment end sign normally, it transmits 1 byte of h'55 to this lsi. when reception is not executed normally, initiate boot mode again. the bit rate may not be adjusted within the allowable range depending on the combination of the bit rate of the host and the system clock frequency of th is lsi. therefore, the tr ansfer bit rate of the host and the system clock frequency of this lsi must be as shown in table 24.6. d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit measure low period (9 bits) (data is h'00) high period of at least 1 bit figure 24.7 automatic-bit- rate adjustment operation section 24 flash memory rev. 2.00 oct. 20, 2009 page 1059 of 1340 rej09b0499-0200 table 24.6 system clock frequency for automatic-bit-rate adjustment bit rate of host system clock frequency of this lsi 9,600 bps 8 to 18 mhz 19,200 bps 8 to 18 mhz (2) state transition diagram the state transition after sci boot mode is initiated is shown in figure 24.8. wait for inquiry setting command wait for programming/erasing command bit rate adjustment processing of read/check command boot mode initiation (reset by boot mode) h'00, ..., h'00 reception h'00 transmission (adjustment completed) (bit rate adjustment) processing of inquiry setting command all user mat and user boot mat erasure wait for program data wait for erase-block data read/check command reception command response (erasure selection command reception) (program data transmission) (erasure selection command reception) (programming completion) (erase-block specification) (erasure completion) inquiry command reception h'55 reception inquiry command response 1. 2. 3. 4. figure 24.8 sci boot mode state transition diagram section 24 flash memory rev. 2.00 oct. 20, 2009 page 1060 of 1340 rej09b0499-0200 1. after sci boot mode is initiated, the bit rate of the sci_4 is adjusted with that of the host. 2. inquiry information about the size, configuration, start address, and support status of the user mat is transmitted to the host. 3. after inquiries have finished, all user ma t and user boot mat are automatically erased. 4. when the program preparation notice is receiv ed, the state of waiting for program data is entered. the start address of the programming destination and program data must be transmitted after the programming command is tr ansmitted. when programming is finished, the start address of the programming destinati on must be set to h'ffffffff and transmitted. then the state of waiting for program data is returned to the state of waiting for programming/erasing command. when the erasure preparation notice is received, the state of waiting for erase block data is entered. the erase block number must be transmitted after the erasing command is transmitted. wh en the erasure is finished, th e erase block number must be set to h'ff and transmitted. then the state of waiting for erase block data is returned to the state of waiting for programming/erasing command. erasure must be executed when the specified block is programmed without a reset st art after programming is executed in sci boot mode. when programming can be executed by only one operation, all blocks are erased before entering the state of waiting for programming/ erasing command or another command. thus, in this case, the erasing operation is not required. the commands other than the programming/erasing command perform sum check, blank check (erasure check), and memory read of the user mat/user boot mat and acquisition of current status information. memory read of the user mat/user boot mat can only read the data programmed after all user mat/user boot mat has automatically been erased. no other data can be read. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1061 of 1340 rej09b0499-0200 24.8.2 usb boot mode usb boot mode executes programming/erasing of the user mat by means of the control command and program data transmitted from th e externally connected host via the usb. in usb boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. the system configuration in usb boot mode is shown in figure 24.9. interrupts are ignored in usb boot mode. configure the user system so that interrupts do not occur. host or self-power hub programming tool and program data software for analyzing control commands (on-chip) this lsi flash memory on-chip ram usb pm2 md3 to md0 pm4 1 0010 pm3 0: self power setting 1: bus power setting vbus usb+ usb- rs data transmission/ reception rs 1.5 k figure 24.9 system config uration in usb boot mode section 24 flash memory rev. 2.00 oct. 20, 2009 page 1062 of 1340 rej09b0499-0200 (1) features ? bus power mode and self power mode are selectable. ? the pm4 pin supports the d+ pull-up control connection. ? for enumeration information, refer to table 24.7. table 24.7 enumeration information usb standard ver.2.0 (full speed) transfer mode transfer mode control (in, out), bulk (in, out) for self power mode (pm3 = 0) 100 ma maximum power consumption for bus power mode (pm3 = 1) 500 ma endpoint configuration ep0 control (in out) 8 bytes configuration 1 interfacenumber0 alternatesetting0 ep1 bulk (out) 64 bytes ep2 bulk (in) 64 bytes section 24 flash memory rev. 2.00 oct. 20, 2009 page 1063 of 1340 rej09b0499-0200 (2) state transition diagram the state transition after usb boot mode is initiated is shown in figure 24.10. boot mode initiation (reset by boot mode) all user mat erasure enumeration inquiry command reception inquiry command response h'55 reception processing of inquiry setting command wait for inquiry setting command read/check command reception command response (programming completion) (program selection command reception) (erasu re completion) (erasure selec tion c ommand reception) (program data transmission) processing of read/check command wait for inquiry programming/erasing command wait for inquiry programming/erasing command wait for inquiry programming/erasing command 1. 2. 3. 4. (erase-block specification) figure 24.10 usb boot mode state transition diagram section 24 flash memory rev. 2.00 oct. 20, 2009 page 1064 of 1340 rej09b0499-0200 1. after a transition to the usb boot mode is made, the boot program embedded in this lsi is initialized. this lsi performs enumeration to the host after the usb boot program is initialized. 2. inquiry information about the size, configuration, start address, and support status of the user mat is transmitted to the host. 3. after inquiries have finished, a ll user mat are automatically erased. 4. after all user mat are auto matically erased, the state of waiting for programming/erasing command is entered. when the programming comman d is received, the stat e shifts to the state of waiting for programming data. the same applie s to erasing. in addition to the commands for programming/erasing, there are commands for pe rforming sum check, blank check (erasure check), and memory read of th e user mat, and acquiring the current status information. (3) notes on usb boot mode execution ? the clock of 48 mhz needs to be supplied to the usb module. set the external clock frequency and clock pulse generator so as to supply 48 mhz as the clock for the usb (cku). for details, refer to section 26, clock pulse generator. ? use the pm4 pin for the d+ pull-up control connection. ? for the stable supply of the power during th e flash memory programm ing and erasing, the cable should not be connected via the bus powered hub. ? if the bus powered hub is disconnected during the flash memory programming and erasing, permanent damage to the lsi may result. ? if the usb bus in the bus power mode enters the suspend mode, this does not make the transition to the software standby mode in the power-down state. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1065 of 1340 rej09b0499-0200 24.8.3 user programming mode programming/erasure of the user mat is executed by downloading an on-chip program. the user boot mat cannot be programmed/erased in user programming mode. the programming/erasing flow is shown in figure 24.11. since high voltage is applied to the internal flash memory during programming/erasure, a transition to the reset state or hardware standby mode must not be made during programming/erasure. a transition to the reset state or hardware standby mode during programming/erasure may damage the flash memory. if a reset is input, the reset must be released after the reset input period (period of res = 0) of at least 100 s. when programming, program data is prepared programming/erasing procedure program is transferred to the on-chip ram and executed programming/erasing start programming/erasing end exit ram emulation mode beforehand. download is not allowed in emulation mode. when the program data is adjusted in emulation mode, select the download destination specified by ftdar carefully. make sure that the download area does not overlap the emulation area. programming/erasing is executed only in the on-chip ram. after programming/erasing is finished, protect the flash memory by the hardware protection. 1. 2. 3. 4. figure 24.11 programming/erasing flow section 24 flash memory rev. 2.00 oct. 20, 2009 page 1066 of 1340 rej09b0499-0200 (1) on-chip ram address map when programming/erasure is executed parts of the procedure program that is made by the user, like download request, programming/erasure procedure, and decision of the result, must be executed in the on-chip ram. since the on-chip program to be downloaded is embedded in the on-chip ram, make sure the on- chip program and procedure program do not overlap. figure 24.12 shows the area of the on-chip program to be downloaded. h'ffbfff programming/erasing program entry system use area (15 bytes) dpfr (return value: 1 byte) ftdar setting ftdar setting + 32 bytes ftdar setting + 16 bytes initialization program entry initialization + programming program or initialization + erasing program ram emulation area or area that can be used by user area that can be used by user area to be downloaded (size: 4 kbytes) unusable area during programming/erasing ftdar setting + 4 kbytes figure 24.12 ram map when pr ogramming/erasure is executed section 24 flash memory rev. 2.00 oct. 20, 2009 page 1067 of 1340 rej09b0499-0200 (2) programming procedure in user programming mode the procedures for download of the on-chip program, initialization, and programming are shown in figure 24.13. select on-chip program to be downloaded and specify download destination by ftdar set fkey to h'a5 set sco to 1 after initializing vbr and execute download dpfr = 0? yes no download error processing set the fpefeq parameter yes end programming procedure program fpfr = 0? no disable interrupts and bus master operation other than cpu clear fkey to 0 programming jsr ftdar setting + 16 yes fpfr = 0? no clear fkey and programming error processing yes required data programming is completed? no set fkey to h'5a clear fkey to 0 1. 2. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 3. download initialization programming initialization jsr ftdar setting + 32 initialization error processing set parameters to er1 and er0 (fmpar and fmpdr) 1 1 start programming procedure program figure 24.13 programming proc edure in user programming mode section 24 flash memory rev. 2.00 oct. 20, 2009 page 1068 of 1340 rej09b0499-0200 the procedure program must be executed in an area other than the flash memory to be programmed. setting the sco bit in fccs to 1 to request download must be executed in the on- chip ram. the area that can be executed in the steps of the procedure program (on-chip ram, user mat, and external space) is shown in section 24.8.5, on-chip program and storable area for program data. the following description assumes that the area to be programmed on the user mat is erased and that program data is prepared in the consecutive area. the program data for one programming operation is always 128 bytes. when the program data exceeds 128 bytes, the start addres s of the programming destination and program data parameters are updated in 128-byte units and programming is repeated. when the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data. if the invalid data to be added is h'ff, the program processing time can be shortened. 1. select the on-chip program to be downloaded and the download destin ation. when the ppvs bit in fpcs is set to 1, the programming program is selected. several programming/erasing programs cannot be selected at one time. if seve ral programs are selected , a download error is returned to the ss bit in the dpfr parameter. the on-chip ram start address of the download destination is specified by ftdar. 2. write h'a5 in fkey. if h'a5 is not written to fkey, the sco bit in fccs cannot be set to 1 to request download of the on-chip program. 3. after initializing vbr to h'00000000, set the sco bit to 1 to execute download. to set the sco bit to 1, all of the following conditions must be satisfied. ? ram emulation mode has been canceled. ? h'a5 is written to fkey. ? setting the sco bit is executed in the on-chip ram. when the sco bit is set to 1, download is started automatically. since the sco bit is cleared to 0 when the procedure program is resumed, the sco bit cannot be confirmed to be 1 in the procedure program. the download result can be confirmed by the return value of the dpfr parameter. to prevent incorrect decision, before setting the sco bit to 1, set one byte of the on-chip ram start address specified by ftdar, which becomes the dpfr parameter, to a value other than the return value (e.g. h'ff). since particular processing that is accompanied by bank switching as described below is performed when download is executed, initialize the vbr contents to h'00000000. dummy read of fccs must be performed twice immediately after the sco bit is set to 1. ? the user-mat space is switched to the on-chip program storage area. ? after the program to be downloaded and th e on-chip ram start ad dress specified by ftdar are checked, they are transferred to the on-chip ram. ? fpcs, fecs, and the sco bit in fccs are cleared to 0. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1069 of 1340 rej09b0499-0200 ? the return value is set in the dpfr parameter. ? after the on-chip program storage area is retu rned to the user-mat space, the procedure program is resumed. after that, vbr can be set again. ? the values of general registers of the cpu are held. ? during download, no interrupts can be accepted. however, since the in terrupt requests are held, when the procedure program is re sumed, the interrup ts are requested. ? to hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed. ? allocate a stack area of 128 by tes at the maximum in the on-chip ram before setting the sco bit to 1. ? if access to the flash memory is requested by the dmac or dtc during download, the operation cannot be guaranteed. make sure th at an access request by the dmac or dtc is not generated. 4. fkey is cleared to h'00 for protection. 5. the download result must be confirmed by the value of the dpfr parameter. check the value of the dpfr parameter (one byte of start address of the download destination specified by ftdar). if the value of the dpfr parameter is h'00, download has been performed normally. if the value is not h'00, the source that caused do wnload to fail can be investigated by the description below. ? if the value of the dpfr parameter is the same as that before downloading, the setting of the start address of the download destination in ftdar may be abnormal. in this case, confirm the setting of the tder bit in ftdar. ? if the value of the dpfr parameter is different from that before down loading, check the ss bit or fk bit in the dpfr parameter to confirm the download program selection and fkey setting, respectively. 6. the operating frequency of the cpu is set in the fpefeq parameter for initialization. the settable operating frequency of the fpefeq parameter ranges from 8 to 50 mhz. when the frequency is set otherwise, an error is return ed to the fpfr parameter of the initialization program and initialization is not performed. for details on setting the frequency, see section 24.7.2 (3), flash program/erase frequency parameter (fpefeq: general register er0 of cpu). section 24 flash memory rev. 2.00 oct. 20, 2009 page 1070 of 1340 rej09b0499-0200 7. initialization is executed. the initialization program is downloaded together with the programming program to the on-chip ram. the entry point of the initialization program is at the address which is 32 bytes after #dltop (start address of the download destination specified by ftdar). call the subroutine to execute initialization by using the following steps. mov.l #dltop+32,er2 ; set entry address to er2 jsr @er2 ; call initialization routine nop ? the general registers other than er0 and er1 are held in the initialization program. ? r0l is a return value of the fpfr parameter. ? since the stack area is used in the initialization program, a stack area of 128 bytes at the maximum must be allocated in ram. ? interrupts can be accepted during execution of the initialization program. make sure the program storage area and stack area in the on-chip ram and register values are not overwritten. 8. the return value in the initialization pr ogram, the fpfr parameter is determined. 9. all interrupts and the use of a bus master other than the cpu are disabled during programming/erasure. the speci fied voltage is applied fo r the specified time when programming or erasing. if interrupts occur or the bus mastership is moved to other than the cpu during programming/erasure, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged. therefore, interrupts are disabled by setting bit 7 (i bit) in the condition code register (ccr) to b'1 in interrupt control mode 0 and by setting bits 2 to 0 (i2 to i0 bits) in the extend register (exr) to b'111 in interrupt control mode 2. accordingly, interrupts other than nmi are held and not executed. conf igure the user system so that nmi interrupts do not occur. the interrupts that are held must be executed after all programming completes. when the bus mastership is moved to other than the cpu, such as to the dmac or dtc, the error protection state is entered. therefore, make sure the dmac does not acquire the bus. 10. fkey must be set to h'5a and the user mat must be prepared for programming. 11. the parameters required for programming are set. the start address of the programming destination on the user mat (fmpar parameter) is set in general register er1. the start address of the program data storage area (fmpdr parameter) is set in general register er0. ? example of fmpar parameter setting: when an address other than one in the user mat area is specified for the star t address of the programming destination, even if the programming program is executed, programming is not executed and an error is returned to the fpfr parameter. since the program data for one programming operation is 128 bytes, the lower eight bits of the address must be h'00 or h'80 to be aligned with the 128-byte boundary. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1071 of 1340 rej09b0499-0200 ? example of fmpdr parameter setting: when the storage destination for the program data is flash memory, even if the programming routine is executed, programming is not executed and an error is return ed to the fpfr parameter. in this case, the program data must be transferred to the on-chip ram and then programming must be executed. 12. programming is executed. the entry point of the programming program is at the address which is 16 bytes after #dltop (start address of the download destination specified by ftdar). call the subroutine to execute programming by using the following steps. mov.l #dltop+16,er2 ; set entry address to er2 jsr @er2 ; call programming routine nop ? the general registers other than er0 and er1 are held in the programming program. ? r0l is a return value of the fpfr parameter. ? since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in ram. 13. the return value in the programming program, the fpfr parameter is determined. 14. determine whether programming of the necessary data has finished. if more than 128 bytes of data are to be programmed, update the fmpar and fmpdr parameters in 128-byte units, and repeat steps 11 to 14. increment the programming destination address by 128 bytes and update the programming data pointer correctly. if an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. 15. after programming finishes, clear fkey and specify software protection. if this lsi is restarted by a reset immediately after programming has finished, secure the reset input period (period of res = 0) of at least 100 s. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1072 of 1340 rej09b0499-0200 (3) erasing procedure in user programming mode the procedures for download of the on-chip program, initialization, and erasing are shown in figure 24.14. set fkey to h'a5 set sco to 1 after initializing vbr and execute download dpfr = 0? yes no download error processing set the fpefeq parameter yes end erasing procedure program fpfr = 0 ? no initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set febs parameter yes fpfr = 0? no clear fkey and erasing error processing yes required block erasing is completed? no set fkey to h'5a clear fkey to 0 1. 2. 3. 4. 5. 6. download initialization erasing initialization jsr ftdar setting + 32 erasing jsr ftdar setting + 16 select on-chip program to be downloaded and specify download destination by ftdar start erasing procedure program 1 1 figure 24.14 erasing procedu re in user programming mode section 24 flash memory rev. 2.00 oct. 20, 2009 page 1073 of 1340 rej09b0499-0200 the procedure program must be executed in an area other than the user mat to be erased. setting the sco bit in fccs to 1 to request download must be executed in the on-chip ram. the area that can be executed in the steps of the procedur e program (on-chip ram, user mat, and external space) is shown in section 24.8 .5, on-chip program and storable area for program data. for the downloaded on-chip program area, see figure 24.12. one erasure processing erases one block. for details on block divisions, refer to figure 24.4. to erase two or more blocks, update the erase bloc k number and repeat the erasing processing for each block. 1. select the on-chip program to be downloaded and the download destination. when the epvb bit in fecs is set to 1, the programming program is selected. several programming/erasing programs cannot be selected at one time. if seve ral programs are selected , a download error is returned to the ss bit in the dpfr parameter. the on-chip ram start address of the download destination is specified by ftdar. for the procedures to be carried out after setting fkey, see section 24.8.3 (2), programming procedure in user programming mode. 2. set the febs parameter necessary for erasur e. set the erase block number (febs parameter) of the user mat in general register er0. if a value other than an erase block number of the user mat is set, no block is erased even thou gh the erasing program is executed, and an error is returned to the fpfr parameter. 3. erasure is executed. similar to as in programming, the entry point of the erasing program is at the address which is 16 bytes after #dltop (start address of the download destination specified by ftdar). call the subroutine to execute erasure by using the following steps. mov.l #dltop+16, er2 ; set entry address to er2 jsr @er2 ; call erasing routine nop ? the general registers other than er0 and er1 are held in the erasing program. ? r0l is a return value of the fpfr parameter. ? since the stack area is used in the erasin g program, a stack area of 128 bytes at the maximum must be allocated in ram. 4. the return value in the erasing prog ram, the fpfr parameter is determined. 5. determine whether erasure of the necessary blocks has finished. if more than one block is to be erased, update the febs parameter and repeat steps 2 to 5. 6. after erasure completes, clear fkey and specify software protection. if this lsi is restarted by a reset immediately after erasure has finished, secure the reset input period (period of res = 0) of at least 100 s. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1074 of 1340 rej09b0499-0200 (4) procedure of erasing, programming, and ram emulation in user programming mode by changing the on-chip ram st art address of the download des tination in ftdar, the erasing program and programming program can be downloaded to separate on-chip ram areas. figure 24.15 shows a repeating procedure of erasing, programming, and ram emulation. yes no erasing program download programming program download emulation/erasing/programming start procedure program initialize erasing program set ftdar to h'02 (specify download destination h'ffb000) download programming program initialize programming program end procedure program erase relevant block (execute erasing program) set fmpdr to h'ffa000 and program relevant block (execute programming program) confirm operation end ? set ftdar to h'00 (specify download destination to h'ff9000) download erasing program exit emulation mode make a transition to ram emulation mode and tuning parameters in on-chip ram 1 1 24.15 repeating procedure of erasing, programming, and ram emulation in user programming mode section 24 flash memory rev. 2.00 oct. 20, 2009 page 1075 of 1340 rej09b0499-0200 in figure 24.15, since ram emulation is performed, the erasing/programming program is downloaded to avoid the 4-kbyte on-chip ram area (h'ffa000 to h'ff afff). download and initialization are performed only once at the beginning. note the following when executing the procedure program. ? be careful not to overwrite data in the on-chip ram with overlay settings. in addition to the programming program area, erasing program ar ea, and ram emulation area, areas for the procedure programs, work area, and stack area are reserved in the on-chip ram. do not make settings that will overwrite data in these areas. ? be sure to initialize both the programming program and erasing program. when the fpefeq parameter is initialized, also initialize both the erasing program and programming program. initialization must be executed for both entry addr esses: #dltop (start address of download destination for erasing program) + 32 bytes, and #dltop (start address of download destination for programming program) + 32 bytes. 24.8.4 user boot mode branching to a programming/erasing program prepared by the user enables user boot mode which is a user-defined boot mode to be used. only the user mat can be programmed/erased in user boot mode. programming/erasure of the user boot mat is only enabled in boot mode or programmer mode. (1) initiation in user boot mode when the reset start is executed with the mode pins set to user boot mode, the built-in check routine runs and checks the user mat and user boot mat st ates. while the check routine is running, nmi and all other interrupts cannot be accepted. next, processi ng starts from the execution start address of the reset vector in the user boot mat. at this point, the user boot mat is selected (fmats = h'aa) as the execution memory mat. (2) user mat programming in user boot mode figure 24.16 shows the procedure for programming the user mat in user boot mode. the difference between the programming procedures in user programming mode and user boot mode is the memory mat switching as shown in figure 24.16. for programming the user mat in user boot mode, additional processing made by setting fmats is required: switching from the user boot mat to the user mat, and switching back to the user boot mat after programming completes. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1076 of 1340 rej09b0499-0200 set fkey to h'a5 dpfr = 0 ? yes no download error processing set the fpefeq parameter initialization jsr ftdar setting + 32 yes end programming procedure program fpfr = 0 ? no initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set parameter to er0 and er1 (fmpar and fmpdr) programming jsr ftdar setting + 16 yes fpfr = 0 ? no yes required data programming is completed? no set fkey to h'a5 clear fkey to 0 download initialization programming mat switchover mat switchover set fmats to value other than h'aa to select user mat set sco to 1 after initializing vbr and execute download clear fkey and programming error processing set fmats to h'aa to select user boot mat user-boot-mat selection state user-mat selection state user-boot-mat selection state note: the mat must be switched by fmats to perform the programming error processing in the user boot mat. start programming procedure program select on-chip program to be downloaded and specify download destination by ftdar 1 1 figure 24.16 procedu re for programming user ma t in user boot mode section 24 flash memory rev. 2.00 oct. 20, 2009 page 1077 of 1340 rej09b0499-0200 in user boot mode, though the user boot mat can be seen in the flash memory space, the user mat is hidden in the background. therefore, the user mat and user boot mat are switched while the user mat is being pr ogrammed. because the user boot mat is hidden while the user mat is being programmed, the procedure program mu st be executed in an area other than flash memory. after programming completes, switch the memory mats again to return to the first state. memory mat switching is enabled by setting fmats. however note that access to a memory mat is not allowed until memory mat switching is completed. during memory mat switching, the lsi is in an unstable state, e.g. if an interrupt occurs, from which memory mat the interrupt vector is read is undetermined. perform me mory mat switching in accordance with the description in section 24.11, switching between user mat and user boot mat. except for memory mat switching, the programming procedure is the same as that in user programming mode. the area that can be executed in the steps of the procedure program (on-chip ram, user mat, and external space) is shown in section 24.8.5, on-chip progra m and storable area for program data. (3) user mat erasing in user boot mode figure 24.17 shows the procedure for erasing the user mat in user boot mode. the difference between the erasing procedures in user programming mode and user boot mode is the memory mat switching as shown in figure 24.17. for erasing the user mat in user boot mode, additional processing made by setting fmats is required: switching from the user boot mat to the user mat, and switching back to the user boot mat after erasing completes. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1078 of 1340 rej09b0499-0200 yes no start erasing procedure program set fkey to h'a5 yes no download error processing set the fpefeq parameter end erasing procedure program fpfr = 0 ? initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set febs parameter yes no clear fkey and erasing error processing yes required block erasing is completed? no set fkey to h'a5 clear fkey to 0 download initialization erasing set fmats to value other than h'aa to select user mat set sco to 1 after initializing vbr and execute download set fmats to h'aa to select user boot mat user-boot-mat selection state user-mat selection state user-boot-mat selection state note: the mat must be switched by fmats to perform the erasing error processing in the user boot mat. mat switchover mat switchover dpfr = 0 ? initialization jsr ftdar setting + 32 erasing jsr ftdar setting + 16 fpfr = 0 ? select on-chip program to be downloaded and specify download destination by ftdar 1 1 figure 24.17 procedure for eras ing user mat in user boot mode section 24 flash memory rev. 2.00 oct. 20, 2009 page 1079 of 1340 rej09b0499-0200 memory mat switching is enabled by setting fmats. however note that access to a memory mat is not allowed until memory mat switching is completed. during memory mat switching, the lsi is in an unstable state, e.g. if an interrupt occurs, from which memory mat the interrupt vector is read is undetermined. perform me mory mat switching in accordance with the description in section 24.11, switching between user mat and user boot mat. except for memory mat switching, the erasing procedure is the same as that in user programming mode. the area that can be executed in the steps of the procedure program (on-chip ram, user mat, and external space) is shown in section 24.8.5, on-chip progra m and storable area for program data. 24.8.5 on-chip program and storable area for program data in the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip ram. however, they can be executed from part of the flash memory which is not to be programmed or erased as lo ng as the following conditions are satisfied. ? the on-chip program is downloaded to and executed in the on-chip ram specified by ftdar. therefore, this on-chip ra m area is not available for use. ? since the on-chip program uses a stack area, allocate 128 byte s at the maximum as a stack area. ? download requested by setting the sco bit in fccs to 1 should be executed from the on-chip ram because it will require switching of the memory mats. ? in an operating mode in which the external addr ess space is not accessible, such as single-chip mode, the required procedure programs, nmi handling vector table, and nmi handling routine should be transferred to the on-chip ram before programming/erasure starts (download result is determined). ? the flash memory is not acce ssible during programming/erasu re. programming/erasure is executed by the program downloaded to the on -chip ram. therefore, the procedure program that initiates operation, the nmi handling vector table, and the nmi handling routine should be stored in the on-chip ram other than the flash memory. ? after programming/erasure starts, access to the fl ash memory should be inhibited until fkey is cleared. the reset input state (period of res = 0) must be set to at least 100 s when the operating mode is changed and the reset start ex ecuted on completion of programming/erasure. transitions to the reset state are inhibited dur ing programming/erasure. when the reset signal is input, a reset input state (period of res = 0) of at least 100 s is needed before the reset signal is released. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1080 of 1340 rej09b0499-0200 ? switching of the memory mats by fmats should be needed when programming/erasure of the user mat is operated in user boot mode . the program which swit ches the memory mats should be executed from the on-chip ram. for details, see section 24.11, switching between user mat and user boot mat. make sure you know which memory mat is currently selected when switching them. ? when the program data storage area is within th e flash memory area, an error will occur even when the data stored is normal program data. therefore, the data should be transferred to the on-chip ram to place the address that the fmpd r parameter indicates in an area other than the flash memory. in consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory mats, as shown in tables 24.8 to 24.12. table 24.8 executable memory mat operating mode processing contents user progr amming mode user boot mode * programming see table 24.9 see table 24.11 erasing see table 24. 10 see table 24.12 note: * programming/erasure is possible to the user mat. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1081 of 1340 rej09b0499-0200 table 24.9 usable area for prog ramming in user programming mode storable/executable area selected mat item on-chip ram user mat user mat embedded program storage mat storage area for program data o * ? ? operation for selecting on-chip program to be downloaded o o o operation for writing h'a5 to fkey o o o execution of writing 1 to sco bit in fccs (download) o o operation for clearing fkey o o o decision of download result o o o operation for download error o o o operation for setting initialization parameter o o o execution of initialization o o decision of initialization result o o o operation for initiali zation error o o o nmi handling routine o o operation for disabling interrupts o o o operation for writing h'5a to fkey o o o operation for setting programming parameter o o execution of programming o o decision of programming result o o operation for programming error o o operation for clearing fkey o o note: * transferring the program data to the on-chip ram beforehand enables this area to be used. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1082 of 1340 rej09b0499-0200 table 24.10 usable area for er asure in user programming mode storable/executable area selected mat item on-chip ram user mat user mat embedded program storage mat operation for selecting on-chip program to be downloaded o o o operation for writing h'a5 to fkey o o o execution of writing 1 to sco bit in fccs (download) o o operation for clearing fkey o o o decision of download result o o o operation for download error o o o operation for setting initialization parameter o o o execution of initialization o o decision of initialization result o o o operation for initiali zation error o o o nmi handling routine o o operation for disabling interrupts o o o operation for writing h'5a to fkey o o o operation for setting erasure parameter o o execution of erasure o o decision of erasure result o o operation for erasure error o o operation for clearing fkey o o section 24 flash memory rev. 2.00 oct. 20, 2009 page 1083 of 1340 rej09b0499-0200 table 24.11 usable area for pr ogramming in user boot mode storable/executable area selected mat item on-chip ram user boot mat user mat user boot mat embedded program storage mat storage area for program data o * 1 ? ? ? operation for selecting on-chip program to be downloaded o o o operation for writing h'a5 to fkey o o o execution of writing 1 to sco bit in fccs (download) o o operation for clearing fkey o o o decision of download result o o o operation for download error o o o operation for setting initialization parameter o o o execution of initialization o o decision of initialization result o o o operation for initializa tion error o o o nmi handling routine o o operation for disabling interrupts o o o switching memory mats by fmats o o operation for writing h'5a to fkey o o operation for setting programming parameter o o execution of programming o o decision of programming result o o operation for programming error o * 2 o operation for clearing fkey o o switching memory mats by fmats o o notes: 1. transferring the program data to the on-chip ram beforehand enables this area to be used. 2. switching memory mats by fmats by a program in the on-chip ram enables this area to be used. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1084 of 1340 rej09b0499-0200 table 24.12 usable area for erasure in user boot mode storable/executable area selected mat item on-chip ram user boot mat user mat user boot mat embedded program storage mat operation for selecting on-chip program to be downloaded o o o operation for writing h'a5 to fkey o o o execution of writing 1 to sco bit in fccs (download) o o operation for clearing fkey o o o decision of download result o o o operation for download error o o o operation for setting initialization parameter o o o execution of initialization o o decision of initialization result o o o operation for initializa tion error o o o nmi handling routine o o operation for disabling interrupts o o o switching memory mats by fmats o o operation for writing h'5a to fkey o o operation for setting erasure parameter o o execution of erasure o o decision of erasure result o o operation for erasure error o * o operation for clearing fkey o o switching memory mats by fmats o o note: * switching memory mats by fmats by a program in the on-chip ram enables this area to be used. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1085 of 1340 rej09b0499-0200 24.9 protection there are three types of protection against the flash memory programming/erasure: hardware protection, software protection, and error protection. 24.9.1 hardware protection programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. in this state, download of an on-chip program and initialization are possible. however, programming or erasure of the user mat cannot be performed even if the programming/erasing program is initiated, and the error in programming /erasure is indicated by the fpfr parameter. table 24.13 hardware protection function to be protected item description download programming/ erasing reset protection ? the programming/erasing interface registers are initialized in the reset state (including a reset by the wdt) and the programming/erasing protection state is entered. ? the reset state will not be entered by a reset using the res pin unless the res pin is held low until oscillation has settled after a power is initially supplied. in the case of a reset during operation, hold the res pin low for the res pulse width given in the ac characteristics. if a reset is input during programming or erasure, data in the flash memory is not guaranteed. in this case, execute erasure and then execute programming again. o o section 24 flash memory rev. 2.00 oct. 20, 2009 page 1086 of 1340 rej09b0499-0200 24.9.2 software protection the software protection protects the flash memory against prog ramming/erasure by disabling download of the programming/erasing program, using the key code, and by the ramer setting. table 24.14 software protection function to be protected item description download programming/ erasing protection by sco bit the programming/erasing protection state is entered when the sco bit in fccs is cleared to 0 to disable download of the programming/erasing programs. o o protection by fkey the programming/erasing protection state is entered because download and programming/erasure are disabled unless the required key code is written in fkey. o o emulation protection the programming/erasing protection state is entered when the rams bit in the ram emulation register (ramer) is set to 1. o o 24.9.3 error protection error protection is a mechanism for aborting programming or erasure when a cpu runaway occurs or operations not according to the progra mming/erasing procedures are detected during programming/erasure of the flash memory. aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. if an error occurs during programming/erasure of the flash memory, the fler bit in fccs is set to 1 and the error protection state is entered. ? when an interrupt request, such as nm i, occurs during programming/erasure. ? when the flash memory is read from during programming/erasure (including a vector read or an instruction fetch). ? when a sleep instruction is executed (including software-standby mode) during programming/erasure. ? when a bus master other than the cpu, such as the dmac and dtc, obtains bus mastership during programming/erasure. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1087 of 1340 rej09b0499-0200 error protection is canceled by a re set. note that the reset should be released after the reset input period of at least 100 s has passed. since high voltages are applied during programming/erasure of the flash memory, some voltage may remain af ter the error protection state has been entered. for this reason, it is necessary to reduce the risk of damaging th e flash memory by extending the reset input period so that the charge is released. the state-transition diagram in figure 24.18 shows transitions to and from the error protection state. reset (hardware protection) programming/erasing mode error-protection mode error-protection mode (software standby) read disabled programming/erasing enabled fler = 0 read disabled programming/erasing disabled fler = 0 read enabled programming/erasing disabled fler = 1 read disabled programming/erasing disabled fler = 1 res = 0 error occurrence error occurred (software standby) res = 0 software standby mode cancel software standby mode res = 0 programming/erasing interface register is in its initial state. programming/erasing interface register is in its initial state. figure 24.18 transitions to error protection state section 24 flash memory rev. 2.00 oct. 20, 2009 page 1088 of 1340 rej09b0499-0200 24.10 flash memory emulation using ram for realtime emulation of the data written to the flash memory using the on-chip ram, the on- chip ram area can be overlaid with several flash memory blocks (user mat) using the ram emulation register (ramer). the overlaid area can be accessed from both the user mat ar ea specified by ramer and the overlaid ram area. the emulation can be performed in user mode and user programming mode. figure 24.19 shows an example of emulatin g realtime programming of the user mat. emulation program start set ramer write tuning data to overlaid ram area execute application program tuning ok? cancel setting in ramer program emulation block in user mat emulation program end ye s no figure 24.19 ram emulation flow section 24 flash memory rev. 2.00 oct. 20, 2009 page 1089 of 1340 rej09b0499-0200 figure 24.20 shows an example of overlaying flash memory block area eb0. this area can be accessed via both the on-chip ram and flash memory area. flash memory user mat eb8 to eb15 * 1 on-chip ram h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 notes: 1. eb8 to eb13 in the h8sx/1652. 2. h'05ffff in the h8sx/1652. h'7ffff * 2 h'ff6000 h'ffa000 h'ffafff h'ffbfff eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 figure 24.20 address map of overlaid ram area (h8sx/1655) the flash memory area that can be emulated is th e one area selected by bits ram2 to ram0 in ramer from among the eight blocks, eb0 to eb7, of the user mat. to overlay a part of the on-chip ram with block eb0 for realtime emulation, set the rams bit in ramer to 1 and bits ram2 to ram0 to b'000. for programming/erasing the user mat, the procedure programs including a download program of the on-chip program must be executed. at this time, the download area should be specified so that the overlaid ram area is not overwritten by downloading the on-chip program. since the area in which the tuned data is stored is overlaid with the download area when ftdar = h'01, the tuned data must be saved in an unused area beforehand. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1090 of 1340 rej09b0499-0200 figure 24.21 shows an example of the procedure to program the tuned data in block eb0 of the user mat. flash memory user mat eb8 to eb15 * 1 notes: 1. eb8 to eb13 in the h8sx/1652. 2. h'05ffff in the h8sx/1652. download area tuned data area area for programming/ erasing program etc. h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'7ffff * 2 specified by ftdar h'ffa000 h'ffb000 h'ffafff h'ffbfff eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 (1) exit ram emulation mode. (2) transfer user-created programming/erasing procedure program. (3) download the on-chip programming/erasing program to the area specified by ftdar. ftdar setting should avoid the tuned data area. (4) program after erasing, if necessary. figure 24.21 programming tuned data (h8sx/1655) 1. after tuning program data is completed, clear the rams bit in ramer to 0 to cancel the overlaid ram. 2. transfer the user-c reated procedure progra m to the on-chip ram. 3. start the procedure program and download the on-chip program to the on-chip ram. the start address of the download destination should be specified by ftdar so that the tuned data area does not overlay the download area. 4. when block eb0 of the user mat has not been erased, the programming program must be downloaded after block eb0 is erased. specify the tuned data saved in the fmpar and fmpdr parameters and then execute programming. note: setting the rams bit to 1 makes all the blocks of the user mat enter the programming/erasing protection state (emulation protection state) regardless of the setting of the ram2 to ram0 bits. under this condition, the on-chip program cannot be downloaded. when data is to be actually programmed and erased, clear the rams bit to 0. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1091 of 1340 rej09b0499-0200 24.11 switching between user mat and user boot mat it is possible to switch between the user mat and user boot mat. however, the following procedure is required because the start addresses of these mats are allocated to the same address. switching to the user boot mat disables programming and erasing. programming of the user boot mat should take place in boot mode or programmer mode. 1. memory mat switching by fmats should always be executed from the on-chip ram. 2. when accessing the memory mat immediat ely after switching the memory mats by fmats from the on-chip ram, similarly execute the nop instruction in the on-chip ram for eight times (this prevents access to the flash memory during memory mat switching). 3. if an interrupt request has occurred during memory mat switching, there is no guarantee of which memory mat is accessed. always mask the maskable interrupts before switching memory mats. in addition, configure the system so that nmi interrupts do not occur during memory mat switching. 4. after the memory mats have been switched, take care because the interrupt vector table will also have been switched. if interrupt processing is to be the same before and after memory mat switching, transfer the interrupt processing routines to the on-chip ram and specify vbr to place the interrupt vector table in the on-chip ram. 5. the size of the user mat is different from that of the user boot mat. addresses which exceed the size of the 16-kbyte user bo ot mat should not be accessed. if an attempt is made, data is read as an undefined value. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1092 of 1340 rej09b0499-0200 24.12 programmer mode along with its on-board programming mode, this lsi also has a programmer mode as a further mode for the writing and erasing of programs and data. in programmer mode, a general-purpose prom programmer that supports the device types shown in table 24.15 can be used to write programs to the on-chip rom without any limitation. table 24.15 device types supported in programmer mode target memory mat product classif ication rom size device type h8sx/1652 384 kbytes user mat h8sx/1655 512 kbytes fztat512v3a h8sx/1652 user boot mat h8sx/1655 16 kbytes fztatusbt16v3a 24.13 standard serial communications in terface specifications for boot mode the boot program initiated in boot mode performs serial communications using the host and on- chip sci_4. the serial co mmunications interface specifi cations are shown below. the boot program has three states. 1. bit-rate-adjustment state in this state, the boot progra m adjusts the bit rate to achiev e serial communications with the host. initiating boot mode enables starting of the boot program and entry to the bit-rate- adjustment state. the program receives the command from the host to adjust the bit rate. after adjusting the bit rate, the program enters the inquiry/selection state. 2. inquiry/selection state in this state, the boot program responds to inquiry commands from the host. the device name, clock mode, and bit rate are selected. after selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. the program transfers the libraries required for erasure to the on- chip ram and erases the user mats and user boot mats before the transition. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1093 of 1340 rej09b0499-0200 3. programming/erasing state programming and erasure by the boot program take place in this state. the boot program is made to transfer the programming/erasing programs to the on-chip ram by commands from the host. sum checks and blank checks are executed by sendin g these commands from the host. these boot program states are shown in figure 24.23. transition to programming/erasing programming/erasing wait checking inquiry response erasing programming reset bit-rate-adjustment state operations for erasing user mats and user boot mats operations for inquiry and selection operations for programming operations for checking operations for erasing operations for response inquiry/response wait figure 24.23 boot program states section 24 flash memory rev. 2.00 oct. 20, 2009 page 1094 of 1340 rej09b0499-0200 (1) bit-rate-adjustment state the bit rate is calculated by measuring the period of transfer of a low-level byte (h'00) from the host. the bit rate can be changed by the command for a new bit rate selection. after the bit rate has been adjusted, the boot program enters the inquiry and selection state. the bit-rate-adjustment sequence is shown in figure 24.24. host boot program h'00 (30 times maximum) h'e6 (boot response) measuring the 1-bit length h'00 (completion of adjustment) h'55 (h'ff (error)) figure 24.24 bit-rate-adjustment sequence (2) communications protocol after adjustment of the bit rate, the protocol fo r serial communications between the host and the boot program is as shown below. 1. one-byte commands and one-byte responses these one-byte commands and one-byte responses consist of the inquiries and the ack for successful completion. 2. n-byte commands or n-byte responses these commands and responses are comprised of n bytes of data. these are selections and responses to inquiries. the program data size is not included under this heading because it is determined in another command. 3. error response the error response is a response to inquiries. it consists of an error response and an error code and comes two bytes. 4. programming of 128 bytes the size is not specified in commands. the size of n is in dicated in response to the programming unit inquiry. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1095 of 1340 rej09b0499-0200 5. memory read response this response consists of four bytes of data. command or response size data checksum error response error code command or response error response n-byte command or n-byte response one-byte command or one-byte response address command data (n bytes) checksum 128-byte programming size response data checksum memory read response figure 24.25 communication protocol format ? command (one byte): commands including inquiries, selection, programming, erasing, and checking ? response (one byte): response to an inquiry ? size (one byte): the amount of data for transmission excluding the command, amount of data, and checksum ? checksum (one byte): th e checksum is calculated so that the total of all values from the command byte to the sum byte becomes h'00. ? data (n bytes): detailed data of a command or response ? error response (one byte): error response to a command ? error code (one byte): type of the error ? address (four bytes): address for programming ? data (n bytes): data to be programmed (the size is indicated in the response to the programming unit inquiry.) ? size (four bytes): four-byte response to a memory read section 24 flash memory rev. 2.00 oct. 20, 2009 page 1096 of 1340 rej09b0499-0200 (3) inquiry and selection states the boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. table 24.16 lists the inquiry and selection commands. table 24.16 inquiry and selection commands command command name description h'20 supported device inquiry inquiry regarding device codes h'10 device selection sele ction of device code h'21 clock mode inquiry inquiry regarding numbers of clock modes and values of each mode h'11 clock mode selection indication of the selected clock mode h'22 multiplication ratio inquiry i nquiry regarding the number of frequency- multiplied clock types, the number of multiplication ratios, and the values of each multiple h'23 operating clock frequency inquiry i nquiry regarding the maximum and minimum values of the main clock and peripheral clocks h'24 user boot mat information inquiry inquiry regarding the number of user boot mats and the start and last addresses of each mat h'25 user mat information inquiry inquiry regarding the a number of user mats and the start and last addresses of each mat h'26 block for erasing information inquiry inquiry regarding the number of blocks and the start and last addresses of each block h'27 programming unit inquiry inquiry re garding the unit of program data h'3f new bit rate selection selection of new bit rate h'40 transition to programming/erasing state erasing of user mat and user boot mat, and entry to programming/erasing state h'4f boot program status inquiry inquiry into the oper ated status of the boot program section 24 flash memory rev. 2.00 oct. 20, 2009 page 1097 of 1340 rej09b0499-0200 the selection commands, which are device selection (h'10), clock mode selection (h'11), and new bit rate selection (h'3f), should be sent from the host in that order. when two or more selection commands are sent at once, the last command will be valid. all of these commands, except for the boot program status inquiry command (h'4f), will be valid until the boot program receives th e programming/erasing transition (h'40). the host can choose the needed commands and make inquiries while th e above commands are being transmitted. h'4f is valid even after the boot program has received h'40. (a) supported device inquiry the boot program will return the device codes of supported devices and the product code in response to the supported device inquiry. command h'20 ? command, h'20, (one byte): inquiry regarding supported devices response h'30 size number of devices number of characters device code product name sum ? response, h'30, (one byte): response to the supported device inquiry ? size (one byte): number of bytes to be tr ansmitted, excluding the command, size, and checksum, that is, the amount of data contribu tes by the number of devices, characters, device codes and product names ? number of devices (one byte): the number of device types supported by the boot program ? number of characters (one byt e): the number of characters in the device codes and boot program's name ? device code (four bytes): ascii code of the supporting product ? product name (n bytes): type name of the boot program in ascii-coded characters ? sum (one byte): checksum the checksum is calculated so that the total number of all values from the command byte to the sum byte becomes h'00. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1098 of 1340 rej09b0499-0200 (b) device selection the boot program will set the supported device to the specified device code. the program will return the selected device code in response to the inquiry after this setting has been made. command h'10 size device code sum ? command, h'10, (one byte): device selection ? size (one byte): amount of device-code data this is fixed at 4. ? device code (four bytes): device code (ascii code) returned in response to the supported device inquiry ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): respon se to the device selection command ack will be returned when the device code matches. error response h'90 error ? error response, h'90, (one byte): error response to the device selection command error : (one byte): error code h'11: sum check error h'21: device code error, that is, the device code does not match (c) clock mode inquiry the boot program will return the supported clock modes in response to the clock mode inquiry. command h'21 ? command, h'21, (one byte): inquiry regarding clock mode response h'31 size mode sum ? response, h'31, (one byte): response to the clock-mode inquiry ? size (one byte): amount of data that represents the modes ? mode (two bytes): values of the supported clock modes h'00: md_clk = 0 (8 to 18 mhz input) h'01: md_clk = 1 (16 mhz input) ? sum (one byte): checksum section 24 flash memory rev. 2.00 oct. 20, 2009 page 1099 of 1340 rej09b0499-0200 (d) clock mode selection the boot program will set the specified clock mode. the program will return the selected clock- mode information after this setting has been made. the clock-mode selection command should be sent after the device-selection commands. command h'11 size mode sum ? command, h'11, (one byte): selection of clock mode ? size (one byte): amount of data that represents the modes ? mode (one byte): a clock mode returned in reply to the supported clock mode inquiry. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to the clock mode selection command ack will be returned when the clock mode matches. error response h'91 error ? error response, h'91, (one byte) : error response to the clock mode selection command ? error : (one byte): error code h'11: checksum error h'22: clock mode error, that is, the clock mode does not match. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1100 of 1340 rej09b0499-0200 (e) multiplication ratio inquiry the boot program will return the supported multiplication and division ratios. command h'22 ? command, h'22, (one byte): inquiry regarding multiplication ratio response h'32 size number of types of multipli cation number of multiplication ratios multiplica- tion ratio sum ? response, h'32, (one byte): response to the multiplication ratio inquiry ? size (one byte): the amount of data that represen ts the number of types of multiplication, the number of multiplication ratios, and the multiplication ratios ? number of types of multiplication (one byte): the number of types of multiplication to which the device can be set (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be h'02.) ? number of multiplication ratios (one byte): the number of types of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) ? multiplication ratio (one byte) multiplication ratio: the value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be h'04.) division ratio: the inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be h'fe. h'fe = -2) the number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types of multiplication. ? sum (one byte): checksum section 24 flash memory rev. 2.00 oct. 20, 2009 page 1101 of 1340 rej09b0499-0200 (f) operating clock frequency inquiry the boot program will return the number of operating clock frequencies, and the maximum and minimum values. command h'23 ? command, h'23, (one byte): inquiry regarding operating clock frequencies response h'33 size number of operating clock frequencies minimum value of operating clock frequency maximum value of operating clock frequency sum ? response, h'33, (one byte): response to operating clock frequency inquiry ? size (one byte): the number of bytes that re presents the minimum values, maximum values, and the number of frequencies. ? number of operating clock frequencies (one byte): the number of supported operating clock frequency types (e.g. when there are two operating clock frequen cy types, which are the main and peripheral clocks, the number of types will be h'02.) ? minimum value of operating clock frequency (two bytes): the minimum value of the multiplied or divided clock frequency. the minimum and maximum values of the operating clock frequency represent the values in mhz, valid to the hundredths place of mhz, an d multiplied by 100. (e.g . when the value is 17.00 mhz, it will be 2000, which is h'07d0.) ? maximum value (two bytes): maximum value among the multiplied or divided clock frequencies. there are as many pairs of minimum and maximum values as there are operating clock frequencies. ? sum (one byte): checksum section 24 flash memory rev. 2.00 oct. 20, 2009 page 1102 of 1340 rej09b0499-0200 (g) user boot mat information inquiry the boot program will return the number of user boot mats and their addresses. command h'24 ? command, h'24, (one byte): inquiry regarding user boot mat information response h'34 size number of areas area-start address area-last address sum ? response, h'34, (one byte): response to user boot mat information inquiry ? size (one byte): the number of bytes that repr esents the number of areas, area-start addresses, and area-last address ? number of areas (one byte): the number of consecutive user boot mat areas when user boot mat areas are consecutive, the number of areas returned is h'01. ? area-start address (four byte) : start address of the area ? area-last address (four byte) : last address of the area there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum (h) user mat information inquiry the boot program will return the number of user mats and their addresses. command h'25 ? command, h'25, (one byte): inquiry regarding user mat information response h'35 size number of areas start address area last address area sum ? response, h'35, (one byte): response to the user mat information inquiry ? size (one byte): the number of bytes that re presents the number of areas, area-start address and area-last address ? number of areas (one byte): the nu mber of consecutive user mat areas when the user mat areas are consecutive, the number of areas is h'01. ? area-start address (four bytes ): start address of the area section 24 flash memory rev. 2.00 oct. 20, 2009 page 1103 of 1340 rej09b0499-0200 ? area-last address (four bytes): last address of the area there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum (i) erased block information inquiry the boot program will return the number of erased blocks and their addresses. command h'26 ? command, h'26, (two bytes): inquiry regarding erased block information response h'36 size number of blocks block start address block last address sum ? response, h'36, (one byte): response to the number of erased blocks and addresses ? size (three bytes): the number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. ? number of blocks (one byte): the number of erased blocks ? block start address (four bytes): start address of a block ? block last address (four bytes): last address of a block there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum (j) programming unit inquiry the boot program will return the programming unit used to program data. command h'27 ? command, h'27, (one byte): inquiry regarding programming unit response h'37 size programming unit sum ? response, h'37, (one byte): response to programming unit inquiry ? size (one byte): the number of bytes that indicate the programming unit, which is fixed to 2 ? programming unit (two bytes): a unit for programming this is the unit for reception of programming. ? sum (one byte): checksum section 24 flash memory rev. 2.00 oct. 20, 2009 page 1104 of 1340 rej09b0499-0200 (k) new bit-rate selection the boot program will set a new bit rate and return the new bit rate. this selection should be sent after sending the clock mode selection command. command h'3f size bit rate input frequency number of types of multiplication multiplication ratio 1 multiplication ratio 2 sum ? command, h'3f, (one byte): selection of new bit rate ? size (one byte): the number of bytes that represents the bit rate, input frequency, number of types of multiplication, and multiplication ratio ? bit rate (two bytes): new bit rate one hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is h'00c0.) ? input frequency (two bytes): frequency of the clock input to the boot program this is valid to the hundredths place and represen ts the value in mhz mul tiplied by 100. (e.g. when the value is 20.00 mhz, it will be 2000, which is h'07d0.) ? number of types of multiplication (one byte): the number of multiplication to which the device can be set. ? multiplication ratio 1 (one byte) : the value of multiplication or division ratios for the main operating frequency multiplication ratio (one byte): the value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be h'04.) division ratio: the inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be h'fe. h'fe = d'-2) ? multiplication ratio 2 (one byte): the value of multiplication or division ratios for the peripheral frequency multiplication ratio (one byte): the value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be h'04.) (division ratio: the inverse of the division ratio, as a negative number (e.g. when the clock is divided by two, the value of division ratio will be h'fe. h'fe = d'-2) ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to selection of a new bit rate when it is possible to set the bit rate, the response will be ack. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1105 of 1340 rej09b0499-0200 error response h'bf error ? error response, h'bf, (one byte): error response to selection of new bit rate ? error: (one byte): error code h'11: sum checking error h'24: bit-rate selection error the rate is not available. h'25: error in input frequency this input frequency is not within the specified range. h'26: multiplication-ratio error the ratio does not match an available ratio. h'27: operating frequency error the frequency is not within the specified range. (4) receive data check the methods for checking of r eceive data are listed below. 1. input frequency the received value of the input fr equency is checked to ensure th at it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. when the value is out of this range, an input-frequency error is generated. 2. multiplication ratio the received value of the multipli cation ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. when the value is out of this range, an input- frequency error is generated. 3. operating frequency error operating frequency is calculated from the r eceived value of the input frequency and the multiplication or division ratio. the input frequency is input to the lsi and the lsi is operated at the operating frequency. the expression is given below. operating frequency = input frequency multiplication ratio, or operating frequency = input frequency division ratio the calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. when it is out of this range, an operating frequency error is generated. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1106 of 1340 rej09b0499-0200 4. bit rate to facilitate error checking, the value (n) of clock select (cks) in the serial mode register (smr), and the value (n) in the bit rate regi ster (brr), which are fo und from the peripheral operating clock frequency ( ) and bit rate (b), are used to calcu late the error rate to ensure that it is less than 4%. if the error is more than 4%, a bit rate error is generated. the error is calculated using the fo llowing expression: error (%) = {[ ] ? 1} 100 (n + 1) b 64 2 (2 n ? 1) 10 6 when the new bit rate is selectable, the rate will be set in the register after sending ack in response. the host will send an ack with the new bit rate for confirmation and the boot program will response with that rate. confirmation h'06 ? confirmation, h'06, (one byte): confirmation of a new bit rate response h'06 ? response, h'06, (one byte): response to confirmation of a new bit rate the sequence of new bit-rate selection is shown in figure 24.26. host boot program setting a new bit rate h'06 (ack) waiting for one-bit period at the specified bit rate h'06 (ack) with the new bit rate h'06 (ack) with the new bit rate setting a new bit rate setting a new bit rate figure 24.26 new bit- rate selection sequence section 24 flash memory rev. 2.00 oct. 20, 2009 page 1107 of 1340 rej09b0499-0200 (5) transition to programming/erasing state the boot program will transfer the erasing program, and erase the user mats and user boot mats in that order. on completion of this erasur e, ack will be returned and will enter the programming/erasing state. the host should select the device code, clock mode, and new bit rate with device selection, clock- mode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. these procedures should be carried out before sending of the programming selection command or program data. command h'40 ? command, h'40, (one byte): transition to programming/erasing state response h'06 ? response, h'06, (one byte): response to transition to programming/erasing state the boot program will send ack when the user mat and user boot mat have been erased by the transferred erasing program. error response h'c0 h'51 ? error response, h'c0, (one byte): error response for user boot mat blank check ? error code, h'51, (one byte): erasing error an error occurred and er asure was not completed. (6) command error a command error will occur when a command is un defined, the order of commands is incorrect, or a command is unacceptable. issuing a clock-mo de selection command be fore a device selection or an inquiry command after the transition to programming/erasing state command, are examples. error response h'80 h'xx ? error response, h'80, (one byte): command error ? command, h'xx, (one byte): received command section 24 flash memory rev. 2.00 oct. 20, 2009 page 1108 of 1340 rej09b0499-0200 (7) command order the order for commands in the inquir y selection state is shown below. 1. a supported device inquiry (h'20) should be made to inquire about the supported devices. 2. the device should be selected from among those described by the returned information and set with a device-selection (h'10) command. 3. a clock-mode inquiry (h'21) should be made to inquire about the supported clock modes. 4. the clock mode should be selected from among those described by the returned information and set. 5. after selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (h'22) or operating frequency inquiry (h'23), which are needed for a new bit-rate selection. 6. a new bit rate should be selected with the new bit-rate selection (h'3f) command, according to the returned information on multiplication ratios and operating frequencies. 7. after selection of the device and clock mode, the information of the user boot mat and user mat should be made to inquire about the user boot mats information inquiry (h'24), user mats information inquiry (h'25), erased block information inquiry (h'26), and programming unit inquiry (h'27). 8. after making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (h'40). the boot program will then enter the programming/erasing state. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1109 of 1340 rej09b0499-0200 (8) programming/erasing state a programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. table 24.17 lists the programming/erasing commands. table 24.17 programming/erasing commands command command name description h'42 user boot mat programming selection t ransfers the user boot mat programming program h'43 user mat programming selection transfers the user mat programming program h'50 128-byte programming programs 128 bytes of data h'48 erasing selection trans fers the erasing program h'58 block erasing erases a block of data h'52 memory read reads the contents of memory h'4a user boot mat sum check checks the checksum of the user boot mat h'4b user mat sum check checks the checksum of the user mat h'4c user boot mat blank check checks the blank data of the user boot mat h'4d user mat blank check checks the blank data of the user mat h'4f boot program status inquiry i nquires into the boot program's status section 24 flash memory rev. 2.00 oct. 20, 2009 page 1110 of 1340 rej09b0499-0200 ? programming programming is executed by the programming selection and 128-byte programming commands. firstly, the host should send the programming selection command and select the programming method and programming mats. there are two programming selection commands, and selection is according to the ar ea and method for programming. 1. user boot mat programming selection 2. user mat programming selection after issuing the programming selection command, the host should send the 128-byte programming command. the 128-byte programming command that follows the selection command represents the data pr ogrammed according to the meth od specified by the selection command. when more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. sending a 128-byte programming command with h'ffffffff as the address will stop the programming. on completion of programming, the boot program will wait for selection of programming or erasing. where the sequence of programming operations th at is executed includes programming with another method or of another mat, the procedure must be repeated from the programming selection command. the sequence for the programming selection and 128-byte programming commands is shown in figure 24.27. transfer of the programming program host boot program programming selection (h'42, h'43) ack programming 128-byte programming (address, data) ack 128-byte programming (h'ffffffff) ack repeat figure 24.27 programming sequence section 24 flash memory rev. 2.00 oct. 20, 2009 page 1111 of 1340 rej09b0499-0200 ? erasure erasure is executed by the erasure selection an d block erasure commands. firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. the command should be repeat edly executed if two or more blocks are to be erased. sending a block erasure command from the host with the block number h'ff will stop the erasure operating. on completion of erasing, the boot program will wait for selection of programming or erasing. the sequence for the erasure selection and bl ock erasure commands is shown in figure24.28 transfer of erasure program host boot program preparation for erasure (h'48) ack erasure erasure (erasure block number) erasure (h'ff) ack ack repeat figure 24.28 erasure sequence section 24 flash memory rev. 2.00 oct. 20, 2009 page 1112 of 1340 rej09b0499-0200 (a) user boot mat programming selection the boot program will transfer a programming program. the data is programmed to the user boot mats by the transferred programming program. command h'42 ? command, h'42, (one byte): user boot mat programming selection response h'06 ? response, h'06, (one byte): response to user boot mat programming selection when the programming program has been transferred, the boot program will return ack. error response h'c2 error ? error response: h'c2 (1 byte): error response to user boot mat programming selection ? error: (1 byte): error code h'54: selection processing error (transfer error occurs and processing is not completed) (b) user mat programming selection the boot program will transfer a program for us er mat programming selection. the data is programmed to the user mats by the transferred program for programming. command h'43 ? command, h'43, (one byte): user mat programming selection response h'06 ? response, h'06, (one byte): response to user mat programming selection when the programming program has been transferred, the boot program will return ack. error response h'c3 error ? error response: h'c3 (1 byte): error response to user mat programming selection ? error: (1 byte): error code h'54: selection processing error (transfer error occurs and processing is not completed) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1113 of 1340 rej09b0499-0200 (c) 128-byte programming the boot program will use the programming program transferred by the programming selection to program the user boot mats or user mats in response to 128-byte programming. command h'50 address data sum ? command, h'50, (one byte): 128-byte programming ? programming address (four bytes): start address for programming multiple of the size specified in response to the programming unit inquiry (i.e. h'00, h'01, h'00, h'00: h'01000000) ? program data (128 bytes): data to be programmed the size is specified in the response to the programming unit inquiry. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to 128-byte programming on completion of programming, the boot program will return ack. error response h'd0 error ? error response, h'd0, (one byte): error response for 128-byte programming ? error: (one byte): error code h'11: checksum error h'2a: address error the address is not in the specified mat. h'53: programming error a programming error has occurred and programming cannot be continued. the specified address should match the unit for programming of data. fo r example, when the programming is in 128-byte units, the lower eight bits of the address should be h'00 or h'80. when there are less than 128 bytes of data to be programmed, the host should fill the rest with h'ff. sending the 128-byte programming command with the address of h'ffffffff will stop the programming operation. the boot program will interpret this as the end of the programming and wait for selection of programming or erasing. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1114 of 1340 rej09b0499-0200 command h'50 address sum ? command, h'50, (one byte): 128-byte programming ? programming address (four bytes): end code is h'ff, h'ff, h'ff, h'ff. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to 128-byte programming on completion of programming, the boot program will return ack. error response h'd0 error ? error response, h'd0, (one byte): error response for 128-byte programming ? error: (one byte): error code h'11: checksum error h'53: programming error an error has occurred in programming and programming cannot be continued. (d) erasure selection the boot program will transfer th e erasure program. user mat data is erased by the transferred erasure program. command h'48 ? command, h'48, (one byte): erasure selection response h'06 ? response, h'06, (one byte): response for erasure selection after the erasure program has been transferred, the boot program will return ack. error response h'c8 error ? error response, h'c8, (one byte): error response to erasure selection ? error: (one byte): error code h'54: selection processing error (transfer error occurs and processing is not completed) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1115 of 1340 rej09b0499-0200 (e) block erasure the boot program will erase the c ontents of the specified block. command h'58 size block number sum ? command, h'58, (one byte): erasure ? size (one byte): the number of bytes th at represents the erase block number this is fixed to 1. ? block number (one byte): number of the block to be erased ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to erasure after erasure has been completed, the boot program will return ack. error response h'd8 error ? error response, h'd8, (one byte): response to erasure ? error (one byte): error code h'11: sum check error h'29: block number error block number is incorrect. h'51: erasure error an error has occurred during erasure. on receiving block number h'ff, the boot program will stop erasure and wait for a selection command. command h'58 size block number sum ? command, h'58, (one byte): erasure ? size, (one byte): the number of bytes that represents the block number this is fixed to 1. ? block number (one byte): h'ff stop code for erasure ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to end of erasure (ack) when erasure is to be performed after the block number h'ff has been sent, the procedure should be executed from the erasure selection command. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1116 of 1340 rej09b0499-0200 (f) memory read the boot program will return the data in the specified address. command h'52 size area read address read size sum ? command: h'52 (1 byte): memory read ? size (1 byte): amount of data that represents th e area, read address, and read size (fixed at 9) ? area (1 byte) h'00: user boot mat h'01: user mat an address error occurs wh en the area setting is incorrect. ? read address (4 bytes): star t address to be read from ? read size (4 bytes): size of data to be read ? sum (1 byte): checksum response h'52 read size data sum ? response: h'52 (1 byte): response to memory read ? read size (4 bytes): size of data to be read ? data (n bytes): data for the read size from the read address ? sum (1 byte): checksum error response h'd2 error ? error response: h'd2 (1 byte): error response to memory read ? error: (1 byte): error code h'11: sum check error h'2a: address error the read address is not in the mat. h'2b: size error the read size exceeds the mat. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1117 of 1340 rej09b0499-0200 (g) user boot mat sum check the boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program, as a four-byte value. command h'4a ? command, h'4a, (one byte): sum check for user-boot program response h'5a size checksum of user boot program sum ? response, h'5a, (one byte): response to the sum check of user-boot program ? size (one byte): the number of byt es that represents the checksum this is fixed to 4. ? checksum of user boot program (four bytes): checksum of user boot mats the total of the data is obtained in byte units. ? sum (one byte): sum check for data being transmitted (h) user mat sum check the boot program will return the byte-by-byte total of the contents of the bytes of the user program. command h'4b ? command, h'4b, (one byte): sum check for user program response h'5b size checksum of user program sum ? response, h'5b, (one byte): response to the sum check of the user program ? size (one byte): the number of byt es that represents the checksum this is fixed to 4. ? checksum of user boot program (four bytes): checksum of user mats the total of the data is obtained in byte units. ? sum (one byte): sum check for data being transmitted section 24 flash memory rev. 2.00 oct. 20, 2009 page 1118 of 1340 rej09b0499-0200 (i) user boot mat blank check the boot program will check whether or not all user boot mats are blank and return the result. command h'4c ? command, h'4c, (one byte): blank check for user boot mat response h'06 ? response, h'06, (one byte): response to the blank check of user boot mat if all user mats are blank (h'ff), th e boot program will return ack. error response h'cc h'52 ? error response, h'cc, (one byte): response to blank check for user boot mat ? error code, h'52, (one byte): erasure has not been completed. (j) user mat blank check the boot program will check whether or not all user mats are blank and return the result. command h'4d ? command, h'4d, (one byte): blank check for user mats response h'06 ? response, h'06, (one byte): response to the blank check for user mats if the contents of all user mats are blank (h'ff), the boot program will return ack. error response h'cd h'52 ? error response, h'cd, (one byte): error response to the blank check of user mats. ? error code, h'52, (one byte): erasure has not been completed. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1119 of 1340 rej09b0499-0200 (k) boot program state inquiry the boot program will return indications of its present state and error condition. this inquiry can be made in the inquiry/selection stat e or the programming/erasing state. command h'4f ? command, h'4f, (one byte): inquiry regarding boot program's state response h'5f size status error sum ? response, h'5f, (one byte): response to boot program state inquiry ? size (one byte): the number of bytes. this is fixed to 2. ? status (one byte): state of the boot program ? error (one byte): error status error = 0 indicates normal operation. error = 1 indicates error has occurred. ? sum (one byte): sum check table 24.18 status code code description h'11 device selection wait h'12 clock mode selection wait h'13 bit rate selection wait h'1f programming/erasing stat e transition wait (bit rate selection is completed) h'31 programming state for erasure h'3f programming/erasing selection wait (erasure is completed) h'4f program data receive wait h'5f erase block specification wait (erasure is completed) section 24 flash memory rev. 2.00 oct. 20, 2009 page 1120 of 1340 rej09b0499-0200 table 24.19 error code code description h'00 no error h'11 sum check error h'12 program size error h'21 device code mismatch error h'22 clock mode mismatch error h'24 bit rate selection error h'25 input frequency error h'26 multiplication ratio error h'27 operating frequency error h'29 block number error h'2a address error h'2b data length error h'51 erasure error h'52 erasure incomplete error h'53 programming error h'54 selection processing error h'80 command error h'ff bit-rate-adjustment confirmation error section 24 flash memory rev. 2.00 oct. 20, 2009 page 1121 of 1340 rej09b0499-0200 24.14 usage notes 1. the initial state of the product at its shipment is in the erased state. for the product whose revision of erasing is undefined, we recommend to execute automatic er asure for checking the initial state (erased state) and compensating. 2. for the prom programmer suitable for programmer mode in this lsi and its program version, refer to the instruction manual of the socket adapter. 3. if the socket, socket adapter, or product index of the prom programmer do not match the specifications, too much current flows and the product may be damaged. 4. use a prom programmer that supports the device with 1-mbyte on-chip flash memory and 3.3-v programming voltage. use only the specified socket adapter. 5. do not turn off the vcc power supply nor remove the chip from the prom programmer during programming/erasure in which a high voltage is applied to the flash memory. doing so may damage the flash memory permanently. if a reset is input, the reset must be released after the reset input period of at least 100ms. 6. the flash memory is not accessi ble until fkey is cleared after programming/erasure starts. if the operating mode is changed and this lsi is restarted by a reset immediately after programming/erasure has finished, secure the reset input period (period of res = 0) of at least 100 s. transition to the reset state during programmin g/erasure is inhibited. if a reset is input, the reset must be released after the reset input period of at least 100 s. 7. at powering on the vcc power supply, fix the res pin to low and set the flash memory to hardware protection state. this power on proced ure must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. in on-board programming mode or programmer mode, programming of the 128-byte programming-unit block must be performed only once. perform programming in the state where the programming-unit block is fully erased. 9. when the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming be performed after execution of automatic erasure. 10. to program the flash memory, the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and h'ff must be written to all the system reserved areas in th e exception handling vector table. 11. the programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. accordingly, when the cpu clock frequency is 35 mhz, the download for each program takes approximately 60 s at the maximum. section 24 flash memory rev. 2.00 oct. 20, 2009 page 1122 of 1340 rej09b0499-0200 12. a programming/erasing program for the flash memory used in a conventional f-ztat h8, h8s microcomputer which does not support download of the on-chip program by setting the sco bit in fccs to 1 cannot run in this lsi. be sure to download the on-chip program to execute programming/erasure of the flash memory in this f-ztat h8sx microcomputer. 13. unlike a conventional f-ztat h8 or h8s microcomputers, measures against a program crash are not taken by wdt while programming/erasing and downloading a programming/erasing program. when needed, measures should be taken by user. a periodic interrupt generated by the wdt can be used as the meas ures, as an example. in this case, the interrupt generation period should take into consideration time to program/erase the flash memory. 14. when downloading the programming/erasing program, do not clear the sco bit in fccs to 0 immediately after setting it to 1. otherwise, download cannot be performed normally. immediately after executing the in struction to set the sco bit to 1, dummy read of the fccs must be executed twice. 15. the contents of general registers er0 and er1 are not saved during download of an on-chip program, initialization, programming, or erasur e. when needed, save the general registers before a download request or before execution of initialization, programming, or erasure using the procedure program. section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1123 of 1340 rej09b0499-0200 section 25 boundary scan this lsi has boundary scan function, which is a serial i/o interface based on the jtag (joint test action group, ieee std.1149.1 and ieee standard test acce ss port and boundary-scan architecture). 25.1 features ? boundary scan valid single chip mode when the emle pin= 0 in mcu operating mode 3 ? p62, p63, p64, p65, and wdtovf are pins only for boundary scan when boundary scan is valid ? six test modes: bypass mode extest mode sample/preload mode clamp mode highz mode idcode mode section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1124 of 1340 rej09b0499-0200 25.2 block diagram of boundary scan function figure 25.1 shows the block diagram of the boundary scan function. jtbpr tdi tdo tck tms trst jtbsr shift register mux tap controller decoder jtir jtdir jtbpr: jtbsr: jtir: jtdir: bypass register boundary scan register instruction register id register [legend] figure 25.1 block diagram of boundary scan function 25.3 input/output pins table 25.1 shows the i/o pins used in the boundary scan function. table 25.1 pin configuration pin name i/o description tck input test clock input pin clock signal for boundary scan. input the clock the duty cycle of which is 50 percent when boundary scan function is used. tms input test mode select pin tdi input test data input pin tdo output test data output pin trst input test reset input pin section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1125 of 1340 rej09b0499-0200 25.4 register descriptions boundary scan has the following four registers. these registers cannot be accessed from the cpu. ? introduction register (jtir) ? bypass register (jtbpr) ? boundary scan register (jtbsr) ? idcode register (jtidr) instructions can be input to the instruction regist er (jtir) via the test data input pin (tdi) by serial transfer. the bypass regist er (jtbpr), which is a 1-bit register, is connected between the tdi and tdo pins in bypass mode. the boundary scan register (jtbsr), which is a jtbsr-bit register (see table 25.4), is connected between the tdi and tdo pins when test data are being shifted in. none of the regist ers is accessible from the cpu. table 25.2 shows the availability of serial transfer for the registers. table 25.2 serial transfers for registers register abbreviation serial input serial output jtir available not available jtbpr available available jtbsr available available jtid not available available section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1126 of 1340 rej09b0499-0200 25.4.1 instruction register (jtir) jtir is a 16-bit register. jtag instructions can be transferred to jtir by serial input from the tdi pin. jtir is initialized when the trst signal is low level, when the tap controller is in the test-logic-reset state, and when this lsi is placed in hardware stan dby mode. jtir is not initialized by a reset or entry to software standby mode. instructions must be serially transferred in 4-bit units. when an instruction with more than 4 bi ts is being transferred, the last four bits of the serial data are stored in jtir. bit bit name initial value r/w 15 ts3 0 ? 14 ts2 0 ? 13 ts1 0 ? 12 ts0 0 ? 11 ? 0 ? 10 ? 0 ? 9 ? 0 ? 8 ? 0 ? bit bit name initial value r/w 7 ? 0 ? 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 2 ? 0 ? 1 ? 0 ? 0 ? 0 ? bit bit name initial value r/w descriptions 15 to 12 ts[3:0] all 0 r/w test bit set specify an instruction as shown in table 25.3. 11 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always 0. section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1127 of 1340 rej09b0499-0200 table 25.3 boundary scan instructions ts3 ts2 ts1 ts0 instruction 0 0 0 0 extest 0 0 0 1 idcode (initial value) 0 0 1 0 clamp 0 0 1 1 highz 0 1 0 0 sample/preload 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 bypass 25.4.2 bypass register (jtbpr) jtbpr is a 1-bit register and is connected betw een the tdi and tdo pins when jtir is set to bypass mode. jtbpr cannot be read from or written to by the cpu. 25.4.3 boundary scan register (jtbsr) jtbsr is a shift register to control the external input and output pins of this lsi and is distributed across the pads. the initial values are undefine d. jtbsr cannot be accessed by the cpu. the extest, sample/preload, clamp, and highz instructions are issued to apply jtbsr in boundary-scan testing conformant to the jtag standard. table 25.5 shows the correspondence between th e jtbsr bits and the pins of this lsi. section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1128 of 1340 rej09b0499-0200 table 25.4 relationship between pins and jtbsr bits from tdi pin no. pin no. lqfp-120 lga-145 pin name input/output bit name lqfp-120 lga-145 pin name input/output bit name 3 c1 pb3 input output enable output 295 294 293 16 h1 pe5 input output enable output 244 243 242 4 d1 md2 input 289 18 h2 pe4 input output enable output 241 240 239 5 d3 pm0 input output enable output 288 287 286 20 h3 pe3 input output enable output 238 237 236 6 d2 pm1 input output enable output 284 283 282 21 j4 pe2 input output enable output 235 234 233 7 e1 pm2 input output enable output 280 279 278 22 j2 pe1 input output enable output 232 231 230 8 f1 pf4 input output enable output 265 264 263 23 k1 pe0 input output enable output 229 228 227 9 f4 pf3 input output enable output 262 261 260 24 j3 pd7 input output enable output 226 225 224 11 f2 pf2 input output enable output 259 258 257 25 k4 pd6 input output enable output 223 222 221 12 g1 pf1 input output enable output 256 255 254 27 k2 pd5 input output enable output 220 219 218 13 h4 pf0 input output enable output 253 252 251 28 k3 pd4 input output enable output 217 216 215 14 g3 pe7 input output enable output 250 249 248 29 l1 pd3 input output enable output 214 213 212 15 g2 pe6 input output enable output 247 246 245 section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1129 of 1340 rej09b0499-0200 pin no. pin no. lqfp-120 lga-145 pin name input/output bit name lqfp-120 lga-145 pin name input/output bit name 30 m1 pd2 input output enable output 211 210 209 49 k7 p25 input output enable output 168 167 166 31 m2 pd1 input output enable output 208 207 206 50 k8 p26 input output enable output 156 155 154 32 n1 pd0 input output enable output 205 204 203 51 n8 p27 input output enable output 153 152 151 52 l9 nmi input 150 34 n2 pm3 input output enable output 201 200 199 53 m9 ph0 input output enable output 143 142 141 35 n3 pm4 input output enable output 197 196 195 40 l4 vbus input 194 54 l10 ph1 input output enable output 140 139 138 41 l5 md_c lk input 193 55 k10 ph2 input output enable output 137 136 135 43 m6 p20 input output enable output 183 182 181 56 n10 ph3 input output enable output 134 133 132 45 k6 p21 input output enable output 180 179 178 61 m12 ph7 input output enable output 131 130 129 46 n6 p22 input output enable output 177 176 175 58 m11 ph4 input output enable output 128 127 126 47 m7 p23 input output enable output 174 173 172 59 n11 ph5 input output enable output 125 124 123 48 l6 p24 input output enable output 171 170 169 60 n12 ph6 input output enable output 122 121 120 section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1130 of 1340 rej09b0499-0200 pin no. pin no. lqfp-120 lga-145 pin name input/output bit name lqfp-120 lga-145 pin name input/output bit name 64 l13 pi1 input output enable output 119 118 117 75 g11 p13 input output enable output 86 85 84 65 l11 pi2 input output enable output 116 115 114 79 g10 p14 input output enable output 77 76 75 66 l12 pi3 input output enable output 113 112 111 80 f11 p15 input output enable output 74 73 72 63 m13 pi0 input output enable output 110 109 108 86 e11 p16 input output enable output 71 70 69 68 k11 pi4 input output enable output 107 106 105 87 e10 p17 input output enable output 68 67 66 69 k12 pi5 input output enable output 104 103 102 89 b13 p60 input output enable output 59 58 57 71 j10 pi7 input output enable output 101 100 99 90 a13 p61 input output enable output 53 52 51 97 d10 md0 input 50 70 j13 pi6 input output enable output 98 97 96 109 b6 md1 input 43 72 j11 p10 input output enable output 95 94 93 110 d6 pa0 input output enable output 32 31 30 73 h11 p11 input output enable output 92 91 90 111 a5 pa1 input output enable output 29 28 27 74 j12 p12 input output enable output 89 88 87 112 b4 pa2 input output enable output 26 25 24 section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1131 of 1340 rej09b0499-0200 pin no. lqfp-120 lga-145 pin name input/output bit name 113 d5 pa3 input output enable output 23 22 21 114 a4 pa4 input output enable output 20 19 18 115 c5 pa5 input output enable output 17 16 15 116 c4 pa6 input output enable output 14 13 12 118 a2 pa7 input output enable output 11 10 9 120 b2 pb0 input output enable output 8 7 6 1 a1 pb1 input output enable output 5 4 3 2 b1 pb2 input output enable output 2 1 0 to tdo section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1132 of 1340 rej09b0499-0200 25.4.4 idcode register (jtid) jtid is a 32-bit register. jtid data is output from the tdo pin when the idcode instruction has been executed. data cannot be written to jtid from the tdi pin. bit bit name initial value r/w 31 did31 ? r/w 30 did30 ? r/w 29 did29 ? r/w 28 did28 ? r/w 27 did27 ? r/w 26 did26 ? r/w 25 did25 ? r/w 24 did24 ? r/w 23 did23 ? r/w 22 did22 ? r/w 21 did21 ? r/w 20 did20 ? r/w 19 did19 ? r/w 18 did18 ? r/w 17 did17 ? r/w 16 did16 ? r/w bit bit name initial value r/w 15 did15 ? r/w 14 did14 ? r/w 13 did13 ? r/w 12 did12 ? r/w 11 did11 ? r/w 10 did10 ? r/w 9 did9 ? r/w 8 did8 ? r/w 7 did7 ? r/w 6 did6 ? r/w 5 did5 ? r/w 4 did4 ? r/w 3 did3 ? r/w 2 did2 ? r/w 1 did1 ? r/w 0 did0 ? r/w bit bit name initial value r/w descriptions 31 to 0 did31 to did0 h'0807f447 r/w jtid is a register the value showing the decide idcode is fixed. section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1133 of 1340 rej09b0499-0200 25.5 operations the boundary scan functionality is valid when the emle pin is set t o 0 and this lsi is in mcu operation mode 3. 25.5.1 tap controller figure 25.2 shows the state transition diagram of the tap controller. test -logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr run-test/idle 1 0 0 0 0 11 1 1 0 0 0 1 11 0 1 1 1 0 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir 0 0 1 0 0 0 1 0 1 1 10 figure 25.2 state transi tions of the tap controller section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1134 of 1340 rej09b0499-0200 25.5.2 commands bypass (instruction code: b'1111): the bypass instruction is an instruction that drives the bypass register (jtbpr). this instruction shortens the shift path, facilitating the transfer of serial data to other lsis on a printed-circuit board at higher speeds. while this instruction is being executed, the test circuit has no effect on the system circuits. the bypass register (jtbpr) is connected betw een the tdi and tdo pins. bypass operation is initiated from shift-dr operation. the tdo is at 0 in the first clock cycle in the shift-dr state; in the subsequent clock cycles, the tdi signal is output on the tdo pin. extest (instruction code: b'0000): the extest instruction is used to test external circuits when this lsi is installed on the printed circuit board. if this instruction is executed, output pins are used to output test data (specified by the sample/preload instruction) from the boundary scan register to the print circuit board, and input pins are used to input test result. sample/preload (instruction code: b'0100): the sample/preload instruction is used to input data from the lsi internal circuits to the boundary scan register, output data from scan path, and reload the data to the scan path. while this instruction is executed, input signals are directly input to the lsi and output signals are also directly output to the external circuits. the lsi system circuit is not affected by this function. in sample operation, the boundary scan register latches the snap shot of data transferred from input pins to internal circuit or data transferred from internal circuit to output pins. the latched data is read from the scan path. the scan register latches the snap data at the rising edge of the tck in capture-dr state. the s can register latches snap shot without affecting the lsi normal operation. in preload operation, initial value is written from the scan path to the parallel output latch of the boundary scan register prior to the extest instruction execution. if the extest is executed without executing this preload operation, undefined values are output from the beginning to the end (transfer to the output latch) of the extest sequence. (in extest instruction, output parallel latches are always output to the output pins.) idcode (instruction code: b'0001): when the idcode instruct ion is selected, idcode register value is output to the tdo in shift-dr state of the tap controller. in this case, idcode register value is output from the lsb. during this instruction execution, test circuit does not affect the system circuit. instr is initialized by the id code instruction in test-logic-reset state of the tap controller. section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1135 of 1340 rej09b0499-0200 clamp (instruction code: b'0010): when the clamp instruction is selected, output pins output the boundary scan register value which was specified by the sample/preload instruction in advance. while the clamp instruc tion is selected, the stat us of boundary scan register is maintained regardless of the tap co ntroller state. bypass is connected between tdi and tdo, the same operation as by pass instruction can be achieved. this instruction connects the bypass register (jtbpr) between the tdi and tdo pins, leading to the same operation as when bypa ss mode has been selected. highz (instruction code: b'0011): when the highz instruction is selected, all output pins enter high-impedance state. while the highz instruction is selected, the status of boundary scan register is maintained regardless of the state of the tap controller. bypass is connected between tdi and tdo pins, leading to the same operation as when the bypass instruction has been selected. section 25 boundary scan rev. 2.00 oct. 20, 2009 page 1136 of 1340 rej09b0499-0200 25.6 usage notes 1. in serial transfer, data are input or output in lsb order (see figure 25.3). from tdi pin jtir and jtidr bit 31 bit 30 bit 1 bit 0 shift register serial data input/output in lsb order notes: serial data output from jtir to tdo is not possible. serial data input from tdi to jtidr is not possible. to tdo pin . . . . . . figure 25.3 serial data input/output 2. if a pin with open-drain function is sampleed while its open-drain function is enabled and while the corresponding out register is set to 1, the corresponding control register is cleared to 0 (the pin status is hi-z). if the pin is sampleed while the corresponding out register is cleared to 0, the corresponding control register is 1 (the pin status is 0) 3. pins of the boundary scan (tck, tdi, tms, and trst ) have to be pulled up by pull-up resistors. 4. power supply pins (v cc , v cl , v ss , av cc , av ss , vref, pllv cc , pllv ss , drv cc , and drv ss ) cannot be boundary-scanned. 5. clock pins (extal and xtal) cannot be boundary-scanned. 6. reset and standby signals ( res and stby ) cannot be boundary-scanned. 7. boundary scan pins (tck, tms, trst , tdi, and tdo) cannot be boundary-scanned. 8. the boundary scan function is not availabl e when this lsi are in the following states. (1) reset state (2) hardware standby mode, software standby mode, and deep software standby mode section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1137 of 1340 rej09b0499-0200 section 26 clock pulse generator this lsi has an on-chip clock pulse generator (cpg) that generates the system clock (i ), peripheral module clock (p ), external bus clock (b ), and usb clock (cku). the clock pulse generator consists of a main clock oscillator, frequency divider, pll (phase- locked loop) circuit, waveform generation circuit, and selector. figure 26.1 is a block diagram of the clock pulse generator. the frequency divider, pll circuit, and selector can change the clock frequency. software changes the frequency through the setting of the system clock control register (sckcr). this lsi supports four clocks: a system clock provided to the cpu and bus masters, a peripheral module clock provided to the peripheral modules, an external bus clock prov ided to the external bus and a usb clock provided to the usb module. frequencies of the peripheral module clock, the external bus clock, and the system clock can be set independently, although the peripheral module clock and the external bus clock operate w ith the frequency lower than the system clock frequency. the usb module requires the 48-mhz clock. se t the external clock frequency and the md_clk pin so that the usb clock (cku ) frequency becomes 48 mhz. note that the md_clk pin setting also changes the frequencies of the peripheral module clock, the external bus clock, and the system clock. section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1138 of 1340 rej09b0499-0200 extal md_clk xtal pll circuit oscillator system clock (i ) (to the cpu, and bus masters) ick2 to ick0 cks cku ckb ckm sckcr divider pck2 to pck0 bck2 to bck0 sckcr sckcr 2 (1) 1 (1/2) 1/2 (setting prohibited) extal 4 (2) * extal 4 (3) selector selector selector peripheral module clock (p ) (to peripheral modules) external bus clock (b ) (to the b pin) usb clock (cku) (to usb) note: * values in parentheses are setting values when md_clk = 1. figure 26.1 block diagra m of clock pulse generator table 26.1 selection of clock pulse generator md_clk extal input clock frequencies i /p /b usb clock (cku) 0 8 mhz to 18 mhz extal 4, 2, 1, 1/2 extal 4 1 16 mhz extal 2, 1, 1/2 extal 3 section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1139 of 1340 rej09b0499-0200 26.1 register description the clock pulse generator has the following registers. ? system clock control register (sckcr) 26.1.1 system clock control register (sckcr) sckcr controls b output control and frequencies of the system, peripheral module, and external bus clocks. bit bit name initial value r/w 15 pstop1 0 r/w 14 ? 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 ? 0 r/w 10 ick2 0 r/w 9 ick1 1 r/w 8 ick0 0 r/w bit bit name initial value r/w 7 ? 0 r/w 6 pck2 0 r/w 5 pck1 1 r/w 4 pck0 0 r/w 3 ? 0 r/w 2 bck2 0 r/w 1 bck1 1 r/w 0 bck0 0 r/w bit bit name initial value r/w description 15 pstop1 0 r/w b clock output enable controls output on pa7. ? normal operation 0: output 1: fixed high 14 to 11 ? all 0 r/w reserved although these bits are readable/writable, only 0 should be written to. section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1140 of 1340 rej09b0499-0200 bit bit name initial value r/w description 10 9 8 ick2 ick1 ick0 0 1 0 r/w r/w r/w system clock (i ) select these bits select the frequency of the system clock provided to the cpu, exdmac, dmac, and dtc. the ratio to the input clock is as follows: ick (2:0) md_clk = 0 md_clk = 1 000: 4 2 001: 2 1 010: 1 1/2 011: 1/2 setting prohibited 1xx: setting prohibited the frequencies of the peripheral module clock and external bus clock change to the same frequency as the system clock if the frequency of the system clock is lower than that of the two clocks. 7 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to. 6 5 4 pck2 pck1 pck0 0 1 0 r/w r/w r/w peripheral module clock (p ) select these bits select the frequency of the peripheral module clock. the ratio to the input clock is as follows: pck (2:0) md_clk = 0 md_clk = 1 000: 4 2 001: 2 1 010: 1 1/2 011: 1/2 setting prohibited 1xx: setting prohibited the frequency of the peripheral module clock should be lower than that of the system clock. though these bits can be set so as to make the frequency of the peripheral module clock high er than that of the system clock, the clocks will have the same frequency in reality. section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1141 of 1340 rej09b0499-0200 bit bit name initial value r/w description 3 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to. 2 1 0 bck2 bck1 bck0 0 1 0 r/w r/w r/w external bus clock (b ) select these bits select the fr equency of the external bus clock. the ratio to the input clock is as follows: bck (2:0) md_clk = 0 md_clk = 1 000: 4 2 001: 2 1 010: 1 1/2 011: 1/2 setting prohibited 1xx: setting prohibited the frequency of the external bus clock should be lower than that of the system clo ck. though these bits can be set so as to make the frequency of the external bus clock higher than that of the system clock, the clocks will have the same frequency in reality. note: x: don't care section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1142 of 1340 rej09b0499-0200 26.2 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 26.2.1 connecting crystal resonator a crystal resonator can be connected as the exam ple in figure 26.2. select the damping resistance r d according to table 26.2. an at-cut pa rallel-resonance type should be used. when providing the clock from the crystal resonator, the frequency should be in the range of 8 to 18 mhz. extal xtal r d c l2 c l1 c l1 = c l2 = 10 pf to 22 pf figure 26.2 connection of crystal resonator (example) table 26.2 damping resistance value frequency (mhz) 8 12 16 18 r d ( ) 200 0 0 0 figure 26.3 shows an equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 26.3. xtal c l at-cut parallel-resonance type extal c 0 lr s figure 26.3 crystal reso nator equivalent circuit section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1143 of 1340 rej09b0499-0200 table 26.3 crystal resonator characteristics frequency (mhz) 8 12 16 18 r s max. ( ) 80 60 50 40 c 0 max. (pf) 7 26.2.2 external clock input an external clock signal can be input as the exam ples in figure 26.4. when the xtal pin is left open, make the parasitic capacitance less than 10 pf. when the counter clock is input to the xtal pin, put the external clock in high level during standby mode. extal xtal external clock input open (a) xtal pin left open extal xtal external clock input (b) counter clock input on xtal pin figure 26.4 external clock input (examples) extal t exh t exl t exr t exf vcc 0.5 figure 26.5 external clock input timing section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1144 of 1340 rej09b0499-0200 26.3 pll circuit the pll circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 4. the frequency multiplication rate is fi xed. the phase difference is controlled so that the timing of the rising edge of the internal cloc k is the same as that of the extal pin signal. 26.4 frequency divider the frequency divider divides the pll clock to generate a 1/2, 1/4, or 1/8 clock. after the bits ick2 to ick0, pck 2 to pck0, and bck2 to bck0 are updated, this lsi operates with the updated frequency. section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1145 of 1340 rej09b0499-0200 26.5 usage notes 26.5.1 notes on clock pulse generator 1. the following points should be noted since the frequency of (i : system clock, p : peripheral module clock, b : external bus clock) supplied to each module changes according to the setting of sckcr. select a clock division ratio that is within the operation guaranteed range of clock cycle time t cyc shown in the ac timing of electrical characteristics. since i min = 8mhz, p min = 8mhz, b min = 8mhz, i max = 50 mhz, p max = 35 mhz, and b max = 50 mhz, the frequencies should satisfy the conditions 8 mhz i 50 mhz, 8 mhz p 35 mhz, and 8 mhz b 50 mhz. 2. all the on-chip peripheral modules (excep t for the exdmac, dmac, and dtc) operate on the p . note therefore that the time processing of modules such as a timer and sci differs before and after changing the clock division ratio. in addition, wait time for clearing software standby mode differs by changing the clock division ratio. for details, see section 27.7.3, setting oscillation settling time after exit from software standby mode. 3. the relationship among the system clock, peripheral module clock, and external bus clock is i p and i b . in addition, the system clock setting has the highest priority. accordingly, p or b may have the frequency set by bits ick2 to ick0 regardless of the settings of bits pck2 to pck0 or bck2 to bck0. 4. note that the frequency of will be changed in the middle of a bus cycle when setting sckcr while executing the external bus cycle with the write-data-buffer function and exdmac. 5. figure 26.6 shows the clock modification timing. after a value is written to sckcr, this lsi waits for the current bus cycle to complete. after the current bus cycle completes, each clock frequency will be modified within one cycle (worst case) of the external input clock . section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1146 of 1340 rej09b0499-0200 external clock one cycle (worst case) after the bus cycle completion operating clock specified in sckcr operating clock changed i cpu cpu cpu bus master figure 26.6 clock modification timing 26.5.2 notes on resonator since various characteristics related to the resonato r are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference. as the pa rameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit, the parameters should be determined in consultation with the resonator manu facturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin. 26.5.3 notes on board design when using the crystal resonator, place the crystal resonator and its load capacitors as close to the xtal and extal pins as possible. other signal lines should be routed away from the oscillation circuit as shown in figure 26.7 to prevent induction from interfering with correct oscillation. c l2 signal a signal b c l1 this lsi xtal extal inhibited figure 26.7 note on board design for oscillation circuit section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1147 of 1340 rej09b0499-0200 figure 26.8 shows the external circuitry re commended for the pll circuit. separate pllv cc and pllv ss from the other v cc and v ss lines at the board power supply source, and be sure to insert bypass capacitors cpb and cb close to the pins. pllv cc pllv ss v cc v ss rp: 100 cpb: 0.1 f * cb: 0.1 f * note: * cb and cpb are laminated ceramic capacitors. figure 26.8 recommended extern al circuitry for pll circuit section 26 clock pulse generator rev. 2.00 oct. 20, 2009 page 1148 of 1340 rej09b0499-0200 section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1149 of 1340 rej09b0499-0200 section 27 power-down modes functions for reduced power consumption by this lsi include a multi-clock function, module stop function, and a function for transition to power-down mode. 27.1 features ? multi-clock function the frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock. ? module stop function the functions for each peripheral module can be stopped to make a transition to a power-down mode. ? transition function to power-down mode transition to a power-down mode is possible to stop the cpu, peripheral modules, and oscillator. ? five power-down modes sleep mode all-module-clock-stop mode software standby mode deep software standby mode hardware standby mode table 27.1 shows conditions to shift to a powe r-down mode, states of the cpu and peripheral modules, and clearing method for each mode. after th e reset state, since this lsi operates in normal program execution state, the modules, other than the dmac, dtc, and exdmac are stopped. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1150 of 1340 rej09b0499-0200 table 27.1 states of operation state of operation sleep mode all-module- clock-stop mode software standby mode deep software standby mode hardware standby mode transition condition control register + instruction control register + instruction control register + instruction control register + instruction pin input cancellation method interrupt interrupt * 2 interrupt * 8 interrupt * 8 oscillator operating oper ating stopped stopped stopped cpu stopped (retained) stopped (retained) stopped (retained) stopped (undefined) stopped (undefined) on-chip ram 4 (h'ff2000 to h'ff3fff) operating (retained) stopped (retained) stopped (retained) stopped (undefined) stopped (undefined) on-chip rams 3 to 0 (h'ff4000 to h'ffbfff) operating (retained) stopped (retained) stopped (retained) stopped (retained/ undefined) * 5 stopped (undefined) universal serial bus interface operating stopped (retained) stopped (retained) stopped (retained/ undefined) * 5 stopped (undefined) watchdog timer operatin g operating stopped (retained) stopped (undefined) stopped (undefined) 8-bit timer (unit 0/1) operating operating * 4 stopped (retained) stopped (undefined) stopped (undefined) voltage detection circuit * 9 operating operat ing operating o perating stopped power-on reset circuit * 9 operating operat ing operating o perating stopped other peripheral modules operating stopped * 1 stopped * 1 stopped * 7 (undefined) stopped * 3 (undefined) i/o ports operating retained retained * 6 stopped * 6 (undefined) hi-z notes: "stopped (retained)" in the table means that the internal values are retained and internal operations are suspended. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1151 of 1340 rej09b0499-0200 "stopped (undefined)" in the table means that the internal values are undefined and the power supply for internal operations is turned off. 1. sci enters the reset state, and other peripheral modules retain their states. 2. external interrupt and some internal in terrupts (8-bit timer, watchdog timer, and 32k timer). 3. all peripheral modules enter the reset state. 4. "functioning" or "stopped" is select able through the setting of bits mstpa9 and mstpa8 in mstpcra. 5. "retained" or "undefined" of the contents of ram is select ed by the setting of the bits ramcut2 to ramcut0 in dpsbycr. 6. retention or high-impedance for the address bus and bus-control signals ( cs0 to cs7 , as , rd , hwr , and lwr ) is selected by the setti ng of the ope bit in sbycr. 7. some peripheral modules enter a state where the register values are retained. 8. an external interrupt or usb suspend/resume interrupt. 9. external interrupt and voltage monitoring interrupt * 10 . 10. supported only by the h8sx/1655m group. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1152 of 1340 rej09b0499-0200 sleep instruction * 4 sleep instruction * 4 (ssby = 1) all interrupts sleep instruction * 4 external interrupt * 2 interrupt * 1 res pin = low stby pin = high stby pin = low ssby = 0 ssby = 0, acse = 1 mstpcr = h'f[c-f]ffffff res pin = high reset state program execution state program halted state hardware standby mode sleep mode all-module-clock- stop mode software standby mode external interrupt * 3 deep software standby mode internal reset state (dpsby = 0 and no external interrupt is generated) (dpsby = 1 and no external interrupt is generated * 5 ) notes: 1. nmi, irq0 to irq11, 8-bit timer interrupt, watchdog timer interrupt, and voltage monitoring interrupt * 6 . note that the 8-bit timer interrupt is valid when the mstpcra9 or mstpcra8 bit is cleared to 0. 2. nmi, irq0 to irq11, and voltage monitoring interrupt * 6 . note that irq is valid only when the corresponding bit in ssier is set to 1. 3. nmi, irq0 -a to irq3 -a, and voltage monitoring interrupt * 6 . note that irq and voltage monitoring * 6 interrupts are valid only when the corresponding bit in dpsier is set to 1. 4. the slpie bit in sbycr is cleared to 0. 5. if a conflict between a transition to deep software standby mode and generation of software standby mode clearing source occurs, a mode transition may be made from software standby mode to program execution state through execution of interrupt exception handling. in this case, a transition to deep software standby mode is not made. for details, refer to section 27.12, usage notes. 6. supported only by the h8sx/1655m group. from any state, a transition to hardware standby mode occurs when stby is driven low. from any state except hardware standby mode, a transition to the reset state occurs when res is driven low. transition after exception handling [legend] figure 27.1 mode transitions section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1153 of 1340 rej09b0499-0200 27.2 register descriptions the registers related to the power-down modes are shown below. for details on the system clock control register (sckcr), refer to section 26.1.1, system clock control register (sckcr). ? standby control register (sbycr) ? module stop control register a (mstpcra) ? module stop control register b (mstpcrb) ? module stop control register c (mstpcrc) ? deep standby control register (dpsbycr) ? deep standby wait contro l register (dpswcr) ? deep standby interrupt enable register (dpsier) ? deep standby interrupt flag register (dpsifr) ? deep standby interrupt ed ge register (dpsiegr) ? reset status register (rstsr) ? deep standby backup register n (dpsbkrn) (n: 15 to 0) 27.2.1 standby control register (sbycr) sbycr controls software standby mode. bit bit name initial value: r/w: bit bit name initial value: r/w: 15 ssby 0 r/w 14 ope 1 r/w 13 ? 0 r/w 12 sts4 0 r/w 11 sts3 1 r/w 10 sts2 1 r/w 9 sts1 1 r/w 8 sts0 1 r/w 7 slpie 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1154 of 1340 rej09b0499-0200 bit bit name initial value r/w description 15 ssby 0 r/w software standby specifies the transition mode after executing the sleep instruction 0: shifts to sleep mode after the sleep instruction is executed 1: shifts to software standby mode after the sleep instruction is executed this bit does not change when clearing the software standby mode by using interrupts and shifting to normal operation. for clearing, write 0 to this bit. when the wdt is used in watchdog timer mode, the setting of this bit is disabled. in this case, a transition is always made to sleep mode or all-module-clock-stop mode after the sleep instruction is executed. when the slpie bit is set to 1, this bit should be cleared to 0. 14 ope 1 r/w output port enable specifies whether the output of the address bus and bus control signals ( cs0 to cs7 , as , rd , hwr , and lwr ) is retained or these lines are set to the high-z state in software standby mode or deep software standby mode. 0: in software standby mode or deep software standby mode, address bus and bus control signal lines are high-impedance. 1: in software standby mode or deep software standby mode, output states of address bus and bus control signals are retained. 13 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1155 of 1340 rej09b0499-0200 bit bit name initial value r/w description 12 11 10 9 8 sts4 sts3 sts2 sts1 sts0 0 1 1 1 1 r/w r/w r/w r/w r/w standby timer select 4 to 0 these bits select the time the mcu waits for the clock to settle when software standby mode is cleared by an interrupt. with a crystal resona tor, refer to table 27.2 and make a selection according to the operating frequency so that the standby time is at least equal to the oscillation settling time. with an external clock, a pll circuit settling time is necessary. refer to table 27.2 to set the standby time. while oscillation is being settled, the timer is counted on the p clock frequency. careful consideration is required in multi-clock mode. 00000: reserved 00001: reserved 00010: reserved 00011: reserved 00100: reserved 00101: standby time = 64 states 00110: standby time = 512 states 00111: standby time = 1024 states 01000: standby time = 2048 states 01001: standby time = 4096 states 01010: standby time = 16384 states 01011: standby time = 32768 states 01100: standby time = 65536 states 01101: standby time = 131072 states 01110: standby time = 262144 states 01111: standby time = 524288 states 1xxxx: reserved section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1156 of 1340 rej09b0499-0200 bit bit name initial value r/w description 7 slpie 0 r/w sleep instructi on exception handling enable selects whether a sleep interrupt is generated or a transition to power-down mode is made when a sleep instruction is executed. 0: a transition to power-down mode is made when a sleep instruction is executed. 1: a sleep instruction exc eption handling is generated when a sleep instruction is executed. even after a sleep instruction exception handling is executed, this bit remains set to 1. for clearing, write 0 to this bit. 6 to 0 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. [legend] x: don't care note: with the f-ztat version, the flash memory settling time must be reserved. 27.2.2 module stop control registers a and b (mstpcra and mstpcrb) mstpcra and mstpcrb control module stop state. setting a bit to 1 makes the corresponding module enter module stop state, while cleari ng the bit to 0 clears module stop state. ? mstpcra bit bit name initial value: r/w: bit bit name initial value: r/w: 15 acse 0 r/w 14 mstpa14 0 r/w 13 mstpa13 0 r/w 12 mstpa12 0 r/w 11 mstpa11 1 r/w 10 mstpa10 1 r/w 9 mstpa9 1 r/w 8 mstpa8 1 r/w 7 mstpa7 1 r/w 6 mstpa6 1 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1157 of 1340 rej09b0499-0200 ? mstpcrb bit bit name initial value: r/w: bit bit name initial value: r/w: 15 mstpb15 1 r/w 14 mstpb14 1 r/w 13 mstpb13 1 r/w 12 mstpb12 1 r/w 11 mstpb11 1 r/w 10 mstpb10 1 r/w 9 mstpb9 1 r/w 8 mstpb8 1 r/w 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w 0 mstpb0 1 r/w ? mstpcra bit bit name initial value r/w module 15 acse 0 r/w all-module-clock-stop mode enable enables/disables all-module- clock-stop state for reducing current consumption by stopping the bus controller and i/o ports operations when t he cpu executes the sleep instruction after module stop state has been set for all the on-chip peripheral modules controlled by mstpcr. 0: all-module-clock-stop mode disabled 1: all-module-clock-stop mode enabled 14 mstpa14 0 r/w exdma controller (exdmac) 13 mstpa13 0 r/w dma controller (dmac) 12 mstpa12 0 r/w data transfer controller (dtc) 11 10 mstpa11 mstpa10 1 1 r/w r/w reserved these bits are always read as 1. the write value should always be 1. 9 mstpa9 1 r/w 8-bit timer (tmr_3 and tmr_2) 8 mstpa8 1 r/w 8-bit timer (tmr_1 and tmr_0) 7 6 mstpa7 mstpa6 1 1 r/w r/w reserved these bits are always read as 1. the write value should always be 1. 5 mstpa5 1 r/w d/a converter (channels 1 and 0) section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1158 of 1340 rej09b0499-0200 bit bit name initial value r/w module 4 mstpa4 1 r/w reserved this bit is always read as 1. the write value should always be 1. 3 mstpa3 1 r/w a/d converter (unit 0) 2 mstpa2 1 r/w reserved this bit is always read as 1. the write value should always be 1. 1 mstpa1 1 r/w 16-bit timer pulse unit (tpu channels 11 to 6) 0 mstpa0 1 r/w 16-bit timer pulse unit (tpu channels 5 to 0) ? mstpcrb bit bit name initial value r/w module 15 mstpb15 1 r/w programmable pulse generator (ppg_0: po7 to po0) 14 13 mstpb14 mstpb13 1 1 r/w r/w reserved these bits are always read as 1. the write value should always be 1. 12 mstpb12 1 r/w serial communications interface_4 (sci_4) 11 mstpb11 1 r/w reserved this bit is always read as 1. the write value should always be 1. 10 mstpb10 1 r/w serial communications interface_2 (sci_2) 9 mstpb9 1 r/w serial communications interface_1 (sci_1) 8 mstpb8 1 r/w serial communications interface_0 (sci_0) 7 mstpb7 1 r/w i 2 c bus interface 2_1 (iic2_1) 6 mstpb6 1 r/w i 2 c bus interface 2_0 (iic2_0) 5 mstpb5 1 r/w user break controller (ubc) 4 3 2 1 0 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 1 1 1 1 1 r/w r/w r/w r/w r/w reserved these bits are always read as 1. the write value should always be 1. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1159 of 1340 rej09b0499-0200 27.2.3 module stop control register c (mstpcrc) when bits mstpc5 to mstpc0 are set to 1, the corresponding on-chip ram stops. do not set the corresponding mstpc5 to mstpc0 bits to 1 while accessing the on-chip ram. do not access the on-chip ram while bits ms tpc5 to mstpc0 are set to 1. the serial communications interfaces, 8-bit ti mers, universal serial bus interface (usb), crc calculator, 10-bit a/d converter, and programmable pulse generator (ppg: po31 to po16) are placed in the module stop state by using th e mstpc15 and mstpc14, mstpc13 and mstpc12, mstpc11, mstpc10, mstpc9, and mstpc8 bits, respectively. bit bit name initial value: r/w: bit bit name initial value: r/w: 15 mstpc15 1 r/w 14 mstpc14 1 r/w 13 mstpc13 1 r/w 12 mstpc12 1 r/w 11 mstpc11 1 r/w 10 mstpc10 1 r/w 9 mstpc9 1 r/w 8 mstpc8 1 r/w 7 mstpc7 0 r/w 6 mstpc6 0 r/w 5 mstpc5 0 r/w 4 mstpc4 0 r/w 3 mstpc3 0 r/w 2 mstpc2 0 r/w 1 mstpc1 0 r/w 0 mstpc0 0 r/w bit bit name initial value r/w module 15 mstpc15 1 r/w serial communicat ions interface_5 (sci_5), (irda) 14 mstpc14 1 r/w serial communications interface_6 (sci_6) 13 mstpc13 1 r/w 8-bit timer (tmr_4, tmr_5) 12 mstpc12 1 r/w 8-bit timer (tmr_6, tmr_7) 11 mstpc11 1 r/w universal serial bus interface (usb) 10 mstpc10 1 r/w cyclic redundancy check calculator 9 mstpc9 1 r/w a/d converter (unit 1) 8 mstpc8 1 r/w programmable pulse generator (ppg_1: po31 to po16) section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1160 of 1340 rej09b0499-0200 bit bit name initial value r/w module 7 6 mstpc7 mstpc6 0 0 r/w r/w reserved always set the mstpc7 and mstpc6 bits to the same value. 5 4 mstpc5 mstpc4 0 0 r/w r/w on-chip ram 4 (h'ff2000 to h'ff3fff) always set the mstpc5 and mstpc4 bits to the same value. 3 2 mstpc3 mstpc2 0 0 r/w r/w on-chip ram_3, 2 (h'ff4000 to h'ff7fff) always set the mstpc3 and mstpc2 bits to the same value. 1 0 mstpc1 mstpc0 0 0 r/w r/w on-chip ram_1, 0 (h'ff8000 to h'ffbfff) always set the mstpc1 and mstpc0 bits to the same value. 27.2.4 deep standby contro l register (dpsbycr) dpsbycr controls deep software standby mode. dpsbycr is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 dpsby 0 r/w 6 iokeep 0 r/w 5 ramcut2 0 r/w 4 ramcut1 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ramcut0 1 r/w section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1161 of 1340 rej09b0499-0200 bit bit name initial value r/w module 7 dpsby 0 r/w deep software standby when the ssby bit in sbycr has been set to 1, executing the sleep instructi on causes a transition to software standby mode. at this time, if there is no source to clear software standby mode and this bit is set to 1, a transition to deep software standby mode is made. ssby dpsby entry to 0 x enters sleep mode after execution of a sleep instruction. 1 0 enters software standby mode after execution of a sleep instruction. 1 1 enters deep software standby mode after execution of a sleep instruction. when deep software standby mode is canceled due to an interrupt, this bit remains at 1. write a 0 here to clear it. setting of this bit has no effect when the wdt is used in watchdog timer mode. in this case, executing the sleep instruction always initiates entry to sleep mode or all- module-clock-stop mode. be sure to clear this bit to 0 when setting the slpie bit to 1. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1162 of 1340 rej09b0499-0200 bit bit name initial value r/w module 6 iokeep 0 r/w i/o port retention in deep software standby mode, the ports retain the states that were held in software standby mode. this bit specifies whether or not the state that has been held in deep software standby mode is retained after exit from deep software standby mode. iokeep pin state 0 the retained port states are released simultaneously with exit from deep software standby mode. 1 the retained port states are released when a 0 is written to this bit following exit from deep software standby mode. in operation in external extended mode, however, the address bus, bus control signals ( cs0 , as , rd , hwr , and lwr ), and data bus are set to the initial state upon exit from deep software standby mode. 5 ramcut2 0 r/w on-chip ram power off 2 ramcut 2, 1, and 0 control the internal power supply to the on-chip ram and usb in deep software standby mode. for details, see descriptions of the ramcut0 bit. 4 ramcut1 0 r/w on-chip ram power off 1 ramcut 2, 1, and 0 control the internal power supply to the on-chip ram and usb in deep software standby mode. for details, see descriptions of the ramcut0 bit. 3 to 1 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 0 ramcut0 1 r/w on-chip ram power off 0 ramcut 2, 1, and 0 control the internal power supply to the on-chip ram and usb in deep software standby mode. ramcut 2 to 0 000: power is supplied to the on-chip ram and usb. 111: power is not supplied to the on-chip ram and usb. settings other than above are prohibited. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1163 of 1340 rej09b0499-0200 27.2.5 deep standby wait control register (dpswcr) dpswcr selects the time for which the mcu waits until the clock settles when deep software standby mode is canceled by an interrupt. dpswcr is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 ? 0 r/w 6 ? 0 r/w 5 wtsts5 0 r/w 4 wtsts4 0 r/w 3 wtsts3 0 r/w 2 wtsts2 0 r/w 1 wtsts1 0 r/w 0 wtsts0 0 r/w bit bit name initial value r/w module 7, 6 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1164 of 1340 rej09b0499-0200 bit bit name initial value r/w module 5 to 0 wtsts [5:0] 0 r/w deep software standby wait time setting these bits select the time for which the mcu waits until the clock settles when deep software standby mode is canceled by an interrupt. when using a crystal resonator, see table 27.3 and select the wait time greater than the oscillation settling time for each operating frequency. when using an external clock, settling time for the pll circuit should be considered. see table 27.3 to select the wait time. during the oscillation settling period, counting is performed with the clock frequency input to the extal. 000000: reserved 000001: reserved 000010: reserved 000011: reserved 000100: reserved 000101: wait time = 64 states 000110: wait time = 512 states 000111: wait time = 1024 states 001000: wait time = 2048 states 001001: wait time = 4096 states 001010: wait time = 16384 states 001011: wait time = 32768 states 001100: wait time = 65536 states 001101: wait time = 131072 states 001110: wait time = 262144 states 001111: wait time = 524288 states 01xxxx: reserved [legend] x: don't care section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1165 of 1340 rej09b0499-0200 27.2.6 deep standby interrupt en able register (dpsier) dpsier enables or disables interrupts to clear deep software standby mode. dpsier is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 ? 0 r/w 6 dusbie 0 r/w 5 ? 0 r/w 4 dlvdie * 0 r/w 3 dirq3e 0 r/w 2 dirq2e 0 r/w 1 dirq1e 0 r/w 0 dirq0e 0 r/w note: * supported only by the h8sx/1655m group. bit bit name initial value r/w module 7 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. 6 dusbie 0 r/w usb suspend/resume interrupt enable enables/disables exit from deep software standby mode by the usb suspend/resume interrupt signal. 0: disables exit from deep so ftware standby mode by the usb suspend/resume interrupt signal. 1: enables exit from deep so ftware standby mode by the usb suspend/resume interrupt signal. 5 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. 4 dlvdie * 0 r/w lvd interrupt enable enables/disables exit from deep software standby mode by the voltage monitoring interrupt signal. 0: disables exit from deep so ftware standby mode by the voltage monitoring interrupt signal. 1: enables exit from deep so ftware standby mode by the voltage monitoring interrupt signal. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1166 of 1340 rej09b0499-0200 bit bit name initial value r/w module 3 dirq3e 0 r/w irq3 interrupt enable enables or disables exit from deep software standby mode by irq3 -a. 0: disables exit from deep software standby mode by irq3 -a. 1: enables exit from deep software standby mode by irq3 -a . 2 dirq2e 0 r/w irq2 interrupt enable enables or disables exit from deep software standby mode by irq2 -a. 0: disables exit from deep software standby mode by irq2 -a 1: enables exit from deep software standby mode by irq2 -a 1 dirq1e 0 r/w irq1 interrupt enable enables or disables exit from deep software standby mode by irq1 -a. 0: disables exit from deep software standby mode by irq1 -a. 1: enables exit from deep software standby mode by irq1 -a . 0 dirq0e 0 r/w irq0 interrupt enable enables or disables exit from deep software standby mode by irq0 -a. 0: disables exit from deep software standby mode by irq0- a. 1: enables exit from deep software standby mode by irq0 -a. note: * supported only by the h8sx/1655m group. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1167 of 1340 rej09b0499-0200 27.2.7 deep standby interrupt flag register (dpsifr) dpsifr is used to request an exit from deep so ftware standby mode. when the interrupt specified in dpsiegr is generated, the applicable bit in dpsifr is set to 1. the bit is set to 1 even when an interrupt is generated in the modes other than deep software standby. therefore, a transition to deep software standby should be made after this regi ster bits are cleared to 0. dpsifr is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 dnmif 0 r/(w) * 1 6 dusbif 0 r/(w) * 1 5 ? 0 r 4 dlvdif * 2 0 r/(w) * 1 3 dirq3f 0 r/(w) * 1 2 dirq2f 0 r/(w) * 1 1 dirq1f 0 r/(w) * 1 0 dirq0f 0 r/(w) * 1 notes: 1. only 0 can be written to clear the flag. 2. supported only by the h8sx/1655m group. bit bit name initial value r/w module 7 dnmif 0 r/(w) * 1 nmi flag [setting condition] nmi input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. 6 dusbif 0 r/(w) * 1 usb suspend/resume interrupt flag [setting condition] when the usb suspend/resume interrupt occurs. [clearing condition] writing a 0 to this bit after reading it as 1. 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 dlvdif * 2 0 r/(w) * 1 lvd interrupt flag [setting condition] voltage monitoring interrupt is generated. [clearing condition] writing a 0 to this bit after reading it as 1. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1168 of 1340 rej09b0499-0200 bit bit name initial value r/w module 3 dirq3f 0 r/(w) * 1 irq3 interrupt flag [setting condition] irq3 -a input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. 2 dirq2f 0 r/(w) * 1 irq2 interrupt flag [setting condition] irq2 -a input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. 1 dirq1f 0 r/(w) * 1 irq1 interrupt flag [setting condition] irq1 -a input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. 0 dirq0f 0 r/(w) * 1 irq0 interrupt flag [setting condition] irq0 -a input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. notes: 1. only 0 can be wr itten to clear the flag. 2. supported only by the h8sx/1655m group. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1169 of 1340 rej09b0499-0200 27.2.8 deep standby interrupt edge register (dpsiegr) dpsiegr selects the rising or falling edge to clear deep software standby mode. dpsiegr is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 dnmieg 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 dirq3eg 0 r/w 2 dirq2eg 0 r/w 1 dirq1eg 0 r/w 0 dirq0eg 0 r/w bit bit name initial value r/w module 7 dnmieg 0 r/w nmi edge select selects the active edge for nmi pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. 6 to 4 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 3 dirq3eg 0 r/w irq3 interrupt edge select selects the active edge for irq3 -a pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. 2 dirq2eg 0 r/w irq2 interrupt edge select selects the active edge for irq2 -a pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. 1 dirq1eg 0 r/w irq1 interrupt edge select selects the active edge for irq1 -a pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1170 of 1340 rej09b0499-0200 bit bit name initial value r/w module 0 dirq0eg 0 r/w irq0 interrupt edge select selects the active edge for irq0 -a pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. 27.2.9 reset status register (rstsr) the dpsrstf bit in rstsr indicates that deep software standby mo de has been canceled by an interrupt. rstsr is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 dpsrstf 0 r/(w) * 1 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 lvdf * 2 0 * 3 r/w * 4 1 ? 0 * 3 r/w 0 porf * 2 0 * 3 r/w * 5 notes: 1. only 0 can be written to clear the flag. 2. supported only by the h8sx/1655m group. 3. initial value is undefined in the h8sx/1655m group. 4. only 0 can be written to clear the flag in the h8sx/1655m group. 5. readable only in the h8sx/1655m group. bit bit name initial value r/w module 7 dpsrstf 0 r/(w) * deep software standby reset flag indicates that deep software standby mode has been canceled by an interrupt source specified in dpsier or dpsiegr and an internal reset is generated. [setting condition] deep software standby mode is canceled by an interrupt source. [clearing condition] writing a 0 to this bit after reading it as 1. 6 to 3 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1171 of 1340 rej09b0499-0200 ? h8sx/1655 group bit bit name initial value r/w module 2 to 0 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. ? h8sx/1655m group bit bit name initial value r/w module 2 lvdf undefined r/(w) * lvd flag this bit indicates that the voltage-detection circuit has detected a low voltage (vcc at or below vdet). for details, see section 5, voltage detection circuit (lvd). 1 ? undefined r/w reserved these bits are always read as 0. the write value should always be 0. 0 porf undefined r power-on reset flag this bit indicates that a power-on reset has been generated. for details, see section 4, reset. note: * only 0 can be written to clear the flag. 27.2.10 deep standby backup register (dpsbkrn) dpsbkrn (n = 15 to 0) is a 16-bit readable/writable register to store data during deep software standby mode. although data in on-chip ram is not retained in de ep software standby mode, data in this register is retained. dpsbkrn (n = 15 to 0) is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 bkupn7 0 r/w 6 bkupn6 0 r/w 5 bkupn5 0 r/w 4 bkupn4 0 r/w 3 bkupn3 0 r/w 2 bkupn2 0 r/w 1 bkupn1 0 r/w 0 bkupn0 0 r/w n: 15 to 0 section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1172 of 1340 rej09b0499-0200 27.3 multi-clock function when bits ick2 to ick0, pck2 to pck0, and bck2 to bck0 in sckcr are set, the clock frequency is changed at the end of the bus cy cle. the cpu and bus ma sters operate on the operating clock specified by bits ick2 to ick0. the peripheral modules operate on the operating clock specified by bits pck2 to pck0. the extern al bus operates on the operating clock specified by bits bck2 to bck0. even if the frequencies specified by bits pck2 to pck0 and bck2 to bck0 are higher than the frequency specified by bits ick2 to ick0, the specified values are not reflected in the peripheral module and external bus clocks. the peripheral module and external bus clocks are restricted to the operating clock specified by bits ick2 to ick0. 27.4 module stop state module stop functionality can be set for individual on-chip peripheral modules. when the corresponding mstp bit in mstpcra , mstpcrb, or mstpcrc is set to 1, module operation stops at the end of the bus cycle and a transition is made to a module stop state. the cpu continues operating independently. when the corresponding mstp bit is cleared to 0, a module stop state is cleared and the module starts operating at the end of the bus cycle. in a module stop state, the internal states of modules other than the sci are retained. after the reset state is cleared, all modules other than the exdmac, dmac, and dtc and on- chip ram are placed in a module stop state. the registers of the module for which the module stop state is selected cannot be read from or written to. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1173 of 1340 rej09b0499-0200 27.5 sleep mode 27.5.1 entry to sleep mode when the sleep instruction is executed when th e ssby bit in sbycr is 0, the cpu enters sleep mode. in sleep mode, cpu operation stops but the contents of the cpu's internal registers are retained. other peripheral functions do not stop. 27.5.2 exit from sleep mode sleep mode is exited by any interrupt, signals on the res or stby pin, and a reset caused by a watchdog timer overflow, a voltage monitoring reset*, or a power-on reset*. ? exit from sleep mode by interrupt when an interrupt occurs, sleep mode is exited and interrupt exception processing starts. sleep mode is not exited if the interrupt is disabled, or interrupts other than nmi are masked by the cpu. ? exit from sleep mode by res pin setting the res pin level low selects the reset state. after the stipulated reset input duration, driving the res pin high makes the cpu start the reset exception processing. ? exit from sleep mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode. ? exit from sleep mode by reset caused by watchdog timer overflow sleep mode is exited by an internal re set caused by a watchdog timer overflow. ? exit from voltage monitoring reset* sleep mode is exited by a voltage monitori ng reset of the voltage detection circuit. ? exit from power-on reset* sleep mode is exited by a power-on reset. note: * supported only by the h8sx/1655m group. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1174 of 1340 rej09b0499-0200 27.6 all-module-clock-stop mode when the acse bit is set to 1 and all mo dules controlled by mstpcra and mstpcrb are stopped (mstpcra, mstpcrb = h'ff ffffff), or all modules except for the 8-bit timer (units 0 and 1) are stopped (mstpcra, mstpcrb = h'f[c to f]ffffff), executing a sleep instruction with the ssby bit in sbycr cleared to 0 will cause all modules (except for the 8-bit timer* 1 , watchdog timer, power-on reset circuit* 2 , and voltage detection circuit* 2 ) the bus controller, and the i/o ports to stop operating, an d to make a transition to all-module-clock-stop mode at the end of the bus cycle. when power consumption should be reduced ever more in all-module-clock-stop mode, stop modules controlled by mstp crc (mstpcrc[15:8] = h'ffff). all-module-clock-stop mode is cleared by an external interrupt (nmi or irq0 to irq11 pins), res pin input, or an internal interrupt (8-bit timer* 1 , watchdog timer, and voltage detection circuit* 2 ), and the cpu returns to the normal prog ram execution state via the exception handling state. all-module-clock-stop mode is not cleared if interrupts are disabled, if interrupts other than nmi are masked on the cpu side, or if the releva nt interrupt is designated as a dtc activation source. when the stby pin is driven low, a transition is made to hardware standby mode. notes: 1. operation or stopping of the 8-bit timer can be selected by bits mstpa9 and mstpa8 in mstpcra. 2. supported only by the h8sx/1655m group. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1175 of 1340 rej09b0499-0200 27.7 software standby mode 27.7.1 entry to software standby mode if a sleep instruction is executed when the ssby bit in sbycr is set to 1 and the dpsby bit in dpsbycr is cleared to 0, software standby mode is entered. in this mode, the cpu, on-chip peripheral functions, and oscillator all stop. however, the contents of the cpu's internal registers, on-chip ram data, and the states of on-chip peripheral functions other than the sci, and the states of the i/o ports, are retained. whether the addr ess bus and bus control si gnals are placed in the high-impedance state or retain th e output state can be specified by the ope bit in sbycr. in this mode the oscillator stops, allowing power consumption to be significantly reduced. if the wdt is used in watchdog timer mode, it is impossible to make a transition to software standby mode. the wdt should be stopped before the sleep instruction execution. 27.7.2 exit from software standby mode software standby mode is cleared by an external interrupt (nmi or irq0 to irq11* 1 ) or an internal interrupt (voltage monitoring interrupt * 2 or usb suspend/resume), a voltage monitoring reset* 2 , a power-on reset* 2 or by means of the res pin or stby pin. 1. exit from software standby mode by interrupt when an nmi, irq0 to irq11* 1 , or usb suspend/resume interr upt request signal is input, clock oscillation starts, and after the elapse of the time set in bits sts4 to sts0 in sbycr, stable clocks are supplied to the entire lsi, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq11* 1 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq11* 1 is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side or has been designated as a dtc activation source. 2. exit from voltage monitoring reset* 2 when a voltage monitoring reset is generated by the fall of power-voltage, software standby mode is cleared and a clock oscillation starts. at the same time, a clock signal is supplied throughout the lsi. after that, if power voltage rises, the voltage detection reset is released while the clock oscillation stabilization time is well kept. thereafter, cpu starts the reset exception handling. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1176 of 1340 rej09b0499-0200 3. exit from power-on reset* 3 when a power-on reset is generated by the fall of power voltage, software standby mode is released. after that, if power volt age rises, the clock oscillation st arts and the power-on reset is released while the clock oscillat ion stabilization time is well kept. thereafter cpu starts the reset exception handling. 4. exit from software standby mode by res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire lsi. note that the res pin must be held low until clock oscillation settles. when the res pin goes high, the cpu begins reset exception handling. 5. exit from software standby mode by stby pin when the stby pin is driven low, a transition is made to hardware standby mode. notes: 1. by setting the ssin bit in ssier to 1, irq0 to irq11 can be used as a software standby mode clearing source. 2. supported only by the h8sx/1655m group. 27.7.3 setting oscillation settling time after exit from software standby mode bits sts4 to sts0 in sbycr should be set as described below. 1. using a crystal resonator set bits sts4 to sts0 so that the standby time is at least equal to the oscillation settling time. table 27.2 shows the standby times for operating frequencies and settings of bits sts4 to sts0. 2. using an external clock a pll circuit settling time is necessary. refer to table 27.2 to set the standby time. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1177 of 1340 rej09b0499-0200 table 27.2 oscillation settling time setting p * (mhz) sts4 sts3 sts2 sts1 sts0 standby time 35 25 20 13 10 8 unit 0 reserved ? ? ? ? ? ? 0 1 reserved ? ? ? ? ? ? 0 reserved ? ? ? ? ? ? 0 1 1 reserved ? ? ? ? ? ? 0 reserved ? ? ? ? ? ? 0 1 64 1.8 2.6 3. 2 4.9 6.4 8.0 0 512 14.6 20.5 25. 6 39.4 51.2 64.0 0 1 1 1 1024 29.3 41.0 51.2 78.8 102.4 128.0 0 2048 58.5 81.9 102.4 157.5 204.8 256.0 s 0 1 4096 0.12 0.16 0.20 0.32 0.41 0.51 0 16384 0.47 0.66 0.82 1.26 1.64 2.05 0 1 1 32768 0.94 1.31 1.64 2.52 3.28 4.10 0 65536 1.87 2.62 3.28 5.04 6.55 8.19 0 1 131072 3.74 5.24 6.55 10.08 13.11 16.38 0 262144 7.49 10.49 13.11 20.16 26.21 32.77 0 1 1 1 1 524288 14.98 20.97 26.21 40. 33 52.43 65.54 1 0 0 0 0 reserved ? ? ? ? ? ? ms [legend] : recommended setting when external clock is in use : recommended setting when crystal oscillator is in use note: * p is the output from the peripheral module frequency divider. the oscillation settling time, which includes a period where the oscillation by an oscillator is not stable, depends on the resonator characteristics. the above figures are for reference. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1178 of 1340 rej09b0499-0200 27.7.4 software standby mode application example figure 27.2 shows an example in which a transiti on is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interr upt is accepted with the nmieg bit in intcr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, cau sing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. oscillator i nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down mode) oscillation settling time t osc2 nmi exception handling figure 27.2 software standby mode application example section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1179 of 1340 rej09b0499-0200 27.8 deep software standby mode 27.8.1 entry to deep software standby mode if a sleep instruction is executed when the ssby bit in sbycr has been set to 1, a transition to software standby mode is made. in this state, if the cpsby bit in dpsbycr is set to 1, a transition to deep software standby mode is made. if a software standby mode clearing source (an nmi, irq0 to irq11, voltage-monitoring interrupt requests*, or usb suspend/resume) occurs when a transition to software standby mode is made, software standby mode will be cleared regardle ss of the dpsby bit setting, and the interrupt exception handling starts after the oscillation settli ng time for software standby mode specified by the bits sts4 to sts0 in sbycr has elapsed. when both of the ssby bit in sbycr and the cpsby bit in dpsbycr are set to 1 and no software standby mode clearing source occurs, a transition to deep software standby mode will be made immediately after software standby mode is entered. in deep software standby mode, the cpu, on-chi p peripheral functions (except for the usb), on- chip ram 4, and oscillator functionality are all halted. in addition, the internal power supply to these modules stops, resulting in a significant reduction in power consumption. at this time, the contents of all the registers of the cpu, on-chip peripheral functions (except for the usb), and on- chip ram 4 become undefined. contents of the on-chip rams 3 to 0 and usb registers can be retained when all the bits ramcut2 to ramcut0 in dpsbycr have been cleared to 0. if these bits are set to all 1, the internal power supply to the on-chip rams 3 to 0 and usb stops and the power consumption is further reduced. at this time, the contents of the on-chip rams 3 to 0 and usb registers become undefined. the voltage detection circuit*, and power-on reset circuit* can operate in deep software standby mode. the i/o ports can be retained in the sa me state as in software standby mode. note: * supported only by the h8sx/1655m group. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1180 of 1340 rej09b0499-0200 27.8.2 exit from deep software standby mode exit from deep software standby mode is initiated by signals on the external interrupt pins (nmi and irq0 -a to irq3 -a), internal interrupt signals (v oltage-monitoring interrupt* and usb suspend/resume), voltage-monitoring reset*, power-on reset*, res pin, or stby pin. 1. exit from deep software standby mode by external interrupt pins or internal interrupt signals deep software standby mode is canceled when any of the dnmif, dirqnf (n = 3 to 0), and dusbif bits in dpsifr is set to 1. the dnmif or dirqnf (n = 3 to 0) bit is set to 1 when a specified edge is generated on the nmi pin or irq0 -a to irq3 -a pins, that have been enabled by the dirqne (n = 3 to 0) bit in dpsier. the rising or falling edge of the signals can be specified with dpsiegr. the dlvdif bit is set to 1 when a voltage-monitoring interrupt occurs. the dusbif bit is set to 1 when a usb suspend/resume interrupt occurs. when deep software standby mode clearing source is generated, internal power supply starts simultaneously with the start of clock oscillation, and internal reset signal is generated for the entire lsi. once the time specified by the wtst s5 to wtsts0 bits in dpswcr has elapsed, a stable clock signal is being supplied throughout the lsi and the internal reset is cleared. deep software standby mode is canceled on clear ing of the internal reset, and then the reset exception handling starts. when deep software standby mode is canceled by an external interrupt pi n or internal interrupt signal, the dpsrstf bit in rstsr is set to 1. 2. exit from deep software standby mode by a voltage-monitoring reset* when a voltage monitoring reset is generated by the power-supply voltage falling, the lsi is released from deep software st andby mode and internal power supply starts simultaneously with the start of clock oscillation. at the same time, a clock signal is supplied throughout the lsi. when the power-supply voltage has risen sufficiently, the lsi is released from the voltage-detection reset state after the clock oscillation stabilization time has been secured. the cpu then starts reset-exception handling. 3. exit from power-on reset* when a power-on reset is generated by the power-supply voltage falling, the lsi is released from deep software standby mode. if the power-supply voltage then rises sufficiently, clock oscillation starts and the lsi is released fro m the power-on reset state after the clock oscillation stabilization time has been secured. as soon as the clock oscillation starts, the clock signal is provided to the lsi. the internal power supply restarts during the power-on reset time. after release from the power-on reset st ate, the cpu starts reset-exception handling. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1181 of 1340 rej09b0499-0200 4. exit from deep software standby mode by the signal on the res pin clock oscillation and internal power supply start as soon as the signal on the res pin is driven low. at the same time, clock signals are supplied to the lsi. in this case, the res pin has to be held low until the clock oscillation has become stable. once the signal on the res pin is driven high, the cpu starts reset exception handling. 5. exit from deep software standby mode by the signal on the stby pin when the stby pin is driven low, a transition is made to hardware standby mode. note: * supported only by the h8sx/1655m group. 27.8.3 pin state on exit from deep software standby mode in deep software standby mode, the ports retain th e states that were held during software standby mode. the internal of the lsi is initialized by an internal reset caused by deep software standby mode, and the reset exception handling starts as soon as deep software standby mode is canceled. the following shows the port states at this time. (1) pins for address bus, bus control and data bus pins for the address bus, bus control signals ( cs0 , as , hwr , and lwr ), and data bus operate depending on the cpu. (2) pins other than address bus, bus control and data bus pins whether the ports are initialized or retain the states that were held during software standby mode can be selected by the iokeep bit. ? when iokeep = 0 ports are initialized by an internal reset caused by deep software standby mode. ? when iokeep = 1 the port states that were held in deep software standby mode are retained regardless of the lsi internal state though the internal of the lsi is initialized by an internal reset caused by deep software standby mode. at this time, the port st ates that were held in software standby mode are retained even if settings of i/o ports or peripheral modules are set. subsequently, the retained port states are released when the iokeep bit is cleared to 0 and operation is performed according to the internal settings. the iokeep bit is not initialized by an internal reset caused by canceling deep standby mode. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1182 of 1340 rej09b0499-0200 27.8.4 b operation after exit from deep software standby mode when the iokeep bit is 0, b output is undefined for a maximum of one cycle immediately after exit from deep software standby mode. at this time, the output state cannot be guaranteed. even when the iokeep bit is set to 1, b output is undefined for a maximum of one cycle immediately after the iokeep bit is cleared to 0 after de ep software standby mode was canceled, and the output state cannot be guaranteed. (see figure 27.3) however, clock can be normally output by canceling deep software standby mode with the iokeep bit set to 1 and then controlling the b output with the iokeep and pstop1 bits. use the following procedure. 1. change the value of the pstop1 bit from 0 to 1 to fix the b output at the high level (given that the b output was already fixed high). 2. clear the iokeep bit to 0 to end retention of the b state. 3. clear the pstop1 b it to 0 to enable b output. for the port state when the iokeep bit is set to 1, see section 27.8.3, pin state on exit from deep software standby mode. deep software standby mode oscillator nmi internal reset i clock is undefined iokeep cleared pstop1 set iokeep cleared pstop1 cleared when iokeep = 1, the clock can be normally output by using the pstop1 bit. b when iokeep = 0 when iokeep = 1 (iokeep=1) b (1) b output cannot be guaranteed. (2) the procedure to guarantee b output is used. figure 27.3 b operation after exit from deep software standby mode section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1183 of 1340 rej09b0499-0200 27.8.5 setting oscillation settling time after ex it from deep soft ware standby mode the wtsts5 to wtsts0 bits in dpswcr should be set as follows: 1. using a crystal resonator specify the wtsts5 to wtsts0 bits so that the standby time is at least equal to the oscillation settling time. table 27.3 shows extal input clock frequencies and the standby time according to wtsts5 to wtsts0 settings. 2. using an external clock the pll circuit settling time should be consider ed. see table 27.3 to set the standby time. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1184 of 1340 rej09b0499-0200 table 27.3 oscillation settling time settings extal input clock frequency * (mhz) wt sts5 wt sts4 wt sts3 wt sts2 wt sts1 wt sts0 standby time 18 16 14 12 10 8 unit 0 reserved ? ? ? ? ? ? 0 1 reserved ? ? ? ? ? ? 0 reserved ? ? ? ? ? ? 0 1 1 reserved ? ? ? ? ? ? 0 reserved ? ? ? ? ? ? 0 1 64 3.6 4.0 4. 6 5.3 6.4 8.0 0 512 28.4 32.0 36.6 42.7 51.2 64.0 0 1 1 1 1024 56.9 64.0 73.1 85.3 102.4 128.0 0 2048 113.8 128.0 146.3 170.7 204.8 256.0 s 0 1 4096 0.23 0.26 0.29 0.34 0.41 0.51 0 16384 0.91 1.02 1.17 1.37 1.64 2.05 0 1 1 32768 1.82 2.05 2.34 2.73 3.28 4.10 0 65536 3.64 4.10 4.68 5.46 6.55 8.19 0 1 131072 7.28 8.19 9.36 10.92 13.11 16.38 0 262144 14.56 16.38 18.72 21.85 26.21 32.77 0 1 1 1 1 524288 29.13 32.77 37.45 43.69 52.43 65.54 0 1 0 0 0 0 reserved ? ? ? ? ? ? ms [legend] : recommended setting when external clock is in use : recommended setting when crystal oscillator is in use note: * the oscillation settling time, which incl udes a period where the oscillation by an oscillator is not stable, depends on the resonator characteristics. the above figures are for reference. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1185 of 1340 rej09b0499-0200 27.8.6 deep software standby mo de application example (1) transition to and exit from deep software standby mode figure 27.4 shows an example where the transition to deep software standby mode is initiated by a falling edge on the nmi pin and exit from deep software standby mode is initiated by a rising edge on the nmi pin. in this example, falling-edge sensing of nmi interrupts has been specified by clearing the nmieg bit in intcr to 0 (not shown). after an nmi interrupt has been sensed, rising-edge sensing is specified by setting the dnmieg bit to 1, the ssby and dpsby bits are set to 1, and the transition to deep software standby mode is triggered by execution of a sleep instruction. after that, deep software standby mode is ca nceled at the rising edge on the nmi pin. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1186 of 1340 rej09b0499-0200 oscillator i nmi dnmieg bit dpsby bit nmi exception handling dnmieg = 1 ssby = 1 dpsby = 1 sleep instruction deep software standby mode (power-down mode) reset exception handling internal reset oscillation settling time iokeep bit dpsrstf flag operated retained operated i/o port cleared cleared cleared set nmi interrupt set dnmi interrupt becomes invalid by an internal reset set set set figure 27.4 deep software standby mode application example (iokeep = 1) section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1187 of 1340 rej09b0499-0200 (2) deep software standby mode in ex ternal extended mode (iokeep = 1) figure 27.5 shows an example of operations in deep standby mode when the iokeep and ope bits are set to 1 in external extended mode. in this example, deep software standby mode is entered with the iokeep and ope bits set to 1, and then exited at the rising edge of the nmi pin. in external expansion mode, while the iokeep bit is set to 1, retention of the states of pins for the address bus, bus-control signals ( cs0 , as , rd , hwr , and lwr ), data bus is released after the oscillation settling time has elapsed. for other pins, including the b output pin, retention is released when the iokeep bit is cleared to 0, and then they are set according to the i/ o port or peripher al module settings. oscillator i nmi sleep instruction deep software standby mode (power-down mode) program execution state program execution state reset exception handling oscillation settling time internal reset operated retained address retained bus control retained data b retained pstop1 set pstop1 cleared iokeep cleared retained i/o other than above started from h'00000 operated operated operated operated operated figure 27.5 example of deep so ftware standby mode operation in external extended mode (iokeep = ope = 1) section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1188 of 1340 rej09b0499-0200 (3) deep software standby mode in ex ternal extended mode (iokeep = 0) figure 27.6 shows an example of operations in deep software standby mode with the iokeep bit is set to 1 and the ope bit is cleared to 0 in external extended mode. when the iokeep bit is cleared to 0, retention of the states of pins including the address bus, bus-control signals ( cs0 , as , rd , hwr , and lwr ), data bus, and other pins including b output is released after the oscillation settling time has elapsed. sleep instruction deep software standby mode (power-down mode) program execution state program execution state reset exception handling oscillator i nmi internal reset operated retained address retained bus control retained data b retained retained i/o other than above started from h'00000 operated operated operated operated operated oscillation settling time figure 27.6 example of deep so ftware standby mode operation in external extended mode (iokeep = ope = 0) section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1189 of 1340 rej09b0499-0200 27.8.7 flowchart of deep software standby mode operation figure 27.7 shows an example of flowchart of deep software standby mode operation. in this example, reading the dpsrst f bit determines whether a reset was generated by the res pin or exit from deep software standby mode, after the reset exception handling was performed. when a reset was caused by the res pin, deep software standby mode is entered after required register settings. when a reset was caused by exit from deep software standby mode, the iokeep bit is cleared after the i/o ports setting. when the iokeep bit is cleared, the setting to avoid instability in b output is also set. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1190 of 1340 rej09b0499-0200 clear a reset by res set oscillation setting time no yes select deep software standby mode set pin state in deep software standby mode and after exit from deep software standby mode set deep software standby mode clearing interrupt an interrupt is generated by exit from deep software standby mode. identify deep software standby mode clearing source (1) set pin state after clearing iokeep to 0 releases pin states that were retained during deep software standby mode start b output reset exception handling read dpsifr set pnddr,pndr set sckcr.pstop1 to 1 set dpsbycr.iokeep to 0 set sckcr.pstop1 to 0 execute a program corresponding to the clearing source that was identified in (1) program start set dpswcr.wtsts5-0 set sbycr.ssby to 1 dpsbycr.dpsby to 1 dpsbycr.ramcut2-0 set pnddr,pndr set sbycr.ope set dpsbycr.iokeep to 1 set dpsiegr set dpsier clear dpsifr execute sleep instruction deep software standby mode rstsr. dpsrstf = 0 figure 27.7 flowchart of deep software standby mode operation section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1191 of 1340 rej09b0499-0200 27.9 hardware standby mode 27.9.1 transition to hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. data in the on-chip ram is not retained because the internal power supply to the on-chip ram stops. i/o ports are set to the high-impedance state. do not change the states of mode pins (md2 to md0) while this lsi is in hardware standby mode. 27.9.2 clearing hardwa re standby mode hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is entered and clock oscillation is started. ensure that the res pin is held low until clock oscillation settles (for details on the oscillation settling time, refer to table 27.2). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 27.9.3 hardware standby mode timing figure 27.8 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation settling time, then changing the res pin from low to high. oscillator res stby oscillation settling time reset exception handling figure 27.8 hardware standby mode timing section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1192 of 1340 rej09b0499-0200 27.9.4 timing sequence at power-on figure 27.9 shows the timing sequence at power-on. at power-on, the res pin must be driven low with the stby pin driven high for a given time in order to clear the reset state. to enter hardware standby mode immediately after power-on, drive the stby pin low after exiting the reset state. for details on clearing hardware standby mode, see section 27.9.3, hardware standby mode timing. in a power-on reset*, power on while driving the stby or res pin to a high-level. note: * supported only by the h8sx/1655m group. res stby power supply reset state hardware standby mode 1 2 3 figure 27.9 timing sequence at power-on section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1193 of 1340 rej09b0499-0200 27.10 sleep instruction exception handling a sleep instruction exception handling is generate d by executing a sleep instruction. the sleep instruction exception handling is always acc epted in the program execution state. when the slpie bit is set to 0, sleep instruction exception handling does not follow execution of the sleep instruction. in this cas e, the cpu is placed in the power- down state. after exit from the power-down state has been initiated by an exception, the cpu starts handling of the exception. when the slpie bit is set to 1, sleep instruction exception handling follows execution of the sleep instruction. the cpu immediately starts sleep instruction exce ption handling, which blocks the transition to the power-down state is prevented by. when a sleep instruction is execut ed while the slpie bit is cleared to 0, a transition is made to the power-down state. exit from the power-down stat e is initiated by an ex it-initiating interrupt source (see figure 27.10). when an interrupt that causes ex it from the power-down state is generated immediately before the execution of a sleep instruction, exception handling for the interrupt starts. on return from the exception service routine, th e sleep instruction is executed to en ter the power-down state. in this case, exit from the powe r-down state will not take place unti l the next time an exit-initiating interrupt is generated (see figure 27.11). as stated above, setting the slpie bit to 1 causes sleep instruction exception handling to follow the execution of the sleep instruction. if this se tting is made in the exce ption service routine for an interrupt that initiates exit from the power-down state, handling of the sleep instruction exception due to the exec ution of a sleep instruction will proceed even if the interrupt was generated immediately beforehand (see figure 27.12). consequently, the cpu will execute the instruction that follows the sleep instruction, after handling of the sleep instruction exception and exception service routine, and w ill not enter the power-down state. thus, when the slpie bit is set to 1 to enable the sleep exception handling, clear the ssby bit in sbycr to 0. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1194 of 1340 rej09b0499-0200 slpie = 0 yes no instruction before sleep instruction instruction after sleep instruction sleep instruction executed (slpie = 0) canceling factor interrupt transition by interrupt exception handling interrupt handling routine rte instruction executed power-down state figure 27.10 when an interrupt that initiates exit from the power-down state is generated after sleep instruction execution slpie = 0 yes no instruction before sleep instruction instruction after sleep instruction sleep instruction executed (slpie = 0) canceling factor interrupt canceling factor interrupt transition by interrupt exception handling return from the power- down state after the next canceling factor interrupt is generated interrupt handling routine rte instruction executed power-down state yes no transition by interrupt exception handling interrupt handling routine rte instruction executed figure 27.11 when an interrupt that initiates exit from the power-down state is generated before sleep instruction execution (sleep-instruction exception handling does not proceed) section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1195 of 1340 rej09b0499-0200 slpie = 0 slpie = 1 ssby = 0 instruction before sleep instruction instruction after sleep instruction sleep instruction executed (slpie = 1) sleep instruction exceotion handling canceling factor interrupt transition by interrupt exception handling vector number 18 exception service routine rte instruction executed yes no transition by interrupt exception handling interrupt handling routine rte instruction executed figure 27.12 when an interrupt that initiates exit from the power-down state is generated before sleep instruction execution (sleep instruction excep tion handling proceeds) section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1196 of 1340 rej09b0499-0200 27.11 | clock output control output of the b clock can be controlled by the psto p1 bit in sckcr, and ddr for the corresponding pa7 pin. clearing the pstop1 bit to 0 enables the b clock output on the pa7 pin. when bit pstop1 is set to 1, the b clock output stops at the en d of the bus cycle, and the b clock output goes high. when ddr for the pa7 pin is cleared to 0, the b clock output is disabled and the pin becomes an input port. table 27.4 shows the states of the b pin in each processing state. table 27.4 pin (pa7) state in each processing state register setting value software standby mode deep software standby mode ddr pstop1 normal operating mode sleep mode all-module- clock-stop mode ope = 0 ope = 1 iokeep = 0 iokeep = 1 hardware standby mode 0 x hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z 1 0 b output b output b output high high high high hi-z 1 1 high high high high high high high hi-z [legend] x = don't care section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1197 of 1340 rej09b0499-0200 27.12 usage notes 27.12.1 i/o port status in software standby mode or deep software st andby mode, the i/o port states are retained. therefore, there is no reduction in current drawn due to output currents when high-level signals are being output. 27.12.2 current consumption during oscillat ion settling standby period current consumption increases during the oscillation settling standby period. 27.12.3 module stop state of exdmac, dmac, or dtc depending on the operating state of the exdmac, dmac, and dtc, bits mstpa14, mstpa13, and mstpa12 may not be set to 1, respectively. the module stop state setting for the exdmac, dmac, or dtc should be carried out only when the exdmac, dmac, or dtc is not activated. for details, refer to section 10, dma controller (dmac), section 11, exdma controller (exdmac), and section 12, data transfer controller (dtc). 27.12.4 on-chip peripheral module interrupts relevant interrupt operations cannot be performed in a module stop state. consequently, if the module stop state is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dmac or dtc activation source. interrupts should therefore be disabled before entering a module stop state. 27.12.5 writing to mstpcra, mstpcrb, and mstpcrc mstpcra, mstpcrb, and mstpcrc should onl y be written to by the cpu. section 27 power-down modes rev. 2.00 oct. 20, 2009 page 1198 of 1340 rej09b0499-0200 27.12.6 control of input buffers by dirqne (n = 3 to 0) when the input buffers for the p10/ irq0 -a to p13/ irq3 -a pins are enabled by setting the dirqne bits (n = 3 to 0) in dspier to 1, the pnicr settings correspon ding to these pins are invalid. therefore, note that external inputs to th ese pins, of which states are reflected on the dirqnf bits, are also input to the interrupt contro ller, peripheral modules and i/o ports, after the dirqne bits (n = 3 to 0) are set to 1. 27.12.7 conflict between a transition to deep software standby mode and interrupts if a conflict between a transition to deep software standby mode and generation of software standby mode clearing source occurs, a transition to deep software standby mode is not made but the software standby mode clearing sequence is ex ecuted. in this case, an interrupt exception handling for the input interrupt starts after the oscillation settling time for software standby mode (set by the sts4 to sts0 b its in sbycr) has elapsed. note that if a conflict between a deep software standby mode transition and nmi interrupt occurs, the nmi interrupt exception ha ndling routine is required. if a conflict between transitions to deep software standby mode, the irq0 to irq11 interrupts, and voltage-monitoring interrupt*occurs, a transition to deep software standby mode can be made without executing the interrupt handling by clearin g the ssin bits in ssier to 0 beforehand. note: * supported only by the h8sx/1655m group. 27.12.8 b output state b output is undefined for a maximum of one cycle immediately after deep software standby mode is canceled with the iokeep bit cleared to 0 or immediately after the iokeep bit is cleared after cancellation of deep software standby mode with the iokeep bit set to 1. however, b can be normally output by setting the iokeep and pstop1 bits. for details, see section 27.8.4, b operation after exit from deep software standby mode. section 28 list of registers rev. 2.00 oct. 20, 2009 page 1199 of 1340 rej09b0499-0200 section 28 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? registers are classified accor ding to functional modules. ? the number of acces s cycles indicates the number of stat es based on the specified reference clock. for details, refer to sec tion 9.5.4, external bus interface. ? among the internal i/o register area, addresses not listed in th e list of registers are undefined or reserved addresses. undefi ned and reserved addresses cannot be accessed. do not access these addresses; otherwise, the operation when accessing these bi ts and subsequent operations cannot be guaranteed. 2. register bits ? bit configurations of the registers are listed in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? space in the bit name field indicates that the entire register is allo cated to either the counter or data. ? for the registers of 16 or 32 bits, the msb is listed first. ? byte configuration description order is subject to big endian. 3. register states in each operating mode ? register states are listed in the same order as the register addresses. ? for the initialized state of each bit, refer to the register description in the corresponding section. ? the register states shown here ar e for the basic operating modes. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. section 28 list of registers rev. 2.00 oct. 20, 2009 page 1200 of 1340 rej09b0499-0200 28.1 register addresses (address order) register name abbreviation number of bits address module data width access cycles (read/write) timer control register_4 tcr_4 8 h'fea40 tmr_4 16 3p /3p timer control register_5 tcr_5 8 h'fea41 tmr_5 16 3p /3p timer control/status register_4 tcsr_4 8 h'fea42 tmr_4 16 3p /3p timer control/status register_5 tcsr_5 8 h'fea43 tmr_5 16 3p /3p time constant registera_4 tcora_4 8 h'fea44 tmr_4 16 3p /3p time constant registera_5 tcora_5 8 h'fea45 tmr_5 16 3p /3p time constant registerb_4 tcorb_4 8 h'fea46 tmr_4 16 3p /3p time constant registerb_5 tcorb_5 8 h'fea47 tmr_5 16 3p /3p timer counter_4 tcnt_4 8 h'fea48 tmr_4 16 3p /3p timer counter_5 tcnt_5 8 h'fea49 tmr_5 16 3p /3p timer counter control register_4 tccr_4 8 h'fea4a tmr_4 16 3p /3p timer counter control register_5 tccr_5 8 h'fea4b tmr_5 16 3p /3p crc control register crccr 8 h'fea4c crc 16 3p /3p crc data input register crcdir 8 h'fea4d crc 16 3p /3p crc data output register crcdor 16 h'fea4e crc 16 3p /3p timer control register_6 tcr_6 8 h'fea50 tmr_6 16 3p /3p timer control register_7 tcr_7 8 h'fea51 tmr_7 16 3p /3p timer control/status register_6 tcsr_6 8 h'fea52 tmr_6 16 3p /3p timer control/status register_7 tcsr_7 8 h'fea53 tmr_7 16 3p /3p time constant registera_6 tcora_6 8 h'fea54 tmr_6 16 3p /3p time constant registera_7 tcora_7 8 h'fea55 tmr_7 16 3p /3p time constant registerb_6 tcorb_6 8 h'fea56 tmr_6 16 3p /3p time constant registerb_7 tcorb_7 8 h'fea57 tmr_7 16 3p /3p timer counter_6 tcnt_6 8 h'fea58 tmr_6 16 3p /3p timer counter_7 tcnt_7 8 h'fea59 tmr_7 16 3p /3p timer counter control register_6 tccr_6 8 h'fea5a tmr_6 16 3p /3p timer counter control register_7 tccr_7 8 h'fea5b tmr_7 16 3p /3p a/d data register a_1 addra_1 16 h'fea80 a/d_1 16 3p /3p a/d data register b_1 addrb_1 16 h'fea82 a/d_1 16 3p /3p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1201 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) a/d data register c_1 addrc_1 16 h'fea84 a/d_1 16 3p /3p a/d data register d_1 addrd_1 16 h'fea86 a/d_1 16 3p /3p a/d data register e_1 addre_1 16 h'fea90 a/d_1 16 3p /3p a/d data register f_1 addrf_1 16 h'fea92 a/d_1 16 3p /3p a/d data register g_1 addrg_1 16 h'fea94 a/d_1 16 3p /3p a/d data register h_1 addrh_1 16 h'fea96 a/d_1 16 3p /3p a/d control/status register_1 adcsr_1 8 h'feaa0 a/d_1 16 3p /3p a/d control register_1 adcr_1 8 h'feaa1 a/d_1 16 3p /3p a/d mode selection register_1 admosel_1 8 h'feaa2 a/d_1 16 3p /3p a/d sampling state register_1 adsstr_1 8 h'feaab a/d_1 16 3p /3p interrupt flag register 0 ifr0 8 h'fee00 usb 8 3p /3p interrupt flag register 1 ifr1 8 h'fee01 usb 8 3p /3p interrupt flag register 2 ifr2 8 h'fee02 usb 8 3p /3p interrupt enable register 0 ier0 8 h'fee04 usb 8 3p /3p interrupt enable register 1 ier1 8 h'fee05 usb 8 3p /3p interrupt enable register 2 ier2 8 h'fee06 usb 8 3p /3p interrupt select register 0 isr0 8 h'fee08 usb 8 3p /3p interrupt select register 1 isr1 8 h'fee09 usb 8 3p /3p interrupt select register 2 isr2 8 h'fee0a usb 8 3p /3p ep0i data register epdr0i 8 h'fee0c usb 8 3p /3p ep0o data register epdr0o 8 h'fee0d usb 8 3p /3p ep0s data register epdr0s 8 h'fee0e usb 8 3p /3p ep1 data register epdr1 8 h'fee10 usb 8 3p /3p ep2 data register epdr2 8 h'fee14 usb 8 3p /3p ep3 data register epdr3 8 h'fee18 usb 8 3p /3p ep0o receive data size register epsz0o 8 h'fee24 usb 8 3p /3p ep1 receive data size register epsz1 8 h'fee25 usb 8 3p /3p data status register dasts 8 h'fee27 usb 8 3p /3p fifo clear register fclr 8 h'fee28 usb 8 3p /3p end point store register epstl 8 h'fee2a usb 8 3p /3p trigger register trg 8 h'fee2c usb 8 3p /3p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1202 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) dma transfer setting register dma 8 h'fee2d usb 8 3p /3p configuration value register cvr 8 h'fee2e usb 8 3p /3p control register ctlr 8 h'fee2f usb 8 3p /3p end point information register epir 8 h'fee32 usb 8 3p /3p transceiver test register 0 trntreg0 8 h'fee44 usb 8 3p /3p transceiver test register 1 trntreg1 8 h'fee45 usb 8 3p /3p port m data direction register pmddr 8 h'fee50 i/o port 8 3p /3p port m data register pmdr 8 h'fee51 i/o port 8 3p /3p port m register portm 8 h'fee52 i/o port 8 3p /3p port m input buffer control register pmicr 8 h'fee53 i/o port 8 3p /3p serial mode register_5 smr_5 8 h'ff600 sci_5 8 3p /3p bit rate register_5 brr_5 8 h'ff601 sci_5 8 3p /3p serial control register_5 scr_5 8 h'ff602 sci_5 8 3p /3p transmit data register_5 tdr_5 8 h'ff603 sci_5 8 3p /3p serial status register_5 ssr_5 8 h'ff604 sci_5 8 3p /3p receive data register_5 rdr_5 8 h'ff605 sci_5 8 3p /3p smart card mode register_5 scmr_5 8 h'ff606 sci_5 8 3p /3p serial extended mode register_5 semr_5 8 h'ff608 sci_5 8 3p /3p irda control register ircr 8 h'ff60c sci_5 8 3p /3p serial mode register_6 smr_6 8 h'ff610 sci_6 8 3p /3p bit rate register_6 brr_6 8 h'ff611 sci_6 8 3p /3p serial control register_6 scr_6 8 h'ff612 sci_6 8 3p /3p transmit data register_6 tdr_6 8 h'ff613 sci_6 8 3p /3p serial status register_6 ssr_6 8 h'ff614 sci_6 8 3p /3p receive data register_6 rdr_6 8 h'ff615 sci_6 8 3p /3p smart card mode register_6 scmr_6 8 h'ff616 sci_6 8 3p /3p serial extended mode register_6 semr_6 8 h'ff618 sci_6 8 3p /3p ppg output control register _1 pcr_1 8 h'ff636 ppg_1 8 3p /3p ppg output mode register_1 pmr_1 8 h'ff637 ppg_1 8 3p /3p next data enable register h_1 nderh_1 8 h'ff638 ppg_1 8 3p /3p next data enable register l_1 nderl_1 8 h'ff639 ppg_1 8 3p /3p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1203 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) output data register h_1 podrh_1 8 h'ff63a ppg_1 8 3p /3p output data register l_1 podrl_1 8 h'ff63b ppg_1 8 3p /3p next data register h_1 * 1 ndrh_1 8 h'ff63c ppg_1 8 3p /3p next data register l_1 * 1 ndrl_1 8 h'ff63d ppg_1 8 3p /3p next data register h_1 * 1 ndrh_1 8 h'ff63e ppg_1 8 3p /3p next data register l_1 * 1 ndrl_1 8 h'ff63f ppg_1 8 3p /3p break address register ah barah 16 h'ffa00 ubc 16 2i /2i break address register al baral 16 h'ffa02 ubc 16 2i /2i break address mask register ah bamrah 16 h'ffa04 ubc 16 2i /2i break address mask register al bamral 16 h'ffa06 ubc 16 2i /2i break address register bh barbh 16 h'ffa08 ubc 16 2i /2i break address register bl barbl 16 h'ffa0a ubc 16 2i /2i break address mask register bh bamrbh 16 h'ffa0c ubc 16 2i /2i break address mask register bl bamrbl 16 h'ffa0e ubc 16 2i /2i break address register ch barch 16 h'ffa10 ubc 16 2i /2i break address register cl barcl 16 h'ffa12 ubc 16 2i /2i break address mask register ch bamrch 16 h'ffa14 ubc 16 2i /2i break address mask register cl bamrcl 16 h'ffa16 ubc 16 2i /2i break address register dh bardh 16 h'ffa18 ubc 16 2i /2i break address register dl bardl 16 h'ffa1a ubc 16 2i /2i break address mask register dh bamrdh 16 h'ffa1c ubc 16 2i /2i break address mask register dl bamrdl 16 h'ffa1e ubc 16 2i /2i break control register a brcra 16 h'ffa28 ubc 16 2i /2i break control register b brcrb 16 h'ffa2c ubc 16 2i /2i break control register c brcrc 16 h'ffa30 ubc 16 2i /2i break control register d brcrd 16 h'ffa34 ubc 16 2i /2i a/d sampling state register_0 adsstr_0 8 h'feadb a/d_0 16 2p /2p timer start register tstrb 8 h'ffb00 tpu (unit 1) 16 2p /2p timer synchronous register tsyrb 8 h'ffb01 tpu (unit 1) 16 2p /2p timer control register_6 tcr_6 8 h'ffb10 tpu_6 16 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1204 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) timer mode register_6 tmdr_6 8 h'ffb11 tpu_6 16 2p /2p timer i/o control register h_6 tiorh_6 8 h'ffb12 tpu_6 16 2p /2p timer i/o control register l_6 tiorl_6 8 h'ffb13 tpu_6 16 2p /2p timer interrupt enable register_6 tier_6 8 h'ffb14 tpu_6 16 2p /2p timer status register_6 tsr_6 8 h'ffb15 tpu_6 16 2p /2p timer counter_6 tcnt_6 16 h'ffb16 tpu_6 16 2p /2p timer general register a_6 tgra_6 16 h'ffb18 tpu_6 16 2p /2p timer general register b_6 tgrb_6 16 h'ffb1a tpu_6 16 2p /2p timer general register c_6 tgrc_6 16 h'ffb1c tpu_6 16 2p /2p timer general register d_6 tgrd_6 16 h'ffb1e tpu_6 16 2p /2p timer control register_7 tcr_7 8 h'ffb20 tpu_7 16 2p /2p timer mode register_7 tmdr_7 8 h'ffb21 tpu_7 16 2p /2p timer i/o control register_7 tior_7 8 h'ffb22 tpu_7 16 2p /2p timer interrupt enable register_7 tier_7 8 h'ffb24 tpu_7 16 2p /2p timer status register_7 tsr_7 8 h'ffb25 tpu_7 16 2p /2p timer counter_7 tcnt_7 16 h'ffb26 tpu_7 16 2p /2p timer general register a_7 tgra_7 16 h'ffb28 tpu_7 16 2p /2p timer general register b_7 tgrb_7 16 h'ffb2a tpu_7 16 2p /2p timer control register_8 tcr_8 8 h'ffb30 tpu_8 16 2p /2p timer mode register_8 tmdr_8 8 h'ffb31 tpu_8 16 2p /2p timer i/o control register_8 tior_8 8 h'ffb32 tpu_8 16 2p /2p timer interrupt enable register_8 tier_8 8 h'ffb34 tpu_8 16 2p /2p timer status register_8 tsr_8 8 h'ffb35 tpu_8 16 2p /2p timer counter_8 tcnt_8 16 h'ffb36 tpu_8 16 2p /2p timer general register a_8 tgra_8 16 h'ffb38 tpu_8 16 2p /2p timer general register b_8 tgrb_8 16 h'ffb3a tpu_8 16 2p /2p timer control register_9 tcr_9 8 h'ffb40 tpu_9 16 2p /2p timer mode register_9 tmdr_9 8 h'ffb41 tpu_9 16 2p /2p timer i/o control register h_9 tiorh_9 8 h'ffb42 tpu_9 16 2p /2p timer i/o control register l_9 tiorl_9 8 h'ffb43 tpu_9 16 2p /2p timer interrupt enable register_9 tier_9 8 h'ffb44 tpu_9 16 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1205 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) timer status register_9 tsr_9 8 h'ffb45 tpu_9 16 2p /2p timer counter_9 tcnt_9 16 h'ffb46 tpu_9 16 2p /2p timer general register a_9 tgra_9 16 h'ffb48 tpu_9 16 2p /2p timer general register b_9 tgrb_9 16 h'ffb4a tpu_9 16 2p /2p timer general register c_9 tgrc_9 16 h'ffb4c tpu_9 16 2p /2p timer general register d_9 tgrd_9 16 h'ffb4e tpu_9 16 2p /2p timer control register_10 tcr_10 8 h'ffb50 tpu_10 16 2p /2p timer mode register_10 tmdr_10 8 h'ffb51 tpu_10 16 2p /2p timer i/o control register_10 tior_10 8 h'ffb52 tpu_10 16 2p /2p timer interrupt enable register_10 tier_10 8 h'ffb54 tpu_10 16 2p /2p timer status register_10 tsr_10 8 h'ffb55 tpu_10 16 2p /2p timer counter_10 tcnt_10 16 h'ffb56 tpu_10 16 2p /2p timer general register a_10 tgra_10 16 h'ffb58 tpu_10 16 2p /2p timer general register b_10 tgrb_10 16 h'ffb5a tpu_10 16 2p /2p timer control register_11 tcr_11 8 h'ffb60 tpu_11 16 2p /2p timer mode register_11 tmdr_11 8 h'ffb61 tpu_11 16 2p /2p timer i/o control register_11 tior_11 8 h'ffb62 tpu_11 16 2p /2p timer interrupt enable register_11 tier_11 8 h'ffb64 tpu_11 16 2p /2p timer status register_11 tsr_11 8 h'ffb65 tpu_11 16 2p /2p timer counter_11 tcnt_11 16 h'ffb66 tpu_11 16 2p /2p timer general register a_11 tgra_11 16 h'ffb68 tpu_11 16 2p /2p timer general register b_11 tgrb_11 16 h'ffb6a tpu_11 16 2p /2p port 1 data direction register p1ddr 8 h'ffb80 i/o port 8 2p /2p port 2 data direction register p2ddr 8 h'ffb81 i/o port 8 2p /2p port 6 data direction register p6ddr 8 h'ffb85 i/o port 8 2p /2p port a data direction register paddr 8 h'ffb89 i/o port 8 2p /2p port b data direction register pbddr 8 h'ffb8a i/o port 8 2p /2p port d data direction register pdddr 8 h'ffb8c i/o port 8 2p /2p port e data direction register peddr 8 h'ffb8d i/o port 8 2p /2p port f data direction register pfddr 8 h'ffb8e i/o port 8 2p /2p port 1 input buffer control register p1icr 8 h'ffb90 i/o port 8 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1206 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) port 2 input buffer control register p2icr 8 h'ffb91 i/o port 8 2p /2p port 5 input buffer control register p5icr 8 h'ffb94 i/o port 8 2p /2p port 6 input buffer control register p6icr 8 h'ffb95 i/o port 8 2p /2p port a input buffer control register paicr 8 h'ffb99 i/o port 8 2p /2p port b input buffer control register pbicr 8 h'ffb9a i/o port 8 2p /2p port d input buffer control register pdicr 8 h'ffb9c i/o port 8 2p /2p port e input buffer control register peicr 8 h'ffb9d i/o port 8 2p /2p port f input buffer control register pficr 8 h'ffb9e i/o port 8 2p /2p port h register porth 8 h'ffba0 i/o port 8 2p /2p port i register porti 8 h'ffba1 i/o port 8 2p /2p port j register portj 8 h'ffba2 i/o port 8 2p /2p port k register portk 8 h'ffba3 i/o port 8 2p /2p port h data register phdr 8 h'ffba4 i/o port 8 2p /2p port i data register pidr 8 h'ffba5 i/o port 8 2p /2p port j data register pjdr 8 h'ffba6 i/o port 8 2p /2p port k data register pkdr 8 h'ffba7 i/o port 8 2p /2p port h data direction register phddr 8 h'ffba8 i/o port 8 2p /2p port i data direction register piddr 8 h'ffba9 i/o port 8 2p /2p port j data direction register pjddr 8 h'ffbaa i/o port 8 2p /2p port k data direction register pkddr 8 h'ffbab i/o port 8 2p /2p port h input buffer control register phicr 8 h'ffbac i/o port 8 2p /2p port i input buffer control register piicr 8 h'ffbad i/o port 8 2p /2p port j input buffer control register pjicr 8 h'ffbae i/o port 8 2p /2p port k input buffer control register pkicr 8 h'ffbaf i/o port 8 2p /2p port d pull-up mos control register pdpcr 8 h'ffbb4 i/o port 8 2p /2p port e pull-up mos control register pepcr 8 h'ffbb5 i/o port 8 2p /2p port f pull-up mos control register pfpcr 8 h'ffbb6 i/o port 8 2p /2p port h pull-up mos control register phpcr 8 h'ffbb8 i/o port 8 2p /2p port i pull-up mos control register pipcr 8 h'ffbb9 i/o port 8 2p /2p port j pull-up mos control register pjpcr 8 h'ffbba i/o port 8 2p /2p port k pull-up mos control register pkpcr 8 h'ffbbb i/o port 8 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1207 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) port 2 open-drain control register p2odr 8 h'ffbbc i/o port 8 2p /2p port f open-drain control register pfodr 8 h'ffbbd i/o port 8 2p /2p port function control register 0 pfcr0 8 h'ffbc0 i/o port 8 2p /3p port function control register 1 pfcr1 8 h'ffbc1 i/o port 8 2p /3p port function control register 2 pfcr2 8 h'ffbc2 i/o port 8 2p /3p port function control register 4 pfcr4 8 h'ffbc4 i/o port 8 2p /3p port function control register 6 pfcr6 8 h'ffbc6 i/o port 8 2p /3p port function control register 7 pfcr7 8 h'ffbc7 i/o port 8 2p /3p port function control register 8 pfcr8 8 h'ffbc8 i/o port 8 2p /3p port function control register 9 pfcr9 8 h'ffbc9 i/o port 8 2p /3p port function control register a pfcra 8 h'ffbca i/o port 8 2p /3p port function control register b pfcrb 8 h'ffbcb i/o port 8 2p /3p port function control register c pfcrc 8 h'ffbcc i/o port 8 2p /3p port function control register d pfcrd 8 h'ffbcd i/o port 8 2p /3p software standby release irq enable register ssier 16 h'ffbce intc 8 2p /3p deep standby backup register 0 dpsbkr0 8 h'ffbf0 system 8 2i /3i deep standby backup register 1 dpsbkr1 8 h'ffbf1 system 8 2i /3i deep standby backup register 2 dpsbkr2 8 h'ffbf2 system 8 2i /3i deep standby backup register 3 dpsbkr3 8 h'ffbf3 system 8 2i /3i deep standby backup register 4 dpsbkr4 8 h'ffbf4 system 8 2i /3i deep standby backup register 5 dpsbkr5 8 h'ffbf5 system 8 2i /3i deep standby backup register 6 dpsbkr6 8 h'ffbf6 system 8 2i /3i deep standby backup register 7 dpsbkr7 8 h'ffbf7 system 8 2i /3i deep standby backup register 8 dpsbkr8 8 h'ffbf8 system 8 2i /3i deep standby backup register 9 dpsbkr9 8 h'ffbf9 system 8 2i /3i deep standby backup register 10 dpsbkr10 8 h'ffbfa system 8 2i /3i deep standby backup register 11 dpsbkr11 8 h'ffbfb system 8 2i /3i deep standby backup register 12 dpsbkr12 8 h'ffbfc system 8 2i /3i deep standby backup register 13 dpsbkr13 8 h'ffbfd system 8 2i /3i deep standby backup register 14 dpsbkr14 8 h'ffbfe system 8 2i /3i section 28 list of registers rev. 2.00 oct. 20, 2009 page 1208 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) deep standby backup register 15 dpsbkr15 8 h'ffbff system 8 2i /3i dma source address register_0 dsar_0 32 h'ffc00 dmac_0 16 2i /2i dma destination address register_0 ddar_0 32 h'ffc04 dmac_0 16 2i /2i dma offset register_0 dofr_0 32 h'ffc08 dmac_0 16 2i /2i dma transfer count register_0 dtcr_0 32 h'ffc0c dmac_0 16 2i /2i dma block size register_0 dbsr_0 32 h'ffc10 dmac_0 16 2i /2i dma mode control register_0 dmdr_0 32 h'ffc14 dmac_0 16 2i /2i dma address control register_0 dacr_0 32 h'ffc18 dmac_0 16 2i /2i dma source address register_1 dsar_1 32 h'ffc20 dmac_1 16 2i /2i dma destination address register_1 ddar_1 32 h'ffc24 dmac_1 16 2i /2i dma offset register_1 dofr_1 32 h'ffc28 dmac_1 16 2i /2i dma transfer count register_1 dtcr_1 32 h'ffc2c dmac_1 16 2i /2i dma block size register_1 dbsr_1 32 h'ffc30 dmac_1 16 2i /2i dma mode control register_1 dmdr_1 32 h'ffc34 dmac_1 16 2i /2i dma address control register_1 dacr_1 32 h'ffc38 dmac_1 16 2i /2i dma source address register_2 dsar_2 32 h'ffc40 dmac_2 16 2i /2i dma destination address register_2 ddar_2 32 h'ffc44 dmac_2 16 2i /2i dma offset register_2 dofr_2 32 h'ffc48 dmac_2 16 2i /2i dma transfer count register_2 dtcr_2 32 h'ffc4c dmac_2 16 2i /2i dma block size register_2 dbsr_2 32 h'ffc50 dmac_2 16 2i /2i dma mode control register_2 dmdr_2 32 h'ffc54 dmac_2 16 2i /2i dma address control register_2 dacr_2 32 h'ffc58 dmac_2 16 2i /2i dma source address register_3 dsar_3 32 h'ffc60 dmac_3 16 2i /2i dma destination address register_3 ddar_3 32 h'ffc64 dmac_3 16 2i /2i dma offset register_3 dofr_3 32 h'ffc68 dmac_3 16 2i /2i dma transfer count register_3 dtcr_3 32 h'ffc6c dmac_3 16 2i /2i dma block size register_3 dbsr_3 32 h'ffc70 dmac_3 16 2i /2i dma mode control register_3 dmdr_3 32 h'ffc74 dmac_3 16 2i /2i dma address control register_3 dacr_3 32 h'ffc78 dmac_3 16 2i /2i exdma source address register_0 edsar_0 32 h'ffc80 exdmac_0 16 2i /2i section 28 list of registers rev. 2.00 oct. 20, 2009 page 1209 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) exdma destination address register_0 eddar_0 32 h'ffc84 exdmac_0 16 2i /2i exdma offset register_0 edofr_0 32 h'ffc88 exdmac_0 16 2i /2i exdma transfer count register_0 edtcr_0 32 h'ffc8c exdmac_0 16 2i /2i exdma block size register_0 edbsr_0 32 h'ffc90 exdmac_0 16 2i /2i exdma mode control regisrer_0 edmdr_0 32 h'ffc94 exdmac_0 16 2i /2i exdma address control register_0 edacr_0 32 h'ffc98 exdmac_0 16 2i /2i exdma source address register_1 edsar_1 32 h'ffca0 exdmac_1 16 2i /2i exdma destination address register_1 eddar_1 32 h'ffca4 exdmac_1 16 2i /2i exdma offset register_1 edofr_1 32 h'ffca8 exdmac_1 16 2i /2i exdma transfer count register_1 edtcr_1 32 h'ffcac exdmac_1 16 2i /2i exdma block size register_1 edbsr_1 32 h'ffcb0 exdmac_1 16 2i /2i exdma mode control register_1 edmdr_1 32 h'ffcb4 exdmac_1 16 2i /2i exdma address control register_1 edacr_1 32 h'ffcb8 exdmac_1 16 2i /2i exdma source address register_2 edsar_2 32 h'ffcc0 exdmac_2 16 2i /2i exdma destination address register_2 eddar_2 32 h'ffcc4 exdmac_2 16 2i /2i exdma offset register_2 edofr_2 32 h'ffcc8 exdmac_2 16 2i /2i exdma transfer count register_2 edtcr_2 32 h'ffccc exdmac_2 16 2i /2i exdma block size register_2 edbsr_2 32 h'ffcd0 exdmac_2 16 2i /2i exdma mode control register_2 edmdr_2 32 h'ffcd4 exdmac_2 16 2i /2i exdma address control register_2 edacr_2 32 h'ffcd8 exdmac_2 16 2i /2i exdma source address register_3 edsar_3 32 h'ffce0 exdmac_3 16 2i /2i exdma destination address register_3 eddar_3 32 h'ffce4 exdmac_3 16 2i /2i exdma offset register_3 edofr_3 32 h'ffce8 exdmac_3 16 2i /2i exdma transfer count register_3 edtcr_3 32 h'ffcec exdmac_3 16 2i /2i exdma block size register_3 edbsr_3 32 h'ffcf0 exdmac_3 16 2i /2i exdma mode control register_3 edmdr_3 32 h'ffcf4 exdmac_3 16 2i /2i exdma address control register_3 edacr_3 32 h'ffcf8 exdmac_3 16 2i /2i cluster buffer register 0 clsbr0 32 h'ffd00 exdmac 16 2i /2i section 28 list of registers rev. 2.00 oct. 20, 2009 page 1210 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) cluster buffer register 1 clsbr1 32 h'ffd04 exdmac 16 2i /2i cluster buffer register 2 clsbr2 32 h'ffd08 exdmac 16 2i /2i cluster buffer register 3 clsbr3 32 h'ffd0c exdmac 16 2i /2i cluster buffer register 4 clsbr4 32 h'ffd10 exdmac 16 2i /2i cluster buffer register 5 clsbr5 32 h'ffd14 exdmac 16 2i /2i cluster buffer register 6 clsbr6 32 h'ffd18 exdmac 16 2i /2i cluster buffer register 7 clsbr7 32 h'ffd1c exdmac 16 2i /2i dma module request select register_0 dmrsr_0 8 h'ffd20 dmac_0 16 2i /2i dma module request select register_1 dmrsr_1 8 h'ffd21 dmac_1 16 2i /2i dma module request select register_2 dmrsr_2 8 h'ffd22 dmac_2 16 2i /2i dma module request select register_3 dmrsr_3 8 h'ffd23 dmac_3 16 2i /2i interrupt priority register a ipra 16 h'ffd40 intc 16 2i /3i interrupt priority register b iprb 16 h'ffd42 intc 16 2i /3i interrupt priority register c iprc 16 h'ffd44 intc 16 2i /3i interrupt priority register e ipre 16 h'ffd48 intc 16 2i /3i interrupt priority register f iprf 16 h'ffd4a intc 16 2i /3i interrupt priority register g iprg 16 h'ffd4c intc 16 2i /3i interrupt priority register h iprh 16 h'ffd4e intc 16 2i /3i interrupt priority register i ipri 16 h'ffd50 intc 16 2i /3i interrupt priority register j iprj 16 h'ffd52 intc 16 2i /3i interrupt priority register k iprk 16 h'ffd54 intc 16 2i /3i interrupt priority register l iprl 16 h'ffd56 intc 16 2i /3i interrupt priority register m iprm 16 h'ffd58 intc 16 2i /3i interrupt priority register n iprn 16 h'ffd5a intc 16 2i /3i interrupt priority register o ipro 16 h'ffd5c intc 16 2i /3i interrupt priority register q iprq 16 h'ffd60 intc 16 2i /3i interrupt priority register r iprr 16 h'ffd62 intc 16 2i /3i irq sense control register h iscrh 16 h'ffd68 intc 16 2i /3i irq sense control register l iscrl 16 h'ffd6a intc 16 2i /3i dtc vector base register dtcvbr 32 h'ffd80 bsc 16 2i /3i bus width control register abwcr 16 h'ffd84 bsc 16 2i /3i section 28 list of registers rev. 2.00 oct. 20, 2009 page 1211 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) access state control register astcr 16 h'ffd86 bsc 16 2i /3i wait control register a wtcra 16 h'ffd88 bsc 16 2i /3i wait control register b wtcrb 16 h'ffd8a bsc 16 2i /3i read strobe timing control register rdncr 16 h'ffd8c bsc 16 2i /3i cs assertion period control register csacr 16 h'ffd8e bsc 16 2i /3i idle control register idlcr 16 h'ffd90 bsc 16 2i /3i bus control register 1 bcr1 16 h'ffd92 bsc 16 2i /3i bus control register 2 bcr2 8 h'ffd94 bsc 16 2i /3i endian control register endiancr 8 h'ffd95 bsc 16 2i /3i sram mode control register sramcr 16 h'ffd98 bsc 16 2i /3i burst rom interface control regi ster bromcr 16 h'ffd9a bsc 16 2i /3i address/data multiplexed i/o control register mpxcr 16 h'ffd9c bsc 16 2i /3i ram emulation register ramer 8 h'ffd9e bsc 16 2i /3i mode control register mdcr 16 h'ffdc0 system 16 2i /3i system control register syscr 16 h'ffdc2 system 16 2i /3i system clock control register sckcr 16 h'ffdc4 system 16 2i /3i standby control register sbycr 16 h'ffdc6 system 16 2i /3i module stop control register a mstpcra 16 h'ffdc8 system 16 2i /3i module stop control register b mstpcrb 16 h'ffdca system 16 2i /3i module stop control register c mstpcrc 16 h'ffdcc system 16 2i /3i flash code control/status regist er fccs 8 h'ffde8 flash 16 2i /2i flash program code select register fpcs 8 h'ffde9 flash 16 2i /2i flash erase code select register fecs 8 h'ffdea flash 16 2i /2i flash key code register fkey 8 h'ffdec flash 16 2i /2i flash mat select register fmats 8 h'ffded flash 16 2i /2i flash transfer destination address register ftdar 8 h'ffdee flash 16 2i /2i deep standby control register dpsbycr 8 h'ffe70 system 8 2i /3i deep standby wait control register dpswcr 8 h'ffe71 system 8 2i /3i deep standby interrupt enable register dpsier 8 h'ffe72 system 8 2i /3i deep standby interrupt flag register dpsifr 8 h'ffe73 system 8 2i /3i section 28 list of registers rev. 2.00 oct. 20, 2009 page 1212 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) deep standby interrupt edge register dpsiegr 8 h'ffe74 system 8 2i /3i reset status register rstsr 8 h'ffe75 system 8 2i /3i low voltage detection control register * 2 lvdcr 8 h'ffe78 system 8 2i /3i serial extended mode register_2 semr_2 8 h'ffe84 sci_2 8 2p /2p serial mode register_4 smr_4 8 h'ffe90 sci_4 8 2p /2p bit rate register_4 brr_4 8 h'ffe91 sci_4 8 2p /2p serial control register_4 scr_4 8 h'ffe92 sci_4 8 2p /2p transmit data register_4 tdr_4 8 h'ffe93 sci_4 8 2p /2p serial status register_4 ssr_4 8 h'ffe94 sci_4 8 2p /2p receive data register_4 rdr_4 8 h'ffe95 sci_4 8 2p /2p smart card mode register_4 scmr_4 8 h'ffe96 sci_4 8 2p /2p i 2 c bus control register a_0 iccra_0 8 h'ffeb0 iic2_0 8 2p /2p i 2 c bus control register b_0 iccrb_0 8 h'ffeb1 iic2_0 8 2p /2p i 2 c bus mode register_0 icmr_0 8 h'ffeb2 iic2_0 8 2p /2p i 2 c bus interrupt enable register_0 icier_0 8 h'ffeb3 iic2_0 8 2p /2p i 2 c bus status register_0 icsr_0 8 h'ffeb4 iic2_0 8 2p /2p slave address register_0 sar_0 8 h'ffeb5 iic2_0 8 2p /2p i 2 c bus transmit data register_0 icdrt_0 8 h'ffeb6 iic2_0 8 2p /2p i 2 c bus receive data register_0 icdrr_0 8 h'ffeb7 iic2_0 8 2p /2p i 2 c bus control register a_1 iccra_1 8 h'ffeb8 iic2_1 8 2p /2p i 2 c bus control register b_1 iccrb_1 8 h'ffeb9 iic2_1 8 2p /2p i 2 c bus mode register_1 icmr_1 8 h'ffeba iic2_1 8 2p /2p i 2 c bus interrupt enable register_1 icier_1 8 h'ffebb iic2_1 8 2p /2p i 2 c bus status register_1 icsr_1 8 h'ffebc iic2_1 8 2p /2p slave address register_1 sar_1 8 h'ffebd iic2_1 8 2p /2p i 2 c bus transmit data register_1 icdrt_1 8 h'ffebe iic2_1 8 2p /2p i 2 c bus receive data register_1 icdrr_1 8 h'ffebf iic2_1 8 2p /2p timer control register_2 tcr_2 8 h'ffec0 tmr_2 16 2p /2p timer control register_3 tcr_3 8 h'ffec1 tmr_3 16 2p /2p timer control/status register_2 tcsr_2 8 h'ffec2 tmr_2 16 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1213 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) timer control/status register_3 tcsr_3 8 h'ffec3 tmr_3 16 2p /2p time constant register a_2 tcora_2 8 h'ffec4 tmr_2 16 2p /2p time constant register a_3 tcora_3 8 h'ffec5 tmr_3 16 2p /2p time constant register b_2 tcorb_2 8 h'ffec6 tmr_2 16 2p /2p time constant register b_3 tcorb_3 8 h'ffec7 tmr_3 16 2p /2p timer counter_2 tcnt_2 8 h'ffec8 tmr_2 16 2p /2p timer counter_3 tcnt_3 8 h'ffec9 tmr_3 16 2p /2p timer counter control register_2 tccr_2 8 h'ffeca tmr_2 16 2p /2p timer counter control register_3 tccr_3 8 h'ffecb tmr_3 16 2p /2p timer control register_4 tcr_4 8 h'ffee0 tpu_4 16 2p /2p timer mode register_4 tmdr_4 8 h'ffee1 tpu_4 16 2p /2p timer i/o control register_4 tior_4 8 h'ffee2 tpu_4 16 2p /2p timer interrupt enable register_4 tier_4 8 h'ffee4 tpu_4 16 2p /2p timer status register_4 tsr_4 8 h'ffee5 tpu_4 16 2p /2p timer counter_4 tcnt_4 16 h'ffee6 tpu_4 16 2p /2p timer general register a_4 tgra_4 16 h'ffee8 tpu_4 16 2p /2p timer general register b_4 tgrb_4 16 h'ffeea tpu_4 16 2p /2p timer control register_5 tcr_5 8 h'ffef0 tpu_5 16 2p /2p timer mode register_5 tmdr_5 8 h'ffef1 tpu_5 16 2p /2p timer i/o control register_5 tior_5 8 h'ffef2 tpu_5 16 2p /2p timer interrupt enable register_5 tier_5 8 h'ffef4 tpu_5 16 2p /2p timer status register_5 tsr_5 8 h'ffef5 tpu_5 16 2p /2p timer counter_5 tcnt_5 16 h'ffef6 tpu_5 16 2p /2p timer general register a_5 tgra_5 16 h'ffef8 tpu_5 16 2p /2p timer general register b_5 tgrb_5 16 h'ffefa tpu_5 16 2p /2p dtc enable register a dtcera 16 h'fff20 intc 16 2i /3i dtc enable register b dtcerb 16 h'fff22 intc 16 2i /3i dtc enable register c dtcerc 16 h'fff24 intc 16 2i /3i dtc enable register d dtcerd 16 h'fff26 intc 16 2i /3i dtc enable register e dtcere 16 h'fff28 intc 16 2i /3i dtc enable register f dtcerf 16 h'fff2a intc 16 2i /3i section 28 list of registers rev. 2.00 oct. 20, 2009 page 1214 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) dtc control register dtccr 8 h'fff30 intc 16 2i /3i interrupt control register intcr 8 h'fff32 intc 16 2i /3i cpu priority control register cpupcr 8 h'fff33 intc 16 2i /3i irq enable register ier 16 h'fff34 intc 16 2i /3i irq status register isr 16 h'fff36 intc 16 2i /3i port 1 register port1 8 h'fff40 i/o port 8 2p /- port 2 register port2 8 h'fff41 i/o port 8 2p /- port 5 register port5 8 h'fff44 i/o port 8 2p /- port 6 register port6 8 h'fff45 i/o port 8 2p /- port a register porta 8 h'fff49 i/o port 8 2p /- port b register portb 8 h'fff4a i/o port 8 2p /- port d register portd 8 h'fff4c i/o port 8 2p /- port e register porte 8 h'fff4d i/o port 8 2p /- port f register portf 8 h'fff4e i/o port 8 2p /- port 1 data register p1dr 8 h'fff50 i/o port 8 2p /2p port 2 data register p2dr 8 h'fff51 i/o port 8 2p /2p port 6 data register p6dr 8 h'fff55 i/o port 8 2p /2p port a data register padr 8 h'fff59 i/o port 8 2p /2p port b data register pbdr 8 h'fff5a i/o port 8 2p /2p port d data register pddr 8 h'fff5c i/o port 8 2p /2p port e data register pedr 8 h'fff5d i/o port 8 2p /2p port f data register pfdr 8 h'fff5e i/o port 8 2p /2p serial mode register_2 smr_2 8 h'fff60 sci_2 8 2p /2p bit rate register_2 brr_2 8 h'fff61 sci_2 8 2p /2p serial control register_2 scr_2 8 h'fff62 sci_2 8 2p /2p transmit data register_2 tdr_2 8 h'fff63 sci_2 8 2p /2p serial status register_2 ssr_2 8 h'fff64 sci_2 8 2p /2p receive data register_2 rdr_2 8 h'fff65 sci_2 8 2p /2p smart card mode register_2 scmr_2 8 h'fff66 sci_2 8 2p /2p d/a data register 0 dadr0h 8 h'fff68 d/a 8 2p /2p d/a data register 1 dadr1h 8 h'fff69 d/a 8 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1215 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) d/a control register 01 dacr01 8 h'fff6a d/a 8 2p /2p d/a data register 01t dadr01t 8 h'fff6b d/a 8 2p /2p ppg output control register pcr 8 h'fff76 ppg_0 8 2p /2p ppg output mode register pmr 8 h'fff77 ppg_0 8 2p /2p next data enable register h nderh 8 h'fff78 ppg_0 8 2p /2p next data enable register l nderl 8 h'fff79 ppg_0 8 2p /2p output data register h podrh 8 h'fff7a ppg_0 8 2p /2p output data register l podrl 8 h'fff7b ppg_0 8 2p /2p next data register h * 1 ndrh 8 h'fff7c ppg_0 8 2p /2p next data register l * 1 ndrl 8 h'fff7d ppg_0 8 2p /2p next data register h * 1 ndrh 8 h'fff7e ppg_0 8 2p /2p next data register l * 1 ndrl 8 h'fff7f ppg_0 8 2p /2p serial mode register_0 smr_0 8 h'fff80 sci_0 8 2p /2p bit rate register_0 brr_0 8 h'fff81 sci_0 8 2p /2p serial control register_0 scr_0 8 h'fff82 sci_0 8 2p /2p transmit data register_0 tdr_0 8 h'fff83 sci_0 8 2p /2p serial status register_0 ssr_0 8 h'fff84 sci_0 8 2p /2p receive data register_0 rdr_0 8 h'fff85 sci_0 8 2p /2p smart card mode register_0 scmr_0 8 h'fff86 sci_0 8 2p /2p serial mode register_1 smr_1 8 h'fff88 sci_1 8 2p /2p bit rate register_1 brr_1 8 h'fff89 sci_1 8 2p /2p serial control register_1 scr_1 8 h'fff8a sci_1 8 2p /2p transmit data register_1 tdr_1 8 h'fff8b sci_1 8 2p /2p serial status register_1 ssr_1 8 h'fff8c sci_1 8 2p /2p receive data register_1 rdr_1 8 h'fff8d sci_1 8 2p /2p smart card mode register_1 scmr_1 8 h'fff8e sci_1 8 2p /2p a/d data register a_0 addra_0 16 h'fff90 a/d_0 16 2p /2p a/d data register b_0 addrb_0 16 h'fff92 a/d_0 16 2p /2p a/d data register c_0 addrc_0 16 h'fff94 a/d_0 16 2p /2p a/d data register d_0 addrd_0 16 h'fff96 a/d_0 16 2p /2p a/d data register e_0 addre_0 16 h'fff98 a/d_0 16 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1216 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) a/d data register f_0 addrf_0 16 h'fff9a a/d_0 16 2p /2p a/d data register g_0 addrg_0 16 h'fff9c a/d_0 16 2p /2p a/d data register h_0 addrh_0 16 h'fff9e a/d_0 16 2p /2p a/d control/status register_0 adcsr_0 8 h'fffa0 a/d_0 16 2p /2p a/d control register_0 adcr_0 8 h'fffa1 a/d_0 16 2p /2p a/d mode selection register_0 admosel_0 8 h'fffa2 a/d_0 16 2p /2p timer control/status register tcsr 8 h'fffa4 wdt 16 2p /3p timer counter tcnt 8 h'fffa5 wdt 16 2p /3p reset control/status register rstcsr 8 h'fffa7 wdt 16 2p /3p timer control register_0 tcr_0 8 h'fffb0 tmr_0 16 2p /2p timer control register_1 tcr_1 8 h'fffb1 tmr_1 16 2p /2p timer control/status register _0 tcsr_0 8 h'fffb2 tmr_0 16 2p /2p timer control/status register _1 tcsr_1 8 h'fffb3 tmr_1 16 2p /2p time constant register a_0 tcora_0 8 h'fffb4 tmr_0 16 2p /2p time constant register a_1 tcora_1 8 h'fffb5 tmr_1 16 2p /2p time constant register b_0 tcorb_0 8 h'fffb6 tmr_0 16 2p /2p time constant register b_1 tcorb_1 8 h'fffb7 tmr_1 16 2p /2p timer counter_0 tcnt_0 8 h'fffb8 tmr_0 16 2p /2p timer counter_1 tcnt_1 8 h'fffb9 tmr_1 16 2p /2p timer counter control register_0 tccr_0 8 h'fffba tmr_0 16 2p /2p timer counter control register_1 tccr_1 8 h'fffbb tmr_1 16 2p /2p timer start register ts tr 8 h'fffbc tpu 16 2p /2p timer synchronous register tsyr 8 h'fffbd tpu 16 2p /2p timer control register_0 tcr_0 8 h'fffc0 tpu_0 16 2p /2p timer mode register_0 tmdr_0 8 h'fffc1 tpu_0 16 2p /2p timer i/o control register h_0 tiorh_0 8 h'fffc2 tpu_0 16 2p /2p timer i/o control register l_0 tiorl_0 8 h'fffc3 tpu_0 16 2p /2p timer interrupt enable register_0 tier_0 8 h'fffc4 tpu_0 16 2p /2p timer status register_0 tsr_0 8 h'fffc5 tpu_0 16 2p /2p timer counter_0 tcnt_0 16 h'fffc6 tpu_0 16 2p /2p timer general register a_0 tgra_0 16 h'fffc8 tpu_0 16 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1217 of 1340 rej09b0499-0200 register name abbreviation number of bits address module data width access cycles (read/write) timer general register b_0 tgrb_0 16 h'fffca tpu_0 16 2p /2p timer general register c_0 tgrc_0 16 h'fffcc tpu_0 16 2p /2p timer general register d_0 tgrd_0 16 h'fffce tpu_0 16 2p /2p timer control register_1 tcr_1 8 h'fffd0 tpu_1 16 2p /2p timer mode register_1 tmdr_1 8 h'fffd1 tpu_1 16 2p /2p timer i/o control register_1 tior_1 8 h'fffd2 tpu_1 16 2p /2p timer interrupt enable register_1 tier_1 8 h'fffd4 tpu_1 16 2p /2p timer status register_1 tsr_1 8 h'fffd5 tpu_1 16 2p /2p timer counter_1 tcnt_1 16 h'fffd6 tpu_1 16 2p /2p timer general register a_1 tgra_1 16 h'fffd8 tpu_1 16 2p /2p timer general register b_1 tgrb_1 16 h'fffda tpu_1 16 2p /2p timer control register_2 tcr_2 8 h'fffe0 tpu_2 16 2p /2p timer mode register_2 tmdr_2 8 h'fffe1 tpu_2 16 2p /2p timer i/o control register_2 tior_2 8 h'fffe2 tpu_2 16 2p /2p timer interrupt enable register_2 tier_2 8 h'fffe4 tpu_2 16 2p /2p timer status register_2 tsr_2 8 h'fffe5 tpu_2 16 2p /2p timer counter_2 tcnt_2 16 h'fffe6 tpu_2 16 2p /2p timer general register a_2 tgra_2 16 h'fffe8 tpu_2 16 2p /2p timer general register b_2 tgrb_2 16 h'fffea tpu_2 16 2p /2p timer control register_3 tcr_3 8 h'ffff0 tpu_3 16 2p /2p timer mode register_3 tmdr_3 8 h'ffff1 tpu_3 16 2p /2p timer i/o control register h_3 tiorh_3 8 h'ffff2 tpu_3 16 2p /2p timer i/o control register l_3 tiorl_3 8 h'ffff3 tpu_3 16 2p /2p timer interrupt enable register_3 tier_3 8 h'ffff4 tpu_3 16 2p /2p timer status register_3 tsr_3 8 h'ffff5 tpu_3 16 2p /2p timer counter_3 tcnt_3 16 h'ffff6 tpu_3 16 2p /2p timer general register a_3 tgra_3 16 h'ffff8 tpu_3 16 2p /2p timer general register b_3 tgrb_3 16 h'ffffa tpu_3 16 2p /2p timer general register c_3 tgrc_3 16 h'ffffc tpu_3 16 2p /2p timer general register d_3 tgrd_3 16 h'ffffe tpu_3 16 2p /2p section 28 list of registers rev. 2.00 oct. 20, 2009 page 1218 of 1340 rej09b0499-0200 notes: 1. when the same output trigger is specif ied for pulse output groups 2 and 3 by the pcr setting, the ndrh address is h'fff7c. when di fferent output triggers are specified, the ndrh addresses for pulse output groups 2 and 3 are h'fff7e and h'fff7c, respectively. similarly, when the same output trigger is specified for pulse output groups 0 and 1 by the pcr setting, the ndrl addr ess is h'fff7d. when different output triggers are specified, the ndrl addre sses for pulse output groups 0 and 1 are h'fff7f and h'fff7d, respectively. when the same output trigger is specified for pulse output groups 6 and 7 by the pcr setting, the ndrh address is h'ff63c. when diffe rent output triggers are specified, the ndrh addresses for pulse output groups 6 and 7 are h'ff63e and h'ff63c, respectively. when the same output trigger is specified fo r pulse output groups 4 and 5 by the pcr setting, the ndrl address is h'ff63d. when di fferent output triggers are specified, the ndrl addresses for pulse output groups 4 and 5 are h'ff63f and h'ff63d, respectively. 2. supported only by the h8sx/1655m group. section 28 list of registers rev. 2.00 oct. 20, 2009 page 1219 of 1340 rej09b0499-0200 28.2 register bits register addresses and bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcr_4 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_4 tcr_5 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_5 tcsr_4 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_4 tcsr_5 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_5 tcora_4 tmr_4 tcora_5 tmr_5 tcorb_4 tmr_4 tcorb_5 tmr_5 tcnt_4 tmr_4 tcnt_5 tmr_5 tccr_4 ? ? ? ? tmris ? icks1 icks0 tmr_4 tccr_5 ? ? ? ? tmris ? icks1 icks0 tmr_5 crccr dorclr ? ? ? ? lms g1 g0 crcdir crcdor crc tcr_6 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_6 tcr_7 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_7 tcsr_6 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_6 tcsr_7 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_7 tcora_6 tmr_6 tcora_7 tmr_7 tcorb_6 tmr_6 tcorb_7 tmr_7 tcnt_6 tmr_6 tcnt_7 tmr_7 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1220 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tccr_6 ? ? ? ? tmris ? icks1 icks0 tmr_6 tccr_7 ? ? ? ? tmris ? icks1 icks0 tmr_7 addra_1 addrb_1 addrc_1 addrd_1 addre_1 addrf_1 addrg_1 addrh_1 adcsr_1 adf adie adst excks ch3 ch2 ch1 ch0 adcr_1 trgs1 trgs0 scane scan s cks1 cks0 adstclr extrgs admosel_1 ? ? ? ? ? ? icksel ? adsstr_1 smp7 smp6 smp5 sm p4 smp3 smp2 smp1 smp0 a/d_1 ifr0 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts ifr1 ? ? ? ? vbus mn ep3 tr ep3 ts vbusf ifr2 ? ? surss sursf cfdn ? setc seti ier0 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts ier1 ? ? ? ? ? ep3 tr ep3 ts vbusf ier2 ssrsme ? ? surse cfdn ? setce setie isr0 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts usb section 28 list of registers rev. 2.00 oct. 20, 2009 page 1221 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module isr1 ? ? ? ? ? ep3 tr ep3 ts vbusf isr2 ? ? ? surse cfdn ? setce setie epdr0i d7 d6 d5 d4 d3 d2 d1 d0 epdr0o d7 d6 d5 d4 d3 d2 d1 d0 epdr0s d7 d6 d5 d4 d3 d2 d1 d0 epdr1 d7 d6 d5 d4 d3 d2 d1 d0 epdr2 d7 d6 d5 d4 d3 d2 d1 d0 epdr3 d7 d6 d5 d4 d3 d2 d1 d0 epsz0o ? ? ? ? ? ? ? ? epsz1 ? ? ? ? ? ? ? ? dasts ? ? ep3 de ep2 de ? ? ? ep0i de fclr ? ep3 clr ep1 clr ep2 clr ? ? ep0o clr ep0i clr epstl ? ? ? ? ep3stl ep2stl ep1stl ep0stl trg ? ep3 pkte ep1 rdfn ep2 pkte ? ep0s rdfn ep0o rdfn ep0i pkte dma ? ? ? ? ? pullup_e ep2dmae ep1dmae cvr cnfv1 cnfv0 intv1 intv0 ? altv2 altv1 altv0 ctlr ? ? ? rwups rsme rwmd asce ? epir d7 d6 d5 d4 d3 d2 d1 d0 trntreg0 ptste ? ? ? suspend txenl txse0 txdata trntreg1 ? ? ? ? ? xver_data dpls dmns usb pmddr ? ? ? pm4ddr pm3ddr pm2ddr pm1ddr pm0ddr pmdr ? ? ? pm4dr pm3dr pm2dr pm1dr pm0dr portm ? ? ? pm4 pm3 pm2 pm1 pm0 pmicr ? ? ? pm4icr pm3icr pm2icr pm1icr pm0icr i/o port c/ a chr pe o/ e stop mp cks1 cks0 smr_5 * 1 (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) brr_5 scr_5 * 1 tie rie te re mpie teie cke1 cke0 tdr_5 sci_5 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1222 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tdre rdrf orer fer per tend mpb mpbt ssr_5 * 1 (ers) rdr_5 scmr_5 ? ? ? ? sdir sinv ? smif semr_5 ? ? ? abcs acs3 acs2 acs1 acs0 ircr ire ircks2 ircks1 ircks0 irtxinv irrxinv ? ? sci_5 c/ a chr pe o/ e stop mp cks1 cks0 smr_6 * 1 (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) brr_6 scr_6 * 1 tie rie te re mpie teie cke1 cke0 tdr_6 tdre rdrf orer fer per tend mpb mpbt ssr_6 * 1 (ers) rdr_6 scmr_6 ? ? ? ? sdir sinv ? smif semr_6 ? ? ? abcs acs3 acs2 acs1 acs0 sci_6 pcr_1 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 pmr_1 g3inv g2inv g1inv g0in v g3nov g2nov g1nov g0nov nderh_1 nder31 nder30 nder29 nder28 nder27 nder26 nder25 nder24 nderl_1 nder23 nder22 nder21 nder20 nder19 nder18 nder17 nder16 podrh_1 pod31 pod30 pod29 po d28 pod27 pod26 pod25 pod24 podrl_1 pod23 pod22 pod21 pod 20 pod19 pod18 pod17 pod16 ndrh_1 * 2 ndr31 ndr30 ndr29 ndr28 ndr27 ndr26 ndr25 ndr24 ndrl_1 * 2 ndr23 ndr22 ndr21 ndr20 ndr19 ndr18 ndr17 ndr16 ndrh_1 * 2 ? ? ? ? ndr27 ndr26 ndr25 ndr24 ndrl_1 * 2 ? ? ? ? ndr19 ndr18 ndr17 ndr16 ppg_1 bara31 bara30 bara29 bara28 bara27 bara26 bara25 bara24 barah bara23 bara22 bara21 bara20 bara19 bara18 bara17 bara16 ubc section 28 list of registers rev. 2.00 oct. 20, 2009 page 1223 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module bara15 bara14 bara13 bara12 bara11 bara10 bara9 bara8 baral bara7 bara6 bara5 bara4 bara3 bara2 bara1 bara0 bamra31 bamra30 bamra29 bamra28 bamra27 bamra26 bamra25 bamra24 bamrah bamra23 bamra22 bamra21 bamra20 bamra19 bamra18 bamra17 bamra16 bamra15 bamra14 bamra13 bamra12 bamra11 bamra10 bamra9 bamra8 bamral bamra7 bamra6 bamra5 bamra4 bamra3 bamra2 bamra1 bamra0 barb31 barb30 barb29 barb28 barb27 barb26 barb25 barb24 barbh barb23 barb22 barb21 barb20 barb19 barb18 barb17 barb16 barb15 barb14 barb13 barb12 barb11 barb10 barb9 barb8 barbl barb7 barb6 barb5 barb4 barb3 barb2 barb1 barb0 bamrb31 bamrb30 bamrb29 bamrb28 bam rb27 bamrb26 bamrb25 bamrb24 bamrbh bamrb23 bamrb22 bamrb21 bamrb20 bam rb19 bamrb18 bamrb17 bamrb16 bamrb15 bamrb14 bamrb13 bamrb12 bamrb11 bamrb10 bamrb9 bamrb8 bamrbl bamrb7 bamrb6 bamrb5 bamrb4 bamrb3 bamrb2 bamrb1 bamrb0 barc31 barc30 barc29 barc28 barc27 barc26 barc25 barc24 barch barc23 barc22 barc21 barc20 barc19 barc18 barc17 barc16 barc15 barc14 barc13 barc12 barc11 barc10 barc9 barc8 barcl barc7 barc6 barc5 barc4 barc3 barc2 barc1 barc0 bamrc31 bamrc30 bamrc29 bamrc28 bamrc27 bamrc26 bamrc25 bamrc24 bamrch bamrc23 bamrc22 bamrc21 bamrc20 bamrc19 bamrc18 bamrc17 bamrc16 bamrc15 bamrc14 bamrc13 bamrc12 bamrc11 bamrc10 bamrc9 bamrc8 bamrcl bamrc7 bamrc6 bamrc5 bamrc4 bamrc3 bamrc2 bamrc1 bamrc0 bard31 bard30 bard29 bard28 bard27 bard26 bard25 bard24 bardh bard23 bard22 bard21 bard20 bard19 bard18 bard17 bard16 bard15 bard14 bard13 bard12 bard11 bard10 bard9 bard8 bardl bard7 bard6 bard5 bard4 bard3 bard2 bard1 bard0 ? ? cmfcpa ? cpa2 cpa1 cpa0 ? brcra ? ? ida1 ida0 rwa1 rwa0 ? ? ? ? cmfcpb ? cpb2 cpb1 cpb0 ? brcrb ? ? idb1 idb0 rwb1 rwb0 ? ? ? ? cmfcpc ? cpc2 cpc1 cpc0 ? brcrc ? ? idc1 idc0 rwc1 rwc0 ? ? ubc section 28 list of registers rev. 2.00 oct. 20, 2009 page 1224 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ? ? dmfcpd ? cpd2 cpd1 cpd0 ? brcrd ? ? idd1 idd0 rwd1 rwd0 ? ? ubc adsstr_0 smp7 smp6 smp5 smp4 smp3 smp2 smp1 smp0 a/d_0 tstrb ? ? cst5 cst4 cst3 cst2 cst1 cst0 tsyrb ? ? sync5 sync4 sync3 sync2 sync1 sync0 tpu (unit 1) tcr_6 cclr2 cclr1 cclr0 ckeg 1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_6 ? ? bfb bfa md3 md2 md1 md0 tiorh_6 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_6 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_6 ? ? ? tciev tgied tgiec tgieb tgiea tsr_6 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_6 tgra_6 tgrb_6 tgrc_6 tgrd_6 tpu_6 tcr_7 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tmdr_7 ? ? ? ? md3 md2 md1 md0 tior_7 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_7 ? ? tcieu tciev ? ? tgieb tgiea tsr_7 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_7 tgra_7 tpu_7 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1225 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tgrb_7 tpu_7 tcr_8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_8 ? ? ? ? md3 md2 md1 md0 tior_8 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_8 ? ? tcieu tciev ? ? tgieb tgiea tsr_8 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_8 tgra_8 tgrb_8 tpu_8 tcr_9 cclr2 cclr1 cclr0 ckeg 1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_9 ? ? bfb bfa md3 md2 md1 md0 tiorh_9 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_9 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_9 ? ? ? tciev tgied tgiec tgieb tgiea tsr_9 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_9 tgra_9 tgrb_9 tgrc_9 tgrd_9 tpu_9 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1226 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcr_10 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tmdr_10 ? ? ? ? md3 md2 md1 md0 tior_10 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_10 ? ? tcieu tciev ? ? tgieb tgiea tsr_10 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_10 tgra_10 tgrb_10 tpu_10 tcr_11 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tmdr_11 ? ? ? ? md3 md2 md1 md0 tior_11 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_11 ? ? tcieu tciev ? ? tgieb tgiea tsr_11 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_11 tgra_11 tgrb_11 tpu_11 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr p6ddr ? ? p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr paddr pa7ddr pa6ddr pa5ddr pa4ddr pa3ddr pa2ddr pa1ddr pa0ddr pbddr ? ? ? ? pb3ddr pb2ddr pb1ddr pb0ddr pdddr pd7ddr pd6ddr pd5ddr pd4 ddr pd3ddr pd2ddr pd1ddr pd0ddr peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr pfddr ? ? ? pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr i/o port section 28 list of registers rev. 2.00 oct. 20, 2009 page 1227 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module p1icr p17icr p16icr p15icr p14icr p13icr p12icr p11icr p10icr p2icr p27icr p26icr p25icr p24icr p23icr p22icr p21icr p20icr p5icr p57icr p56icr p55icr p54icr p53icr p52icr p51icr p50icr p6icr ? ? p65icr p64icr p63icr p62icr p61icr p60icr paicr pa7icr pa6icr pa5icr pa4i cr pa3icr pa2icr pa1icr pa0icr pbicr ? ? ? ? pb3icr pb2icr pb1icr pb0icr pdicr pd7icr pd6icr pd5icr pd4icr pd3icr pd2icr pd1icr pd0icr peicr pe7icr pe6icr pe5icr pe4i cr pe3icr pe2icr pe1icr pe0icr pficr ? ? ? pf4icr pf3icr pf2icr pf1icr pf0icr porth ph7 ph6 ph5 ph 4 ph3 ph2 ph1 ph0 porti pi7 pi6 pi5 pi 4 pi3 pi2 pi1 pi0 portj pj7 pj6 pj5 pj 4 pj3 pj2 pj1 pj0 portk pk7 pk6 pk5 pk4 pk3 pk2 pk1 pk0 phdr ph7dr ph6dr ph5dr ph4dr ph3dr ph2dr ph1dr ph0dr pidr pi7dr pi6dr pi5dr pi4dr pi3dr pi2dr pi1dr pi0dr pjdr pj7dr pj6dr pj5dr pj4dr pj3dr pj2dr pj1dr pj0dr pkdr pk7dr pk6dr pk5dr pk4dr pk3dr pk2dr pk1dr pk0dr phddr ph7ddr ph6ddr ph5ddr ph4ddr ph3ddr ph2ddr ph1ddr ph0ddr piddr pi7ddr pi6ddr pi5ddr pi4ddr pi3ddr pi2ddr pi1ddr pi0ddr pjddr pj7ddr pj6ddr pj5ddr pj4ddr pj3ddr pj2ddr pj1ddr pj0ddr pkddr pk7ddr pk6ddr pk5ddr pk4ddr pk3ddr pk2ddr pk1ddr pk0ddr phicr ph7icr ph6icr ph5icr ph4icr ph3icr ph2icr ph1icr ph0icr piicr pi7icr pi6icr pi5icr pi4icr pi3icr pi2icr pi1icr pi0icr pjicr pj7icr pj6icr pj5icr pj4i cr pj3icr pj2icr pj1icr pj0icr pkicr pk7icr pk6icr pk5icr pk4i cr pk3icr pk2icr pk1icr pk0icr pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr pepcr pe7pcr pe6pcr pe5pcr pe4p cr pe3pcr pe2pcr pe1pcr pe0pcr pfpcr ? ? ? pf4pcr pf3pcr pf2pcr pf1pcr pf0pcr phpcr ph7pcr ph6pcr ph5pcr ph4pcr ph3pcr ph2pcr ph1pcr ph0pcr i/o port section 28 list of registers rev. 2.00 oct. 20, 2009 page 1228 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module pipcr pi7pcr pi6pcr pi 5pcr pi4pcr pi3pcr pi 2pcr pi1pcr pi0pcr pjpcr pj7pcr pj6pcr pj5pcr pj4pcr pj3pcr pj2pcr pj1pcr pj0pcr pkpcr pk7pcr pk6pcr pk5pcr pk4p cr pk3pcr pk2pcr pk1pcr pk0pcr p2odr p27odr p26odr p25odr p 24odr p23odr p22odr p21odr p20odr pfodr ? ? ? pf4odr pf3odr pf2odr pf1odr pf0odr pfcr0 cs7e cs6e cs5e cs4e cs3e cs2e cs1e cs0e pfcr1 cs7sa cs7sb cs6sa cs6sb cs5sa cs5sb ? ? pfcr2 ? cs2s bss bse ? rdwre asoe ? pfcr4 ? ? ? a20e a19e a18e a17e a16e pfcr6 ? lhwroe ? ? tclks ? ? ? pfcr7 dmas3a dmas3b dmas2a dmas2 b dmas1a dmas1b dmas0a dmas0b pfcr8 ? ? ? ? edmas1a edmas1b edmas0a edmas0b pfcr9 tpums5 tpums4 tpums3a tpums3b ? ? ? ? pfcra tpums11 tpums10 tpums9a tpums 9b tpums8 tpums7 tpums6a tpums6b pfcrb ? its14 ? ? its11 its10 its9 its8 pfcrc its7 its6 its5 its4 its3 its2 its1 its0 pfcrd pcjke ? ? ? ? ? ? ? i/o port ? ? ? ? ssi11 ssi10 ssi9 ssi8 ssier ssi7 ssi6 ssi5 ssi4 ssi3 ssi2 ssi1 ssi0 intc dpsbkr0 dkup07 dkup06 dkup05 dkup04 dkup03 dkup02 dkup01 dkup00 dpsbkr1 dkup17 dkup16 dkup15 dkup14 dkup13 dkup12 dkup11 dkup10 dpsbkr2 dkup27 dkup26 dkup25 dkup24 dkup23 dkup22 dkup21 dkup20 dpsbkr3 dkup37 dkup36 dkup35 dkup34 dkup33 dkup32 dkup31 dkup30 dpsbkr4 dkup47 dkup46 dkup45 dkup44 dkup43 dkup42 dkup41 dkup40 dpsbkr5 dkup57 dkup56 dkup55 dkup54 dkup53 dkup52 dkup51 dkup50 dpsbkr6 dkup67 dkup66 dkup65 dkup64 dkup63 dkup62 dkup61 dkup60 dpsbkr7 dkup77 dkup76 dkup75 dkup74 dkup73 dkup72 dkup71 dkup70 dpsbkr8 dkup87 dkup86 dkup85 dkup84 dkup83 dkup82 dkup81 dkup80 dpsbkr9 dkup97 dkup96 dkup95 dkup94 dkup93 dkup92 dkup91 dkup90 dpsbkr10 dkup107 dkup106 dkup105 dkup104 dkup103 dkup102 dkup101 dkup100 system section 28 list of registers rev. 2.00 oct. 20, 2009 page 1229 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dpsbkr11 dkup117 dkup116 dkup115 dkup114 dkup113 dkup112 dkup111 dkup110 dpsbkr12 dkup127 dkup126 dkup125 dkup124 dkup123 dkup122 dkup121 dkup120 dpsbkr13 dkup137 dkup136 dkup135 dkup134 dkup133 dkup132 dkup131 dkup130 dpsbkr14 dkup147 dkup146 dkup145 dkup144 dkup143 dkup142 dkup141 dkup140 dpsbkr15 dkup157 dkup156 dkup155 dkup154 dkup153 dkup152 dkup151 dkup150 system dsar_0 ddar_0 dofr_0 dtcr_0 bkszh31 bkszh30 bkszh29 bkszh28 bkszh27 bkszh26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 dbsr_0 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dte dacke tende ? dreqs nrd ? ? act ? ? ? errf ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie dmdr_0 dtf1 dtf0 dta ? ? dmap2 dmap1 dmap0 dmac_0 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1230 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 dacr_0 darie ? ? dara4 dara3 dara2 dara1 dara0 dmac_0 dsar_1 ddar_1 dofr_1 dtcr_1 bkszh31 bkszh30 bkszh 29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 dbsr_1 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dte dacke tende ? dreqs nrd ? ? act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie dmdr_1 dtf1 dtf0 dta ? ? dmap2 dmap1 dmap0 dmac_1 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1231 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 dacr_1 darie ? ? dara4 dara3 dara2 dara1 dara0 dmac_1 dsar_2 ddar_2 dofr_2 dtcr_2 bkszh31 bkszh30 bkszh 29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 dbsr_2 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dte dacke tende ? dreqs nrd ? ? act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie dmdr_2 dtf1 dtf0 dta ? ? dmap2 dmap1 dmap0 dmac_2 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1232 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 dacr_2 darie ? ? dara4 dara3 dara2 dara1 dara0 dmac_2 dsar_3 ddar_3 dofr_3 dtcr_3 bkszh31 bkszh30 bkszh 29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 dbsr_3 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dte dacke tende ? dreqs nrd ? ? act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie dmdr_3 dtf1 dtf0 dta ? ? dmap2 dmap1 dmap0 dmac_3 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1233 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 dacr_3 darie ? ? dara4 dara3 dara2 dara1 dara0 dmac_3 edsar_0 eddar_0 edofr_0 edtcr_0 bkszh31 bkszh30 bkszh 29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 edbsr_0 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dte edacke etende edrake edreqs nrd ? ? act ? ? ? errf ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie edmdr_0 dtf1 dtf0 ? ? ? edmap2 demap1 edmap0 exdmac_0 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1234 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 edacr_0 darie ? ? dara4 dara3 dara2 dara1 dara0 exdmac_0 edsar_1 eddar_1 edofr_1 edtcr_1 bkszh31 bkszh30 bkszh 29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 edbsr_1 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dte edacke etende edrake edreqs nrd ? ? act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie edmdr_1 dtf1 dtf0 ? ? ? edmap2 demap1 edmap0 exdmac_1 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1235 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 edacr_1 darie ? ? dara4 dara3 dara2 dara1 dara0 exdmac_1 edsar_2 eddar_2 edofr_2 edtcr_2 bkszh31 bkszh30 bkszh 29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 edbsr_2 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dte edacke etende edrake edreqs nrd ? ? act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie edmdr_2 dtf1 dtf0 ? ? ? edmap2 demap1 edmap0 exdmac_2 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1236 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 edacr_2 darie ? ? dara4 dara3 dara2 dara1 dara0 exdmac_2 edsar_3 eddar_3 edofr_3 edtcr_3 bkszh31 bkszh30 bkszh 29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 edbsr_3 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dte edacke etende edrake edreqs nrd ? ? act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie edmdr_3 dtf1 dtf0 ? ? ? edmap2 demap1 edmap0 exdmac_3 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1237 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 edacr_3 darie ? ? dara4 dara3 dara2 dara1 dara0 exdmac_3 clsbr0 clsbr1 clsbr2 clsbr3 clsbr4 clsbr5 exdmac section 28 list of registers rev. 2.00 oct. 20, 2009 page 1238 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module clsbr6 clsbr7 exdmac dmrsr_0 dmac_0 dmrsr_1 dmac_1 dmrsr_2 dmac_2 dmrsr_3 dmac_3 ? ipra14 ipra13 ipra12 ? ipra10 ipra9 ipra8 ipra ? ipra6 ipra5 ipra4 ? ipra2 ipra1 ipra0 ? iprb14 iprb13 iprb12 ? iprb10 iprb9 iprb8 iprb ? iprb6 iprb5 iprb4 ? iprb2 iprb1 iprb0 ? iprc14 iprc13 iprc12 ? iprc10 iprc9 iprc8 iprc ? iprc6 iprc5 iprc4 ? iprc2 iprc1 iprc0 ? ? ? ? ? ipre10 ipre9 ipre8 ipre ? ? ? ? ? ? ? ? ? ? ? ? ? iprf10 iprf9 iprf8 iprf ? iprf6 iprf5 iprf4 ? iprf2 iprf1 iprf0 ? iprg14 iprg13 iprg12 ? iprg10 iprg9 iprg8 iprg ? iprg6 iprg5 iprg4 ? iprg2 iprg1 iprg0 ? iprh14 iprh13 iprh12 ? iprh10 iprh9 iprh8 iprh ? iprh6 iprh5 iprh4 ? iprh2 iprh1 iprh0 ? ipri14 ipri13 ipri12 ? ipri10 ipri9 ipri8 ipri ? ipri6 ipri5 ipri4 ? ipri2 ipri1 ipri0 ? iprij4 iprj13 iprj12 ? iprj10 iprj9 iprj8 iprj ? iprj6 iprj5 iprj4 ? iprj2 iprj1 iprj0 intc section 28 list of registers rev. 2.00 oct. 20, 2009 page 1239 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ? iprk14 iprk13 iprk12 ? iprk10 iprk9 iprk8 iprk ? iprk6 iprk5 iprk4 ? iprk2 iprk1 iprk0 ? iprl14 iprl13 iprl12 ? ? ? ? iprl ? iprl6 iprl5 iprl4 ? iprl2 iprl1 iprl0 ? iprm14 iprm13 iprm12 ? iprm10 iprm9 iprm8 iprm ? iprm6 iprm5 iprm4 ? iprm2 iprm1 iprm0 ? iprn14 iprn13 iprn12 ? iprn10 iprn9 iprn8 iprn ? iprn6 iprn5 iprn4 ? iprn2 iprn1 iprn0 ? ipro14 ipro13 ipro12 ? ipro10 ipro9 ipro8 ipro ? ipro6 ipro5 ipro4 ? ? ? ? ? ? ? ? ? ? ? ? iprq ? iprq6 iprq5 iprq4 ? iprq2 iprq1 iprq0 ? iprr14 iprr13 iprr12 ? iprr10 iprr9 iprr8 iprr ? iprr6 iprr5 iprr4 ? iprr2 iprr1 iprr0 ? ? ? ? ? ? ? ? iscrh irq11sr irq11sf irq10sr irq10sf irq9sr irq9sf irq8sr irq8sf irq7sr irq7sf irq6sr irq6sf irq5sr irq5sf irq4sr irq4sf iscrl irq3sr irq3sf irq2sr irq2sf irq1sr irq1sf irq0sr irq0sf intc dtcvbr abwh7 abwh6 abwh5 abwh4 abwh3 abwh2 abwh1 abwh0 abwcr abwl7 abwl6 abwl5 abwl4 abwl3 abwl2 abwl1 abwl0 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 astcr ? ? ? ? ? ? ? ? ? w72 w71 w70 ? w62 w61 w60 wtcra ? w52 w51 w50 ? w42 w41 w40 ? w32 w31 w30 ? w22 w21 w20 wtcrb ? w12 w11 w10 ? w02 w01 w00 bsc section 28 list of registers rev. 2.00 oct. 20, 2009 page 1240 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module rdn7 rdn6 rdn5 rdn4 rdn3 rdn2 rdn1 rdn0 rdncr ? ? ? ? ? ? ? ? csxh7 csxh6 csxh5 csxh4 csxh3 csxh2 csxh1 csxh0 csacr csxt7 csxt6 csxt 5 csxt4 csxt3 c sxt2 csxt1 csxt0 idls3 idls2 idls1 idls0 idlc b1 idlcb0 idlca1 idlca0 idlcr idlsel7 idlsel6 idlsel5 idlsel4 idlsel3 idlsel2 idlsel1 idlsel0 brle breqoe ? ? ? ? wdbe waite bcr1 dkc ? ? ? ? ? ? ? bcr2 ? ? ebccs ibccs ? ? ? pwdbe endiancr le7 le6 le5 le4 le3 le2 ? ? bcsel7 bcsel6 bcsel5 bcsel4 bcsel3 bcsel2 bcsel1 bcsel0 sramcr ? ? ? ? ? ? ? ? bsrm0 bsts02 bsts01 bsts00 ? ? bswd01 bswd00 bromcr bsrm1 bsts12 bsts11 bsts10 ? ? bswd11 bswd10 mpxe7 mpxe6 mpxe5 mpxe4 mpxe3 ? ? ? mpxcr ? ? ? ? ? ? ? addex ramer ? ? ? ? rams ram2 ram1 ram0 bsc ? ? ? ? mds3 mds2 mds1 mds0 mdcr ? ? ? ? ? ? ? ? ? ? macs ? fetchmd ? expe rame syscr ? ? ? ? ? ? dtcmd ? pstop1 ? ? ? ? ick2 ick1 ick0 sckcr ? pck2 pck1 pck0 ? bck2 bck1 bck0 ssby ope ? sts4 sts3 sts2 sts1 sts0 sbycr slpie ? ? ? ? ? ? ? acse mstpa14 mstpa13 mstpa12 ms tpa11 mstpa10 mstpa9 mstpa8 mstpcra mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 mstpb15 mstpb14 mstpb13 mstpb12 mstpb11 mstpb10 mstpb9 mstpb8 mstpcrb mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 system section 28 list of registers rev. 2.00 oct. 20, 2009 page 1241 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module mstpc15 mstpc14 mstpc13 mstpc12 mstpc11 mstpc10 mstpc9 mstpc8 mstpcrc mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstp c2 mstpc1 mstpc0 system fccs ? ? ? fler ? ? ? sco fpcs ? ? ? ? ? ? ? ppvs fecs ? ? ? ? ? ? ? epvb fkey k7 k6 k5 k4 k3 k2 k1 k0 fmats ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 ftdar tder tda6 tda5 tda4 tda3 tda2 tda1 tda0 flash dpsbycr dpsby iokeep ramcut2 ramcut1 ? ? ? ramcut0 dpswcr ? ? wtsts5 wtsts4 wtsts3 wtsts2 wtsts1 wtsts0 dpsier ? dusbie ? dlvdie dirq3e dirq2e dirq1e dirq0e dpsifr dnmif dusbif ? dlvdif dirq3f dirq2f dirq1f dirq0f dpsiegr dnmieg ? ? ? dirq3eg dirq2eg dirq1eg dirq0eg rstsr dpsrstf ? ? ? ? lvdf ? porf lvdcr * 3 lvde lvdri ? lvdmon ? ? ? ? system semr_2 ? ? ? ? abcs acs2 acs1 acs0 sci_2 smr_4 * 1 c/ a (gm) chr (blk) pe (pe) o/ e (o/ e ) stop (bcp1) mp (bcp0) cks1 cks0 brr_4 scr_4 * 1 tie rie te re mpie teie cke1 cke0 tdr_4 ssr_4 * 1 tdre rdrf orer fer (ers) per tend mpb mpbt rdr_4 scmr_4 ? ? ? ? sdir sinv ? smif sci_4 iccra_0 ice rcvd mst trs cks3 cks2 cks1 cks0 iccrb_0 bbsy scp sdao ? sclo ? iicrst ? icmr_0 ? wait ? ? bcwp bc2 bc1 bc0 icier_0 tie teie rie naki e stie acke ackbr ackbt icsr_0 tdre tend rdrf nackf stop al aas adz sar_0 sva6 sva5 sva4 sva3 sva2 sva1 sva0 ? iic2_0 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1242 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module icdrt_0 icdrr_0 iic2_0 iccra_1 ice rcvd mst trs cks3 cks2 cks1 cks0 iccrb_1 bbsy scp sdao ? sclo ? iicrst ? icmr_1 ? wait ? ? bcwp bc2 bc1 bc0 icier_1 tie teie rie naki e stie acke ackbr ackbt icsr_1 tdre tend rdrf nackf stop al aas adz sar_1 sva6 sva5 sva4 sva3 sva2 sva1 sva0 ? icdrt_1 icdrr_1 iic2_1 tcr_2 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_2 tcr_3 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_3 tcsr_2 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_2 tcsr_3 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_3 tcora_2 tmr_2 tcora_3 tmr_3 tcorb_2 tmr_2 tcorb_3 tmr_3 tcnt_2 tmr_2 tcnt_3 tmr_3 tccr_2 ? ? ? ? tmris ? icks1 icks0 tmr_2 tccr_3 ? ? ? ? tmris ? icks1 icks0 tmr_3 tcr_4 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tmdr_4 ? ? ? ? md3 md2 md1 md0 tior_4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_4 ttge ? tcieu tciev ? ? tgieb tgiea tsr_4 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_4 tpu_4 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1243 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tgra_4 tgrb_4 tpu_4 tcr_5 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_5 ? ? ? ? md3 md2 md1 md0 tior_5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_5 ttge ? tcieu tciev ? ? tgieb tgiea tsr_5 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_5 tgra_5 tgrb_5 tpu_5 dtcea15 dtcea14 dtcea13 dtcea12 dtcea11 dtcea10 dtcea9 dtcea8 dtcera dtcea7 dtcea6 dtcea5 dtcea4 ? ? ? ? dtceb15 ? dtceb13 dtceb12 dtceb11 dtceb10 dtceb9 dtceb8 dtcerb dtceb7 dtceb6 dtceb5 dtceb4 dtceb3 dtceb2 dtceb1 dtceb0 dtcec15 dtcec14 dtcec13 dtcec12 dtcec11 dtcec10 dtcec9 dtcec8 dtcerc dtcec7 dtcec6 dtcec5 dtcec4 dtcec3 dtce c2 dtcec1 dtcec0 dtced15 dtced14 dtced13 dtced12 dtced11 dtced10 dtced9 dtced8 dtcerd dtced7 dtced6 dtced5 dtced4 dtced3 dtce d2 dtced1 dtced0 ? ? dtcee13 dtcee12 dtcee11 dtcee10 dtcee9 dtcee8 dtcere dtcee7 dtcee6 dtcee5 dtcee4 dtcee3 dtcee2 dtcee1 dtcee0 dtcef15 dtcef14 ? ? dtcef11 dtcef10 dtcef9 ? dtcerf ? ? ? ? ? ? ? ? dtccr ? ? ? rrs rchne ? ? err intcr ? ? intm1 intm0 nmieg ? ? ? cpupcr cpupce dtcp2 dtcp1 dt cp0 ipsete cpup2 cpup1 cpup0 intc section 28 list of registers rev. 2.00 oct. 20, 2009 page 1244 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ? ? ? ? irq11e irq10e irq9e irq8e ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e ? ? ? ? irq11f irq10f irq9f irq8f isr irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f intc port1 p17 p16 p15 p14 p13 p12 p11 p10 port2 p27 p26 p25 p24 p23 p22 p21 p20 port5 p57 p56 p55 p54 p53 p52 p51 p50 port6 ? ? p65 p64 p63 p62 p61 p60 porta pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 portb ? ? ? ? pb3 pb2 pb1 pb0 portd pd7 pd6 pd5 pd 4 pd3 pd2 pd1 pd0 porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 portf ? ? ? pf4 pf3 pf2 pf1 pf0 p1dr p17dr p16dr p15dr p14 dr p13dr p12dr p11dr p10dr p2dr p27dr p26dr p25dr p24 dr p23dr p22dr p21dr p20dr p6dr ? ? p65dr p64dr p63dr p62dr p61dr p60dr padr pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr pbdr ? ? ? ? pb3dr pb2dr pb1dr pb0dr pddr pd7dr pd6dr pd5dr pd4 dr pd3dr pd2dr pd1dr pd0dr pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr pfdr ? ? ? pf4dr pf3dr pf2dr pf1dr pf0dr i/o port smr_2 * 1 c/ a (gm) chr (blk) pe (pe) o/ e (o/ e ) stop (bcp1) mp (bcp0) cks1 cks0 brr_2 scr_2 * 1 tie rie te re mpie teie cke1 cke0 tdr_2 ssr_2 * 1 tdre rdrf orer fer (ers) per tend mpb mpbt rdr_2 scmr_2 ? ? ? ? sdir sinv ? smif sci_2 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1245 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dadr0h dadr1h dacr01 daoe1 daoe0 dae ? ? ? ? ? dadr01t dadt1 dadt0 dad1l1 dad1l0 dad0l1 dad0l0 ? ? d/a pcr g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 pmr g3inv g2inv g1inv g0inv g3nov g2nov g1nov g0nov nderh nder15 nder14 nder13 nder 12 nder11 nder10 nder9 nder8 nderl nder7 nder6 nder5 nder 4 nder3 nder2 nder1 nder0 podrh pod15 pod14 pod13 pod 12 pod11 pod10 pod9 pod8 podrl pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 ndrh * 2 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 ndrl * 2 ndr7 ndr6 ndr5 ndr4 nd r3 ndr2 ndr1 ndr0 ndrh * 2 ? ? ? ? ndr11 ndr10 ndr9 ndr8 ndrl * 2 ? ? ? ? ndr3 ndr2 ndr1 ndr0 ppg_0 smr_0 * 1 c/ a (gm) chr (blk) pe (pe) o/ e (o/ e ) stop (bcp1) mp (bcp0) cks1 cks0 brr_0 scr_0 * 1 tie rie te re mpie teie cke1 cke0 tdr_0 ssr_0 * 1 tdre rdrf orer fer (ers) per tend mpb mpbt rdr_0 scmr_0 ? ? ? ? sdir sinv ? smif sci_0 smr_1 * 1 c/ a (gm) chr (blk) pe (pe) o/ e (o/ e ) stop (bcp1) mp (bcp0) cks1 cks0 brr_1 scr_1 * 1 tie rie te re mpie teie cke1 cke0 tdr_1 ssr_1 * 1 tdre rdrf orer fer (ers) per tend mpb mpbt sci_1 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1246 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module rdr_1 scmr_1 ? ? ? ? sdir sinv ? smif sci_1 addra_0 addrb_0 addrc_0 addrd_0 addre_0 addrf_0 addrg_0 addrh_0 adcsr_0 adf adie adst ? ch3 ch2 ch1 ch0 adcr_0 trgs1 trgs0 scan e scans cks1 cks0 ? extrgs admosel_0 ? ? ? ? ? ? icksel ? a/d_0 tcsr ovf wt/ it tme ? ? cks2 cks1 cks0 tcnt rstcsr wovf rste ? ? ? ? ? ? wdt tcr_0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_0 tcr_1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_1 tcsr_0 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_0 tcsr_1 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_1 tcora_0 tmr_0 tcora_1 tmr_1 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1247 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcorb_0 tmr_0 tcorb_1 tmr_1 tcnt_0 tmr_0 tcnt_1 tmr_1 tccr_0 ? ? ? ? tmris ? icks1 icks0 tmr_0 tccr_1 ? ? ? ? tmris ? icks1 icks0 tmr_1 tstr ? ? cst5 cst4 cst3 cst2 cst1 cst0 tsyr ? ? sync5 sync4 sync3 sync2 sync1 sync0 tpu tcr_0 cclr2 cclr1 cclr0 ckeg 1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_0 ? ? bfb bfa md3 md2 md1 md0 tiorh_0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_0 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_0 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_0 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_0 tgra_0 tgrb_0 tgrc_0 tgrd_0 tpu_0 tcr_1 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_1 ? ? ? ? md3 md2 md1 md0 tior_1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_1 ttge ? tcieu tciev ? ? tgieb tgiea tsr_1 tcfd ? tcfu tcfv ? ? tgfb tgfa tpu_1 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1248 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcnt_1 tgra_1 tgrb_1 tpu_1 tcr_2 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tmdr_2 ? ? ? ? md3 md2 md1 md0 tior_2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_2 ttge ? tcieu tciev ? ? tgieb tgiea tsr_2 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_2 tgra_2 tgrb_2 tpu_2 tcr_3 cclr2 cclr1 cclr0 ckeg 1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_3 ? ? bfb bfa md3 md2 md1 md0 tiorh_3 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_3 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_3 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_3 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_3 tgra_3 tgrb_3 tpu_3 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1249 of 1340 rej09b0499-0200 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tgrc_3 tgrd_3 tpu_3 notes: 1. parts of the bit functions differ in normal mode and the smart card interface. 2. when the same output trigger is specifie d for pulse output groups 2 and 3 by the pcr setting, the ndrh address is h'fff7c. when di fferent output triggers are specified, the ndrh addresses for pulse output groups 2 and 3 are h'fff7e and h'fff7c, respectively. similarly, when the same output trigger is specified for pulse output groups 0 and 1 by the pcr setting, the ndrl addr ess is h'fff7d. when different output triggers are specified, the ndrl addre sses for pulse output groups 0 and 1 are h'fff7f and h'fff7d, respectively. when the same output trigger is specified for pulse output groups 6 and 7 by the pcr setting, the ndrh address is h'ff63c. when diffe rent output triggers are specified, the ndrh addresses for pulse output groups 6 and 7 are h'ff63e and h'ff63c, respectively. when the same output trigger is specified fo r pulse output groups 4 and 5 by the pcr setting, the ndrl address is h'ff63d. when di fferent output triggers are specified, the ndrl addresses for pulse output groups 4 and 5 are h'ff63f and h'ff63d, respectively. 3. supported only by the h8sx/1655m group. section 28 list of registers rev. 2.00 oct. 20, 2009 page 1250 of 1340 rej09b0499-0200 28.3 register states in each operating mode register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module tcr_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcr_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tcsr_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcsr_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tcora_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcora_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tcorb_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcorb_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tcnt_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcnt_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tccr_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tccr_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 crccr initialized ? ? ? ? initialized * 1 initialized crcdir initialized ? ? ? ? initialized * 1 initialized crcdor initialized ? ? ? ? initialized * 1 initialized crc tcr_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcr_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tcsr_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcsr_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tcora_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcora_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tcorb_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcorb_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tcnt_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcnt_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tccr_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tccr_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1251 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module addra_1 initialized ? ? ? ? initialized * 1 initialized addrb_1 initialized ? ? ? ? initialized * 1 initialized addrc_1 initialized ? ? ? ? initialized * 1 initialized addrd_1 initialized ? ? ? ? initialized * 1 initialized addre_1 initialized ? ? ? ? initialized * 1 initialized addrf_1 initialized ? ? ? ? initialized * 1 initialized addrg_1 initialized ? ? ? ? initialized * 1 initialized addrh_1 initialized ? ? ? ? initialized * 1 initialized adcsr_1 initialized ? ? ? ? initialized * 1 initialized adcr_1 initialized ? ? ? ? initialized * 1 initialized admosel_1 initialized ? ? ? ? initialized * 1 initialized adsstr_1 initialized ? ? ? ? initialized * 1 initialized a/d_1 ifr0 initialized ? ? ? ? initialized * 2 initialized ifr1 initialized ? ? ? ? initialized * 2 initialized ifr2 initialized ? ? ? ? initialized * 2 initialized ier0 initialized ? ? ? ? initialized * 2 initialized ier1 initialized ? ? ? ? initialized * 2 initialized ier2 initialized ? ? ? ? initialized * 2 initialized isr0 initialized ? ? ? ? initialized * 2 initialized isr1 initialized ? ? ? ? initialized * 2 initialized isr2 initialized ? ? ? ? initialized * 2 initialized epdr0i initialized ? ? ? ? initialized * 2 initialized epdr0o initialized ? ? ? ? initialized * 2 initialized epdr0s initialized ? ? ? ? initialized * 2 initialized epdr1 initialized ? ? ? ? initialized * 2 initialized epdr2 initialized ? ? ? ? initialized * 2 initialized epdr3 initialized ? ? ? ? initialized * 2 initialized epsz0o initialized ? ? ? ? initialized * 2 initialized epsz1 initialized ? ? ? ? initialized * 2 initialized usb section 28 list of registers rev. 2.00 oct. 20, 2009 page 1252 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module dasts initialized ? ? ? ? initialized * 2 initialized fclr initialized ? ? ? ? initialized * 2 initialized epstl initialized ? ? ? ? initialized * 2 initialized trg initialized ? ? ? ? initialized * 2 initialized dma initialized ? ? ? ? initialized * 2 initialized cvr initialized ? ? ? ? initialized * 2 initialized ctlr initialized ? ? ? ? initialized * 2 initialized epir initialized ? ? ? ? initialized * 2 initialized trntreg0 initialized ? ? ? ? initialized * 2 initialized trntreg1 initialized ? ? ? ? initialized * 2 initialized usb pmddr initialized ? ? ? ? initialized * 1 initialized pmdr initialized ? ? ? ? initialized * 1 initialized portm ? ? ? ? ? ? ? pmicr initialized ? ? ? ? initialized * 1 initialized i/o port smr_5 initialized ? ? ? ? initialized * 1 initialized brr_5 initialized ? ? ? ? initialized * 1 initialized scr_5 initialized ? ? ? ? initialized * 1 initialized tdr_5 initialized initialized ? initialized initialized initialized * 1 initialized ssr_5 initialized initialized ? initialized initialized initialized * 1 initialized rdr_5 initialized initialized ? initialized initialized initialized * 1 initialized scmr_5 initialized ? ? ? ? initialized * 1 initialized semr_5 initialized ? ? ? ? initialized * 1 initialized ircr initialized ? ? ? ? initialized * 1 initialized sci_5 smr_6 initialized ? ? ? ? initialized * 1 initialized brr_6 initialized ? ? ? ? initialized * 1 initialized scr_6 initialized ? ? ? ? initialized * 1 initialized tdr_6 initialized initialized ? initialized initialized initialized * 1 initialized ssr_6 initialized initialized ? initialized initialized initialized * 1 initialized rdr_6 initialized initialized ? initialized initialized initialized * 1 initialized sci_6 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1253 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module scmr_6 initialized ? ? ? ? initialized * 1 initialized semr_6 initialized ? ? ? ? initialized * 1 initialized sci_6 pcr_1 initialized ? ? ? ? initialized * 1 initialized pmr_1 initialized ? ? ? ? initialized * 1 initialized nderh_1 initialized ? ? ? ? initialized * 1 initialized nderl_1 initialized ? ? ? ? initialized * 1 initialized podrh_1 initialized ? ? ? ? initialized * 1 initialized podrl_1 initialized ? ? ? ? initialized * 1 initialized ndrh_1 initialized ? ? ? ? initialized * 1 initialized ndrl_1 initialized ? ? ? ? initialized * 1 initialized ppg_1 barah initialized ? ? ? ? initialized * 1 initialized baral initialized ? ? ? ? initialized * 1 initialized bamrah initialized ? ? ? ? initialized * 1 initialized bamral initialized ? ? ? ? initialized * 1 initialized barbh initialized ? ? ? ? initialized * 1 initialized barbl initialized ? ? ? ? initialized * 1 initialized bamrbh initialized ? ? ? ? initialized * 1 initialized bamrbl initialized ? ? ? ? initialized * 1 initialized barch initialized ? ? ? ? initialized * 1 initialized barcl initialized ? ? ? ? initialized * 1 initialized bamrch initialized ? ? ? ? initialized * 1 initialized bamrcl initialized ? ? ? ? initialized * 1 initialized bardh initialized ? ? ? ? initialized * 1 initialized bardl initialized ? ? ? ? initialized * 1 initialized bamrdh initialized ? ? ? ? initialized * 1 initialized bamrdl initialized ? ? ? ? initialized * 1 initialized brcra initialized ? ? ? ? initialized * 1 initialized brcrb initialized ? ? ? ? initialized * 1 initialized brcrc initialized ? ? ? ? initialized * 1 initialized brcrd initialized ? ? ? ? initialized * 1 initialized ubc section 28 list of registers rev. 2.00 oct. 20, 2009 page 1254 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module adsstr_0 initialized ? ? ? ? initialized * 1 initialized a/d_0 tstrb initialized ? ? ? ? initialized * 1 initialized tsyrb initialized ? ? ? ? initialized * 1 initialized tpu (unit 1) tcr_6 initialized ? ? ? ? initialized * 1 initialized tmdr_6 initialized ? ? ? ? initialized * 1 initialized tiorh_6 initialized ? ? ? ? initialized * 1 initialized tiorl_6 initialized ? ? ? ? initialized * 1 initialized tier_6 initialized ? ? ? ? initialized * 1 initialized tsr_6 initialized ? ? ? ? initialized * 1 initialized tcnt_6 initialized ? ? ? ? initialized * 1 initialized tgra_6 initialized ? ? ? ? initialized * 1 initialized tgrb_6 initialized ? ? ? ? initialized * 1 initialized tgrc_6 initialized ? ? ? ? initialized * 1 initialized tgrd_6 initialized ? ? ? ? initialized * 1 initialized tpu_6 tcr_7 initialized ? ? ? ? initialized * 1 initialized tmdr_7 initialized ? ? ? ? initialized * 1 initialized tior_7 initialized ? ? ? ? initialized * 1 initialized tier_7 initialized ? ? ? ? initialized * 1 initialized tsr_7 initialized ? ? ? ? initialized * 1 initialized tcnt_7 initialized ? ? ? ? initialized * 1 initialized tgra_7 initialized ? ? ? ? initialized * 1 initialized tgrb_7 initialized ? ? ? ? initialized * 1 initialized tpu_7 tcr_8 initialized ? ? ? ? initialized * 1 initialized tmdr_8 initialized ? ? ? ? initialized * 1 initialized tior_8 initialized ? ? ? ? initialized * 1 initialized tpu_8 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1255 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module tier_8 initialized ? ? ? ? initialized * 1 initialized tsr_8 initialized ? ? ? ? initialized * 1 initialized tcnt_8 initialized ? ? ? ? initialized * 1 initialized tgra_8 initialized ? ? ? ? initialized * 1 initialized tgrb_8 initialized ? ? ? ? initialized * 1 initialized tcr_9 initialized ? ? ? ? initialized * 1 initialized tmdr_9 initialized ? ? ? ? initialized * 1 initialized tiorh_9 initialized ? ? ? ? initialized * 1 initialized tiorl_9 initialized ? ? ? ? initialized * 1 initialized tier_9 initialized ? ? ? ? initialized * 1 initialized tsr_9 initialized ? ? ? ? initialized * 1 initialized tcnt_9 initialized ? ? ? ? initialized * 1 initialized tgra_9 initialized ? ? ? ? initialized * 1 initialized tgrb_9 initialized ? ? ? ? initialized * 1 initialized tgrc_9 initialized ? ? ? ? initialized * 1 initialized tgrd_9 initialized ? ? ? ? initialized * 1 initialized tpu_9 tcr_10 initialized ? ? ? ? initialized * 1 initialized tmdr_10 initialized ? ? ? ? initialized * 1 initialized tior_10 initialized ? ? ? ? initialized * 1 initialized tier_10 initialized ? ? ? ? initialized * 1 initialized tsr_10 initialized ? ? ? ? initialized * 1 initialized tcnt_10 initialized ? ? ? ? initialized * 1 initialized tgra_10 initialized ? ? ? ? initialized * 1 initialized tgrb_10 initialized ? ? ? ? initialized * 1 initialized tpu_10 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1256 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module tcr_11 initialized ? ? ? ? initialized * 1 initialized tmdr_11 initialized ? ? ? ? initialized * 1 initialized tior_11 initialized ? ? ? ? initialized * 1 initialized tier_11 initialized ? ? ? ? initialized * 1 initialized tsr_11 initialized ? ? ? ? initialized * 1 initialized tcnt_11 initialized ? ? ? ? initialized * 1 initialized tgra_11 initialized ? ? ? ? initialized * 1 initialized tgrb_11 initialized ? ? ? ? initialized * 1 initialized tpu_11 p1ddr initialized ? ? ? ? initialized * 1 initialized p2ddr initialized ? ? ? ? initialized * 1 initialized p6ddr initialized ? ? ? ? initialized * 1 initialized paddr initialized ? ? ? ? initialized * 1 initialized pbddr initialized ? ? ? ? initialized * 1 initialized pdddr initialized ? ? ? ? initialized * 1 initialized peddr initialized ? ? ? ? initialized * 1 initialized pfddr initialized ? ? ? ? initialized * 1 initialized p1icr initialized ? ? ? ? initialized * 1 initialized p2icr initialized ? ? ? ? initialized * 1 initialized p5icr initialized ? ? ? ? initialized * 1 initialized p6icr initialized ? ? ? ? initialized * 1 initialized paicr initialized ? ? ? ? initialized * 1 initialized pbicr initialized ? ? ? ? initialized * 1 initialized pdicr initialized ? ? ? ? initialized * 1 initialized peicr initialized ? ? ? ? initialized * 1 initialized pficr initialized ? ? ? ? initialized * 1 initialized porth ? ? ? ? ? ? ? porti ? ? ? ? ? ? ? portj ? ? ? ? ? ? ? portk ? ? ? ? ? ? ? i/o port section 28 list of registers rev. 2.00 oct. 20, 2009 page 1257 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module phdr initialized ? ? ? ? initialized * 1 initialized pidr initialized ? ? ? ? initialized * 1 initialized pjdr initialized ? ? ? ? initialized * 1 initialized pkdr initialized ? ? ? ? initialized * 1 initialized phddr initialized ? ? ? ? initialized * 1 initialized piddr initialized ? ? ? ? initialized * 1 initialized pjddr initialized ? ? ? ? initialized * 1 initialized pkddr initialized ? ? ? ? initialized * 1 initialized phicr initialized ? ? ? ? initialized * 1 initialized piicr initialized ? ? ? ? initialized * 1 initialized pjicr initialized ? ? ? ? initialized * 1 initialized pkicr initialized ? ? ? ? initialized * 1 initialized pdpcr initialized ? ? ? ? initialized * 1 initialized pepcr initialized ? ? ? ? initialized * 1 initialized pfpcr initialized ? ? ? ? initialized * 1 initialized phpcr initialized ? ? ? ? initialized * 1 initialized pipcr initialized ? ? ? ? initialized * 1 initialized pjpcr initialized ? ? ? ? initialized * 1 initialized pkpcr initialized ? ? ? ? initialized * 1 initialized p2odr initialized ? ? ? ? initialized * 1 initialized pfodr initialized ? ? ? ? initialized * 1 initialized pfcr0 initialized ? ? ? ? initialized * 1 initialized pfcr1 initialized ? ? ? ? initialized * 1 initialized pfcr2 initialized ? ? ? ? initialized * 1 initialized pfcr4 initialized ? ? ? ? initialized * 1 initialized pfcr6 initialized ? ? ? ? initialized * 1 initialized pfcr7 initialized ? ? ? ? initialized * 1 initialized pfcr8 initialized ? ? ? ? initialized * 1 initialized pfcr9 initialized ? ? ? ? initialized * 1 initialized i/o port section 28 list of registers rev. 2.00 oct. 20, 2009 page 1258 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module pfcra initialized ? ? ? ? initialized * 1 initialized pfcrb initialized ? ? ? ? initialized * 1 initialized pfcrc initialized ? ? ? ? initialized * 1 initialized pfcrd initialized ? ? ? ? initialized * 1 initialized i/o port ssier initialized ? ? ? ? initialized * 1 initialized intc dpsbkr0 initialized ? ? ? ? ? initialized dpsbkr1 initialized ? ? ? ? ? initialized dpsbkr2 initialized ? ? ? ? ? initialized dpsbkr3 initialized ? ? ? ? ? initialized dpsbkr4 initialized ? ? ? ? ? initialized dpsbkr5 initialized ? ? ? ? ? initialized dpsbkr6 initialized ? ? ? ? ? initialized dpsbkr7 initialized ? ? ? ? ? initialized dpsbkr8 initialized ? ? ? ? ? initialized dpsbkr9 initialized ? ? ? ? ? initialized dpsbkr10 initialized ? ? ? ? ? initialized dpsbkr11 initialized ? ? ? ? ? initialized dpsbkr12 initialized ? ? ? ? ? initialized dpsbkr13 initialized ? ? ? ? ? initialized dpsbkr14 initialized ? ? ? ? ? initialized dpsbkr15 initialized ? ? ? ? ? initialized system dsar_0 initialized ? ? ? ? initialized * 1 initialized ddar_0 initialized ? ? ? ? initialized * 1 initialized dofr_0 initialized ? ? ? ? initialized * 1 initialized dtcr_0 initialized ? ? ? ? initialized * 1 initialized dbsr_0 initialized ? ? ? ? initialized * 1 initialized dmdr_0 initialized ? ? ? ? initialized * 1 initialized dacr_0 initialized ? ? ? ? initialized * 1 initialized dmac_0 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1259 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module dsar_1 initialized ? ? ? ? initialized * 1 initialized ddar_1 initialized ? ? ? ? initialized * 1 initialized dofr_1 initialized ? ? ? ? initialized * 1 initialized dtcr_1 initialized ? ? ? ? initialized * 1 initialized dbsr_1 initialized ? ? ? ? initialized * 1 initialized dmdr_1 initialized ? ? ? ? initialized * 1 initialized dacr_1 initialized ? ? ? ? initialized * 1 initialized dmac_1 dsar_2 initialized ? ? ? ? initialized * 1 initialized ddar_2 initialized ? ? ? ? initialized * 1 initialized dofr_2 initialized ? ? ? ? initialized * 1 initialized dtcr_2 initialized ? ? ? ? initialized * 1 initialized dbsr_2 initialized ? ? ? ? initialized * 1 initialized dmdr_2 initialized ? ? ? ? initialized * 1 initialized dacr_2 initialized ? ? ? ? initialized * 1 initialized dmac_2 dsar_3 initialized ? ? ? ? initialized * 1 initialized ddar_3 initialized ? ? ? ? initialized * 1 initialized dofr_3 initialized ? ? ? ? initialized * 1 initialized dtcr_3 initialized ? ? ? ? initialized * 1 initialized dbsr_3 initialized ? ? ? ? initialized * 1 initialized dmdr_3 initialized ? ? ? ? initialized * 1 initialized dacr_3 initialized ? ? ? ? initialized * 1 initialized dmac_3 edsar_0 initialized ? ? ? ? initialized * 1 initialized eddar_0 initialized ? ? ? ? initialized * 1 initialized edofr_0 initialized ? ? ? ? initialized * 1 initialized edtcr_0 initialized ? ? ? ? initialized * 1 initialized edbsr_0 initialized ? ? ? ? initialized * 1 initialized edmdr_0 initialized ? ? ? ? initialized * 1 initialized edacr_0 initialized ? ? ? ? initialized * 1 initialized exdmac_0 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1260 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module edsar_1 initialized ? ? ? ? initialized * 1 initialized eddar_1 initialized ? ? ? ? initialized * 1 initialized edofr_1 initialized ? ? ? ? initialized * 1 initialized edtcr_1 initialized ? ? ? ? initialized * 1 initialized edbsr_1 initialized ? ? ? ? initialized * 1 initialized edmdr_1 initialized ? ? ? ? initialized * 1 initialized edacr_1 initialized ? ? ? ? initialized * 1 initialized exdmac_1 edsar_2 initialized ? ? ? ? initialized * 1 initialized eddar_2 initialized ? ? ? ? initialized * 1 initialized edofr_2 initialized ? ? ? ? initialized * 1 initialized edtcr_2 initialized ? ? ? ? initialized * 1 initialized edbsr_2 initialized ? ? ? ? initialized * 1 initialized edmdr_2 initialized ? ? ? ? initialized * 1 initialized edacr_2 initialized ? ? ? ? initialized * 1 initialized exdmac_2 edsar_3 initialized ? ? ? ? initialized * 1 initialized eddar_3 initialized ? ? ? ? initialized * 1 initialized edofr_3 initialized ? ? ? ? initialized * 1 initialized edtcr_3 initialized ? ? ? ? initialized * 1 initialized edbsr_3 initialized ? ? ? ? initialized * 1 initialized edmdr_3 initialized ? ? ? ? initialized * 1 initialized edacr_3 initialized ? ? ? ? initialized * 1 initialized exdmac_3 clsbr0 ? ? ? ? ? ? ? clsbr1 ? ? ? ? ? ? ? clsbr2 ? ? ? ? ? ? ? clsbr3 ? ? ? ? ? ? ? clsbr4 ? ? ? ? ? ? ? clsbr5 ? ? ? ? ? ? ? clsbr6 ? ? ? ? ? ? ? clsbr7 ? ? ? ? ? ? ? exdmac section 28 list of registers rev. 2.00 oct. 20, 2009 page 1261 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module dmrsr_1 initialized ? ? ? ? initialized * 1 initialized dmac_1 dmrsr_1 initialized ? ? ? ? initialized * 1 initialized dmac_1 dmrsr_2 initialized ? ? ? ? initialized * 1 initialized dmac_2 dmrsr_3 initialized ? ? ? ? initialized * 1 initialized dmac_3 ipra initialized ? ? ? ? initialized * 1 initialized iprb initialized ? ? ? ? initialized * 1 initialized iprc initialized ? ? ? ? initialized * 1 initialized iprd initialized ? ? ? ? initialized * 1 initialized ipre initialized ? ? ? ? initialized * 1 initialized iprf initialized ? ? ? ? initialized * 1 initialized iprg initialized ? ? ? ? initialized * 1 initialized iprh initialized ? ? ? ? initialized * 1 initialized ipri initialized ? ? ? ? initialized * 1 initialized iprj initialized ? ? ? ? initialized * 1 initialized iprk initialized ? ? ? ? initialized * 1 initialized iprl initialized ? ? ? ? initialized * 1 initialized iprm initialized ? ? ? ? initialized * 1 initialized iprn initialized ? ? ? ? initialized * 1 initialized ipro initialized ? ? ? ? initialized * 1 initialized iprq initialized ? ? ? ? initialized * 1 initialized iprr initialized ? ? ? ? initialized * 1 initialized iscrh initialized ? ? ? ? initialized * 1 initialized iscrl initialized ? ? ? ? initialized * 1 initialized intc dtcvbr initialized ? ? ? ? initialized * 1 initialized abwcr initialized ? ? ? ? initialized * 1 initialized astcr initialized ? ? ? ? initialized * 1 initialized wtcra initialized ? ? ? ? initialized * 1 initialized wtcrb initialized ? ? ? ? initialized * 1 initialized rdncr initialized ? ? ? ? initialized * 1 initialized bsc section 28 list of registers rev. 2.00 oct. 20, 2009 page 1262 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module csacr initialized ? ? ? ? initialized * 1 initialized idlcr initialized ? ? ? ? initialized * 1 initialized bcr1 initialized ? ? ? ? initialized * 1 initialized bcr2 initialized ? ? ? ? initialized * 1 initialized endiancr initialized ? ? ? ? initialized * 1 initialized sramcr initialized ? ? ? ? initialized * 1 initialized bromcr initialized ? ? ? ? initialized * 1 initialized mpxcr initialized ? ? ? ? initialized * 1 initialized ramer initialized ? ? ? ? initialized * 1 initialized bsc mdcr initialized ? ? ? ? initialized * 1 initialized syscr initialized ? ? ? ? initialized * 1 initialized sckcr initialized ? ? ? ? initialized * 1 initialized sbycr initialized ? ? ? ? initialized * 1 initialized mstpcra initialized ? ? ? ? initialized * 1 initialized mstpcrb initialized ? ? ? ? initialized * 1 initialized mstpcrc initialized ? ? ? ? initialized * 1 initialized system fccs initialized ? ? ? ? initialized * 1 initialized fpcs initialized ? ? ? ? initialized * 1 initialized fec initialized ? ? ? ? initialized * 1 initialized fkey initialized ? ? ? ? initialized * 1 initialized fmats initialized ? ? ? ? initialized * 1 initialized ftdar initialized ? ? ? ? initialized * 1 initialized flash dpsbycr initialized ? ? ? ? ? initialized dpswcr initialized ? ? ? ? ? initialized dpsier initialized ? ? ? ? ? initialized dpsifr initialized ? ? ? ? ? initialized dpsiegr initialized ? ? ? ? ? initialized rstsr initialized ? ? ? ? ? initialized lvdcr * 3 initialized * 4 ? ? ? ? ? initialized system section 28 list of registers rev. 2.00 oct. 20, 2009 page 1263 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module semr_2 initialized ? ? ? ? initialized * 1 initialized sci_2 smr_4 initialized ? ? ? ? initialized * 1 initialized brr_4 initialized ? ? ? ? initialized * 1 initialized scr_4 initialized ? ? ? ? initialized * 1 initialized tdr_4 initialized initialized ? initialized initialized initialized * 1 initialized ssr_4 initialized initialized ? initialized initialized initialized * 1 initialized rdr_4 initialized initialized ? initialized initialized initialized * 1 initialized scmr_4 initialized ? ? ? ? initialized * 1 initialized sci_4 iccra_0 initialized ? ? ? ? initialized * 1 initialized iccrb_0 initialized ? ? ? ? initialized * 1 initialized icmr_0 initialized ? ? ? ? initialized * 1 initialized icier_0 initialized ? ? ? ? initialized * 1 initialized icsr_0 initialized ? ? ? ? initialized * 1 initialized sar_0 initialized ? ? ? ? initialized * 1 initialized icdrt_0 initialized ? ? ? ? initialized * 1 initialized icdrr_0 initialized ? ? ? ? initialized * 1 initialized iic2_0 iccra_1 initialized ? ? ? ? initialized * 1 initialized iccrb_1 initialized ? ? ? ? initialized * 1 initialized icmr_1 initialized ? ? ? ? initialized * 1 initialized icier_1 initialized ? ? ? ? initialized * 1 initialized icsr_1 initialized ? ? ? ? initialized * 1 initialized sar_1 initialized ? ? ? ? initialized * 1 initialized icdrt_1 initialized ? ? ? ? initialized * 1 initialized icdrr_1 initialized ? ? ? ? initialized * 1 initialized iic2_1 tcr_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcr_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcsr_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcsr_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcora_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1264 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module tcora_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcorb_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcorb_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcnt_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcnt_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tccr_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tccr_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcr_4 initialized ? ? ? ? initialized * 1 initialized tmdr_4 initialized ? ? ? ? initialized * 1 initialized tior_4 initialized ? ? ? ? initialized * 1 initialized tier_4 initialized ? ? ? ? initialized * 1 initialized tsr_4 initialized ? ? ? ? initialized * 1 initialized tcnt_4 initialized ? ? ? ? initialized * 1 initialized tgra_4 initialized ? ? ? ? initialized * 1 initialized tgrb_4 initialized ? ? ? ? initialized * 1 initialized tpu_4 tcr_5 initialized ? ? ? ? initialized * 1 initialized tmdr_5 initialized ? ? ? ? initialized * 1 initialized tior_5 initialized ? ? ? ? initialized * 1 initialized tier_5 initialized ? ? ? ? initialized * 1 initialized tsr_5 initialized ? ? ? ? initialized * 1 initialized tcnt_5 initialized ? ? ? ? initialized * 1 initialized tgra_5 initialized ? ? ? ? initialized * 1 initialized tgrb_5 initialized ? ? ? ? initialized * 1 initialized tpu_5 dtcera initialized ? ? ? ? initialized * 1 initialized dtcerb initialized ? ? ? ? initialized * 1 initialized dtcerc initialized ? ? ? ? initialized * 1 initialized dtcerd initialized ? ? ? ? initialized * 1 initialized dtcere initialized ? ? ? ? initialized * 1 initialized dtcerf initialized ? ? ? ? initialized * 1 initialized intc section 28 list of registers rev. 2.00 oct. 20, 2009 page 1265 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module dtccr initialized ? ? ? ? initialized * 1 initialized intcr initialized ? ? ? ? initialized * 1 initialized cpupcr initialized ? ? ? ? initialized * 1 initialized ier initialized ? ? ? ? initialized * 1 initialized isr initialized ? ? ? ? initialized * 1 initialized intc port1 ? ? ? ? ? ? ? port2 ? ? ? ? ? ? ? port5 ? ? ? ? ? ? ? port6 ? ? ? ? ? ? ? porta ? ? ? ? ? ? ? portb ? ? ? ? ? ? ? portd ? ? ? ? ? ? ? porte ? ? ? ? ? ? ? portf ? ? ? ? ? ? ? p1dr initialized ? ? ? ? initialized * 1 initialized p2dr initialized ? ? ? ? initialized * 1 initialized p6dr initialized ? ? ? ? initialized * 1 initialized padr initialized ? ? ? ? initialized * 1 initialized pbdr initialized ? ? ? ? initialized * 1 initialized pddr initialized ? ? ? ? initialized * 1 initialized pedr initialized ? ? ? ? initialized * 1 initialized pfdr initialized ? ? ? ? initialized * 1 initialized i/o port smr_2 initialized ? ? ? ? initialized * 1 initialized brr_2 initialized ? ? ? ? initialized * 1 initialized scr_2 initialized ? ? ? ? initialized * 1 initialized tdr_2 initialized initialized ? initialized initialized initialized * 1 initialized ssr_2 initialized initialized ? initialized initialized initialized * 1 initialized rdr_2 initialized initialized ? initialized initialized initialized * 1 initialized scmr_2 initialized ? ? ? ? initialized * 1 initialized sci_2 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1266 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module dadr0h initialized ? ? ? ? initialized * 1 initialized dadr1h initialized ? ? ? ? initialized * 1 initialized dacr01 initialized ? ? ? ? initialized * 1 initialized dadr01t initialized ? ? ? ? initialized * 1 initialized d/a pcr initialized ? ? ? ? initialized * 1 initialized pmr initialized ? ? ? ? initialized * 1 initialized nderh initialized ? ? ? ? initialized * 1 initialized nderl initialized ? ? ? ? initialized * 1 initialized podrh initialized ? ? ? ? initialized * 1 initialized podrl initialized ? ? ? ? initialized * 1 initialized ndrh initialized ? ? ? ? initialized * 1 initialized ndrl initialized ? ? ? ? initialized * 1 initialized ppg smr_0 initialized ? ? ? ? initialized * 1 initialized brr_0 initialized ? ? ? ? initialized * 1 initialized scr_0 initialized ? ? ? ? initialized * 1 initialized tdr_0 initialized initialized ? initialized initialized initialized * 1 initialized ssr_0 initialized initialized ? initialized initialized initialized * 1 initialized rdr_0 initialized initialized ? initialized initialized initialized * 1 initialized scmr_0 initialized ? ? ? ? initialized * 1 initialized sci_0 smr_1 initialized ? ? ? ? initialized * 1 initialized brr_1 initialized ? ? ? ? initialized * 1 initialized scr_1 initialized ? ? ? ? initialized * 1 initialized tdr_1 initialized initialized ? initialized initialized initialized * 1 initialized ssr_1 initialized initialized ? initialized initialized initialized * 1 initialized rdr_1 initialized initialized ? initialized initialized initialized * 1 initialized scmr_1 initialized ? ? ? ? initialized * 1 initialized sci_1 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1267 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module addra_0 initialized ? ? ? ? initialized * 1 initialized addrb_0 initialized ? ? ? ? initialized * 1 initialized addrc_0 initialized ? ? ? ? initialized * 1 initialized addrd_0 initialized ? ? ? ? initialized * 1 initialized addre_0 initialized ? ? ? ? initialized * 1 initialized addrf_0 initialized ? ? ? ? initialized * 1 initialized addrg_0 initialized ? ? ? ? initialized * 1 initialized addrh_0 initialized ? ? ? ? initialized * 1 initialized adcsr_0 initialized ? ? ? ? initialized * 1 initialized adcr_0 initialized ? ? ? ? initialized * 1 initialized a/d_0 tcsr initialized ? ? ? ? initialized * 1 initialized tcnt initialized ? ? ? ? initialized * 1 initialized rstcsr initialized ? ? ? ? initialized * 1 initialized wdt tcr_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcr_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tcsr_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcsr_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tcora_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcora_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tcorb_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcorb_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tcnt_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcnt_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tccr_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tccr_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tstr initialized ? ? ? ? initialized * 1 initialized tsyr initialized ? ? ? ? initialized * 1 initialized tpu section 28 list of registers rev. 2.00 oct. 20, 2009 page 1268 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module tcr_0 initialized ? ? ? ? initialized * 1 initialized tmdr_0 initialized ? ? ? ? initialized * 1 initialized tiorh_0 initialized ? ? ? ? initialized * 1 initialized tiorl_0 initialized ? ? ? ? initialized * 1 initialized tier_0 initialized ? ? ? ? initialized * 1 initialized tsr_0 initialized ? ? ? ? initialized * 1 initialized tcnt_0 initialized ? ? ? ? initialized * 1 initialized tgra_0 initialized ? ? ? ? initialized * 1 initialized tgrb_0 initialized ? ? ? ? initialized * 1 initialized tgrc_0 initialized ? ? ? ? initialized * 1 initialized tgrd_0 initialized ? ? ? ? initialized * 1 initialized tpu_0 tcr_1 initialized ? ? ? ? initialized * 1 initialized tmdr_1 initialized ? ? ? ? initialized * 1 initialized tior_1 initialized ? ? ? ? initialized * 1 initialized tier_1 initialized ? ? ? ? initialized * 1 initialized tsr_1 initialized ? ? ? ? initialized * 1 initialized tcnt_1 initialized ? ? ? ? initialized * 1 initialized tgra_1 initialized ? ? ? ? initialized * 1 initialized tgrb_1 initialized ? ? ? ? initialized * 1 initialized tpu_1 tcr_2 initialized ? ? ? ? initialized * 1 initialized tmdr_2 initialized ? ? ? ? initialized * 1 initialized tior_2 initialized ? ? ? ? initialized * 1 initialized tier_2 initialized ? ? ? ? initialized * 1 initialized tsr_2 initialized ? ? ? ? initialized * 1 initialized tcnt_2 initialized ? ? ? ? initialized * 1 initialized tgra_2 initialized ? ? ? ? initialized * 1 initialized tgrb_2 initialized ? ? ? ? initialized * 1 initialized tpu_2 section 28 list of registers rev. 2.00 oct. 20, 2009 page 1269 of 1340 rej09b0499-0200 register abbreviation reset module stop state sleep all- module- clock-stop software standby deep software standby hardware standby module tcr_3 initialized ? ? ? ? initialized * 1 initialized tmdr_3 initialized ? ? ? ? initialized * 1 initialized tiorh_3 initialized ? ? ? ? initialized * 1 initialized tiorl_3 initialized ? ? ? ? initialized * 1 initialized tier_3 initialized ? ? ? ? initialized * 1 initialized tsr_3 initialized ? ? ? ? initialized * 1 initialized tcnt_3 initialized ? ? ? ? initialized * 1 initialized tgra_3 initialized ? ? ? ? initialized * 1 initialized tgrb_3 initialized ? ? ? ? initialized * 1 initialized tgrc_3 initialized ? ? ? ? initialized * 1 initialized tgrd_3 initialized ? ? ? ? initialized * 1 initialized tpu_3 notes: 1. not initialized in deep software standby mode but initialized when deep software standby mode is released by the internal reset. 2. these registers are initialized when a ll the ramcut2 to ramcut0 bits in dpsbycr are set to 1, and not initialized when these bits are set to 0. 3. supported only by the h8sx/1655m group. 4. lvdcr is initialized by a pin reset or pow er-on reset not by a voltage-monitoring reset, deep software standby reset, or watchdog timer reset. section 28 list of registers rev. 2.00 oct. 20, 2009 page 1270 of 1340 rej09b0499-0200 section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1271 of 1340 rej09b0499-0200 section 29 electrical characteristics 29.1 absolute maximum ratings table 29.1 absolute maximum ratings item symbol value unit power supply voltage v cc pllv cc drv cc ?0.3 to +4.6 v input voltage (except for port 5) v in ?0.3 to v cc +0.3 v input voltage (port 5) v in ?0.3 to av cc +0.3 v reference power supply voltage v ref ?0.3 to av cc +0.3 v analog power supply voltage av cc ?0.3 to +4.6 v analog input voltage v an ?0.3 to av cc +0.3 v regular specifications: ?20 to +75 * operating temperature t opr wide-range specifications: ?40 to +85 * c storage temperature t stg ?55 to +125 c caution: permanent damage to the lsi may resu lt if absolute maximum ratings are exceeded. note: * the operating temperature range during prog ramming/erasing of the flash memory is 0 c to +75 c for regular specifications and 0 c to +85 c for wide-range specifications. section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1272 of 1340 rej09b0499-0200 29.2 dc characteristics (h8sx/1655 group) table 29.2 dc characteristics conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v* 1 , t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit test conditions vt ? v cc 0.2 ? ? v vt + ? ? v cc 0.7 v irq input pin, tpu input pin, tmr input pin, port 2 port j, port k vt + ? vt ? v cc 0.06 ? ? v vt ? av cc 0.2 ? ? v vt + ? ? av cc 0.7 v schmitt trigger input voltage irq0-b to irq7-b input pin vt + ? vt ? av cc 0.06 ? ? v md, res , stby , emle, nmi v cc 0.9 ? v cc + 0.3 extal other input pins v cc 0.7 ? v cc + 0.3 input high voltage (except schmitt trigger input pin) port 5 v ih av cc 0.7 ? av cc + 0.3 v md, res , stby , emle ?0.3 ? v cc 0.1 extal, nmi ?0.3 ? v cc 0.2 input low voltage (except schmitt trigger input pin) other input pins v il ?0.3 ? v cc 0.2 v v cc ? 0.5 ? ? v i oh = ?200 a output high voltage all output pins v oh v cc ? 1.0 ? ? i oh = ?1 ma output low voltage all output pins v ol ? ? 0.4 v i ol = 1.6 ma res ? ? 10.0 a md, stby , emle, nmi ? ? 1.0 v in = 0.5 to v cc ? 0.5 v input leakage current port 5 |i in | ? ? 1.0 v in = 0.5 to av cc ? 0.5 v section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1273 of 1340 rej09b0499-0200 item symbol min. typ. max. unit test conditions three-state leakage current (off state) ports 1, 2, 6, a, b, d to f, h to k, m | i tsi | ? ? 1.0 a v in = 0.5 to v cc ? 0.5 v input pull-up mos current ports d to f, h, i ?i p 10 ? 300 a v cc = 3.0 to 3.6 v v in = 0 v input capacitance all input pins c in ? ? 15 pf v in = 0 v f = 1 mhz t a = 25 c normal operation i cc * 3 ? 50 85 ma f = 50 mhz sleep mode ? 48 60 ? 0.15 1.1 ma t a 50 c software standby mode ? ? 3.5 50c < t a ? 20 60 a t a 50 c ram, usb retained ? ? 200 50c < t a ? 3 8 t a 50 c supply current * 2 deep software standby mode ram, usb power supply stopped ? ? 26 50c < t a ? 2 7 a t a 50 c standby mode hardware standby mode ? ? 25 50c < t a all-module-clock-stop mode * 4 ? 23 30 ma during a/d and d/a conversion ai cc ? 2.0 3.5 ma analog power supply current standby for a/d and d/a conversion ? 0.5 1.5 a during a/d and d/a conversion ai cc ? 0.8 1.5 ma reference power supply current standby for a/d and d/a conversion ? 0.5 1.5 a ram standby voltage v ram 2.5 ? ? v section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1274 of 1340 rej09b0499-0200 item symbol min. typ. max. unit test conditions vcc start voltage * 5 v ccstart ? ? 0.8 v vcc rising gradient * 5 sv cc ? ? 20 ms/v notes: 1. when the a/d and d/a c onverters are not used, the av cc , v ref , and av ss pins should not be open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. supply current values are for v ih = v cc and v il = 0 v with all output pins unloaded and all built-in pull-up moss in the off state. 3. i cc depends on f as follows: i cc max = 30 (ma) + 1.1 (ma/mhz) f (normal operation) i cc max = 35 (ma) + 0.5 (ma/mhz) f (sleep mode) 4. the values are for reference. 5. this applies when the res pin is held low at power-on. table 29.3 permissible output currents conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v*, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit permissible output low current (per pin) output pins i ol ? ? 2.0 ma permissible output low current (total) total of output pins i ol ? ? 80 ma permissible output high current (per pin) all output pins ?i oh ? ? 2.0 ma permissible output high current (total) total of all output pins ?i oh ? ? 40 ma caution: to protect the lsi's re liability, do not exceed the output current values in table 29.3. note: * when the a/d and d/a conver ters are not used, the av cc , v ref , and av ss pins should not be open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1275 of 1340 rej09b0499-0200 29.3 dc characteristics (h8sx/1655m group) table 29.4 dc characteristics conditions: v cc = pllv cc = drv cc = 2.95 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v* 1 , t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit test conditions vt ? v cc 0.2 ? ? v vt + ? ? v cc 0.7 v irq input pin, tpu input pin, tmr input pin, port 2 port j, port k vt + ? vt ? v cc 0.06 ? ? v vt ? av cc 0.2 ? ? v vt + ? ? av cc 0.7 v schmitt trigger input voltage irq0-b to irq7-b input pin vt + ? vt ? av cc 0.06 ? ? v md, res , stby , emle, nmi v cc 0.9 ? v cc + 0.3 extal other input pins v cc 0.7 ? v cc + 0.3 input high voltage (except schmitt trigger input pin) port 5 v ih av cc 0.7 ? av cc + 0.3 v md, res , stby , emle ?0.3 ? v cc 0.1 extal, nmi ?0.3 ? v cc 0.2 input low voltage (except schmitt trigger input pin) other input pins v il ?0.3 ? v cc 0.2 v v cc ? 0.5 ? ? v i oh = ?200 a output high voltage all output pins v oh v cc ? 1.0 ? ? i oh = ?1 ma output low voltage all output pins v ol ? ? 0.4 v i ol = 1.6 ma res ? ? 10.0 a md, stby , emle, nmi ? ? 1.0 v in = 0.5 to v cc ? 0.5 v input leakage current port 5 |i in | ? ? 1.0 v in = 0.5 to av cc ? 0.5 v section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1276 of 1340 rej09b0499-0200 item symbol min. typ. max. unit test conditions three-state leakage current (off state) ports 1, 2, 3, 6, a to f, h to k, m | i tsi | ? ? 1.0 a v in = 0.5 to v cc ? 0.5 v input pull-up mos current ports d to f, h, i ?i p 10 ? 300 a v cc = 3.0 to 3.6 v v in = 0 v input capacitance all input pins c in ? ? 15 pf v in = 0 v f = 1 mhz t a = 25 c normal operation i cc * 3 ? 50 85 ma f = 50 mhz sleep mode ? 48 60 ? 0.15 1.1 ma t a 50 c software standby mode ? ? 3.5 50c < t a ? 24 67 a t a 50 c ram, usb retained ? ? 200 50c < t a ? 23 35 t a 50 c supply current * 2 deep software standby mode ram, usb power supply stopped ? ? 60 50c < t a ? 2 7 a t a 50 c standby mode hardware standby mode ? ? 25 50c < t a all-module-clock-stop mode * 4 ? 23 30 ma during a/d and d/a conversion ai cc ? 2.0 3.5 ma analog power supply current standby for a/d and d/a conversion ? 0.5 1.5 a during a/d and d/a conversion ai cc ? 0.8 1.5 ma reference power supply current standby for a/d and d/a conversion ? 0.5 1.5 a ram standby voltage v ram 2.5 ? ? v section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1277 of 1340 rej09b0499-0200 item symbol min. typ. max. unit test conditions vcc start voltage * 5 v ccstart ? ? 0.8 v vcc rising gradient * 5 sv cc ? ? 20 ms/v notes: 1. when the a/d and d/a c onverters are not used, the av cc , v ref , and av ss pins should not be open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. supply current values are for v ih = v cc and v il = 0 v with all output pins unloaded and all built-in pull-up moss in the off state. 3. i cc depends on f as follows: i cc max = 30 (ma) + 1.1 (ma/mhz) f (normal operation) i cc max = 35 (ma) + 0.5 (ma/mhz) f (sleep mode) 4. the values are for reference. 5. this applies when the res pin is held low at power-on. table 29.5 permissible output currents conditions: v cc = pllv cc = drv cc = 2.95 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v*, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit permissible output low current (per pin) output pins i ol ? ? 2.0 ma permissible output low current (total) total of output pins i ol ? ? 80 ma permissible output high current (per pin) all output pins ?i oh ? ? 2.0 ma permissible output high current (total) total of all output pins ?i oh ? ? 40 ma caution: to protect the lsi's re liability, do not exceed the output current values in table 29.5. note: * when the a/d and d/a conver ters are not used, the av cc , v ref , and av ss pins should not be open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1278 of 1340 rej09b0499-0200 29.4 ac characteristics lsi output pin c rh rl 3 v c = 30 pf rl = 2.4 k rh = 12 k input/output timing measurement level: 1.5 v (v cc = 3.0 v to 3.6 v * ) note: * vcc=2.95 to 3.60v in the h8sx/1655m group. figure 29.1 output load circuit section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1279 of 1340 rej09b0499-0200 29.4.1 clock timing table 29.6 clock timing conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, i = 8 mhz to 50 mhz, b = 8 mhz to 50 mhz, p = 8 mhz to 35 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit. test conditions clock cycle time t cyc 20 125 ns figure 29.2 clock high pulse width t ch 5 ? ns clock low pulse width t cl 5 ? ns clock rising time t cr ? 5 ns clock falling time t cf ? 5 ns oscillation settling time after reset (crystal) t osc1 10 ? ms figure 29.4 oscillation settling time after leaving software standby mode (crystal) t osc2 10 ? ms figure 29.3 external clock output delay settling time t dext 1 ? ms figure 29.4 external clock input low pulse width t exl 27.7 ? ns figure 29.5 external clock input high pulse width t exh 27.7 ? ns external clock rising time t exr ? 5 ns external clock falling time t exf ? 5 ns note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. t cyc b t ch t cf t cl t cr figure 29.2 external bus clock timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1280 of 1340 rej09b0499-0200 oscillator software standby mode (power-down mode) oscillation settling time t osc2 i nmi nmi exception handling nmieg = 1 ssby = 1 nmi exception handling sleep instruction nmieg ssby figure 29.3 oscillation settling ti ming after software standby mode extal v cc stby res i t dext t osc1 t dext t osc1 figure 29.4 oscillation settling timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1281 of 1340 rej09b0499-0200 extal vcc 0.5 t exr t exh t exl t exf figure 29.5 external input clock timing 29.4.2 control signal timing table 29.7 control signal timing conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, i = 8 mhz to 50 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 29.6 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 29.7 nmi hold time t nmih 10 ? ns nmi pulse width (after leaving software standby mode) t nmiw 200 ? ns irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? ns irq pulse width (after leaving software standby mode) t irqw 200 ? ns note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. i res t ress t ress t resw figure 29.6 reset input timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1282 of 1340 rej09b0499-0200 i nmi irqi * (i = 0 to 11) irq (edge input) note: * ssier must be set to cancel software standby mode. irq (level input) t nmis t nmih t irqs t irqs t irqh t nmiw t irqw figure 29.7 int errupt input timing 29.4.3 bus timing table 29.8 bus timing (1) conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, b = 8 mhz to 50 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit test conditions address delay time t ad ? 15 ns address setup time 1 t as1 0.5 t cyc ? 8 ? ns figures 29.8 to 29.20 address setup time 2 t as2 1.0 t cyc ? 8 ? ns address setup time 3 t as3 1.5 t cyc ? 8 ? ns address setup time 4 t as4 2.0 t cyc ? 8 ? ns address hold time 1 t ah1 0.5 t cyc ? 8 ? ns address hold time 2 t ah2 1.0 t cyc ? 8 ? ns address hold time 3 t ah3 1.5 t cyc ? 8 ? ns section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1283 of 1340 rej09b0499-0200 item symbol min. max. unit test conditions cs delay time 1 t csd1 ? 15 ns as delay time t asd ? 15 ns rd delay time 1 t rsd1 ? 15 ns rd delay time 2 t rsd2 ? 15 ns read data setup time 1 t rds1 15 ? ns read data setup time 2 t rds2 15 ? ns figures 29.8 to 29.20 read data hold time 1 t rdh1 0 ? ns read data hold time 2 t rdh2 0 ? ns read data access time 2 t ac2 ? 1.5 t cyc ? 20 ns read data access time 4 t ac4 ? 2.5 t cyc ? 20 ns read data access time 5 t ac5 ? 1.0 t cyc ? 20 ns read data access time 6 t ac6 ? 2.0 t cyc ? 20 ns read data access time (from address) 1 t aa1 ? 1.0 t cyc ? 20 ns read data access time (from address) 2 t aa2 ? 1.5 t cyc ? 20 ns read data access time (from address) 3 t aa3 ? 2.0 t cyc ? 20 ns read data access time (from address) 4 t aa4 2.5 t cyc ? 20 ns read data access time (from address) 5 t aa5 ? 3.0 t cyc ? 20 ns note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1284 of 1340 rej09b0499-0200 table 29.8 bus timing (2) conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, b = 8 mhz to 50 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit test conditions wr delay time 1 t wrd1 ? 15 ns wr delay time 2 t wrd2 ? 15 ns wr pulse width 1 t wsw1 1.0 t cyc ? 13 ? ns wr pulse width 2 t wsw2 1.5 t cyc ? 13 ? ns write data delay time t wdd ? 20 ns write data setup time 1 t wds1 0.5 t cyc ? 13 ? ns write data setup time 2 t wds2 1.0 t cyc ? 13 ? ns write data setup time 3 t wds3 1.5 t cyc ? 13 ? ns write data hold time 1 t wdh1 0.5 t cyc ? 8 ? ns write data hold time 3 t wdh3 1.5 t cyc ? 8 ? ns figures 29.8 to 29.20 byte control delay time t ubd ? 15 ns figures 29.13, 29.14 byte control pulse width 1 t ubw1 ? 1.0 t cyc ? 15 ns figure 29.13 byte control pulse width 2 t ubw2 ? 2.0 t cyc ? 15 ns figure 29.14 multiplexed address delay time 1 t mad1 ? 15 ns multiplexed address hold time t mah 1.0 t cyc ? 15 ? ns multiplexed address setup time 1 t mas1 0.5 t cyc ? 15 ? ns multiplexed address setup time 2 t mas2 1.5 t cyc ? 15 ? ns address hold delay time t ahd ? 15 ns address hold pulse width 1 t ahw1 1.0 t cyc ? 15 ? ns address hold pulse width 2 t ahw2 2.0 t cyc ? 15 ? ns figures 29.17, 29.18 wait setup time t wts 15 ? ns wait hold time t wth 5.0 ? ns figures 29.10, 29.18 breq setup time t breqs 20 ? ns back delay time t bacd ? 15 ns bus floating time t bzd ? 30 ns figure 29.19 breqo delay time t brqod ? 15 ns figure 29.20 section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1285 of 1340 rej09b0499-0200 item symbol min. max. unit test conditions bs delay time t bsd 1.0 15 ns rd/ wr delay time t rwd ? 15 ns figures 29.8, 29.9, 29.11 to 29.14 note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1286 of 1340 rej09b0499-0200 t1 t2 t ad t csd1 t rwd t rwd t as1 t bsd t bsd t as1 t as1 t as1 t rsd1 t rsd1 t ac5 t aa2 t rsd1 t wrd2 t wsw1 t wdh1 t wdd t dacd1 t dacd2 t wrd2 t ah1 t ac2 t rds2 t rdh2 t aa3 t rsd2 t rds1 t rdh1 t ah1 t asd t asd t rwd t rwd t dacd2 t dacd2 t rwd t rwd b a20 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 read (rdnn = 1) read (rdnn = 0) write bs rd/ wr rd/ wr rd/ wr d15 to d0 (write) (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 lhwr , llwr figure 29.8 basic bus timing: two-state access section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1287 of 1340 rej09b0499-0200 t1 t2 t3 t ad t as1 t ah1 t rsd1 t rds1 t rdh1 t rsd2 t rds2 t rdh2 t asd t asd t rsd1 t rsd1 t ac6 t ac4 t aa5 t as2 t wdd t wsw2 t wdh1 t wds1 t dacd1 t dacd2 t dacd2 t dacd2 t wrd1 t wrd2 t ah1 t aa4 t as1 t as1 t csd1 t rwd t rwd t bsd t bsd t rwd t rwd t rwd t rwd b a20 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 read (rdnn = 1) read (rdnn = 0) write bs rd/ wr rd/ wr rd/ wr d15 to d0 (write) (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 lhwr , llwr figure 29.9 basic bus timing: three-state access section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1288 of 1340 rej09b0499-0200 t1 b a20 to a0 cs7 to cs0 as bs rd/ wr rd d15 to d0 rd d15 to d0 lhwr , llwr d15 to d0 wait t wts t wth t wts t wth t2 tw t3 read (rdnn = 1) read (rdnn = 0) write rd/ wr rd/ wr figure 29.10 basic bus timing : three-state access, one wait section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1289 of 1340 rej09b0499-0200 th t ad t csd1 t as1 t asd t as3 t rsd1 t ac5 t rds1 t rdh1 t ah2 t ah3 t wdh3 t wsw1 t wds2 t wdd t as3 t wrd2 t wrd2 t rsd2 t rsd1 t ac2 t rds2 t rdh2 t as3 t rsd1 t ah3 t ah1 t asd t1 t2 tt t rwd t rwd t rwd t bsd t bsd t rwd t rwd t rwd t dacd1 t dacd2 t dacd2 t dacd2 b a20 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 read (rdnn = 1) read (rdnn = 0) write bs rd/ wr rd/ wr rd/ wr d15 to d0 (write) (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 lhwr , llwr figure 29.11 basic bus timing: two-state access ( cs assertion period extended) section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1290 of 1340 rej09b0499-0200 th t ad t csd1 t as1 t asd t as3 t rsd1 t rsd1 t asd t ah1 t ah3 t ah2 t ah3 t wdh3 t wsw2 t wds3 t as4 t as3 t rsd1 t wdd t wrd2 t wrd1 t ac4 t rds2 t rdh2 t rsd2 t ac6 t rds1 t rdh1 t1 t2 t3 tt t rwd t rwd t rwd t rwd t rwd t bsd t bsd t rwd t dacd2 t dacd1 t dacd2 t dacd2 b a20 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 read (rdnn = 1) read (rdnn = 0) write bs rd/ wr rd/ wr rd/ wr d15 to d0 (write) (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 lhwr , llwr figure 29.12 basic bus timing: three-state access ( cs assertion period extended) section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1291 of 1340 rej09b0499-0200 t1 as bs rd/ wr t ad t csd1 t as1 t ah1 t ah1 t asd t asd t2 t bsd t ac5 t ac5 t aa2 t rwd t rwd t bsd rd rd/ wr rd t rsd1 t rsd1 t rds1 t rdh1 t ubw1 t ubd t rwd t wdd t wdh1 t rwd t ubd t as1 t as1 b a20 to a0 cs7 to cs0 read d15 to d0 lub , llb d15 to d0 (write) write high figure 29.13 byte control sram: two-stat e read/write access section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1292 of 1340 rej09b0499-0200 t1 t ad t csd1 t as1 t ah1 t asd t rwd t rwd t asd as bs rd/ wr rd rd/ wr rd t2 t3 t as1 t ah1 t as1 t rsd1 t ubd t rwd t wdd t wdh1 t rwd t ubd t rsd1 t rds1 t ac6 t ac6 t ubw2 t aa4 t rdh1 t bsd t bsd b a20 to a0 cs7 to cs0 lub , llb d15 to d0 d15 to d0 (write) read write high figure 29.14 byte control sram: three-state read/write access section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1293 of 1340 rej09b0499-0200 t1 b a20 to a6, a0 a5 to a1 cs7 to cs0 as bs rd/ wr rd d15 to d0 high lhwr , llwr t2 t1 t ad t rsd2 t aa1 t rds2 t rdh2 t1 read figure 29.15 burst rom access timing: one-state burst access section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1294 of 1340 rej09b0499-0200 t1 b a20 to a6, a0 a5 to a1 cs7 to cs0 as rd d15 to d0 lhwr , llwr t2 t3 t1 t ad t as1 t asd t aa3 t rsd2 t rds2 t rdh2 t asd t ah1 t2 read bs rd/ wr high figure 29.16 burst rom access timing: two-state burst access section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1295 of 1340 rej09b0499-0200 tma1 t ad t ahd t ahw1 t wsw1 t ahd t mad1 t mah t rds2 t rdh2 b a20 to a0 cs7 to cs0 ah ( as ) tma2 t1 t2 rd/ wr bs rd ad15 to ad0 rd/ wr lhwr , llwr t mad1 t wdd t wdh1 ad15 to ad0 read write t mas1 t mah t mas1 dkc = 0 dkc = 1 dack3 to dack0 figure 29.17 address/data multiplexed access timing (no wait) (basic, four-state access) section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1296 of 1340 rej09b0499-0200 tma1 tmaw tma2 t1 t2 tpw ttw t3 rd/ wr wait t ad t ahd t ahd t ahw2 t mas2 t mah rd rd/ wr t mad1 t rds2 t rdh2 t wdd t wds1 t wts t wth t wts t wth t wdh1 t mas2 t mah t mad1 a20 to a0 cs7 to cs0 ah ( as ) ad15 to ad0 read write ad15 to ad0 lhwr , llwr b figure 29.18 address/data multiple xed access timing (wait control) (address cycle program wait 1 + data cycle program wait 1 + data cycle pin wait 1) section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1297 of 1340 rej09b0499-0200 b breq t breqs t breqs t bacd t bzd t bacd t bzd back a20 to a0 cs7 to cs0 d15 to d0 as , rd, lhwr , llwr figure 29.19 external bus release timing b back t brqod t brqod breqo figure 29.20 external bu s request output timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1298 of 1340 rej09b0499-0200 29.4.4 dmac/exdmac timing table 29.9 dmac/exdmac timing conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, b = 8 mhz to 50 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. max. unit test conditions dreq setup time t drqs 20 ? ns figure 29.21 dreq hold time t drqh 5 ? ns tend delay time t ted ? 15 ns figure 29.22 dack delay time 1 t dacd1 ? 15 ns figure 29.23 dack delay time 2 t dacd2 ? 15 ns figure 29.24 edreq setup time t edrqs 20 ? ns figure 29.21 edreq hold time t edrqh 5 ? ns etend delay time t eted ? 15 ns figure 29.22 edack delay time 1 t edacd1 ? 15 ns edack delay time 2 t edacd2 ? 15 ns figure 29.23 figure 29.24 edrak delay time t edrkd ? 15 ns figure 29.25 note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. b dreq0 to dreq3 edreq0 to edreq1 t drqs t drqh t edrqs t edrqh figure 29.21 dmac/exdmac ( dreq and edreq ) input timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1299 of 1340 rej09b0499-0200 etend0 to etend1 t1 t ted t ted b tend0 to tend3 t2 or t3 t eted t eted figure 29.22 dmac/exdmac ( tend and etend ) output timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1300 of 1340 rej09b0499-0200 t1 b a20 to a0 cs7 to cs0 as bs rd/ wr rd (read) d15 to d0 (read) lhwr , llwr (write) d15 to d0 (write) t2 (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 t dacd1 t dacd2 t dacd2 t dacd2 t edacd2 t edacd2 (edkc = 0) edack0 to edack1 (edkc = 1) edack0 to edack1 t edacd1 t edacd2 figure 29.23 dmac/exdmac single-addr ess transfer timing: two-state access section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1301 of 1340 rej09b0499-0200 t1 t dacd1 t dacd2 b a 20 to a0 cs7 to cs0 as rd (read) d15 to d0 (read) lhwr , llwr (write) d15 to d0 (write) t2 t3 t dacd2 t dacd2 (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 bs rd/ wr t edacd2 t edacd2 t edacd1 t edacd2 (edkc = 0) edack0 to edack1 (edkc = 1) edack0 to edack1 figure 29.24 dmac/exdmac single-address transfer timing: three-state access section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1302 of 1340 rej09b0499-0200 edrak0 to edrak1 t edrkd t edrkd b figure 29.25 exdmac ( edrak ) output timing 29.4.5 timing of on-chip peripheral modules table 29.10 timing of on -chip peripheral modules conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v* 1 , av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, p = 8 mhz to 35 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit test conditions i/o ports output data delay time t pwd ? 40 ns figure 29.26 input data setup time t prs 25 ? ns input data hold time t prh 25 ? ns tpu timer output delay time t tocd ? 40 ns figure 29.27 timer input setup time t tics 25 ? ns timer clock input setup time t tcks 25 ? ns figure 29.28 single-edge setting t tckwh 1.5 ? t cyc timer clock pulse width both-edge setting t tckwl 2.5 ? t cyc ppg pulse output delay time t pod ? 40 ns figure 29.29 timer output delay time t tmod ? 40 ns figure 29.30 8-bit timer timer reset input setup time t tmrs 25 ? ns figure 29.31 timer clock input setup time t tmcs 25 ? ns figure 29.32 timer clock pulse width single-edge setting t tmcwh 1.5 ? t cyc both-edge setting t tmcwl 2.5 ? t cyc section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1303 of 1340 rej09b0499-0200 item symbol min. max. unit test conditions wdt overflow output delay time t wovd ? 40 ns figure 29.33 sci asynchronous t scyc 4 ? t cyc figure 29.34 input clock cycle clocked synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 t cyc input clock fall time t sckf ? 1.5 t cyc sci transmit data delay time t txd ? 40 ns figure 29.35 receive data setup time (clocked synchronous) t rxs 40 ? ns receive data hold time (clocked synchronous) t rxh 40 ? ns a/d converter trigger input setup time t trgs 30 ? ns figure 29.36 iic2 scl input cycle time t scl 12 t cyc + 600 ? ns figure 29.37 scl input high pulse width t sclh 3 t cyc + 300 ? ns scl input low pulse width t scll 5 t cyc + 300 ? ns scl, sda input falling time t sf ? 300 ns scl, sda input spike pulse removal time t sp ? 1 t cyc ns sda input bus free time t buf 5 t cyc ? ns start condition input hold time t stah 3 t cyc ? ns repeated start condition input setup time t stas 3 t cyc ? ns stop condition input setup time t stos 1 t cyc + 20 ? ns data input setup time t sdas 0 ? ns data input hold time t sdah 0 ? ns scl, sda capacitive load cb ? 400 pf scl, sda falling time t sf ? 300 ns section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1304 of 1340 rej09b0499-0200 item symbol min. max. unit test conditions tck clock cycle time t tckcyc 50 * 2 ? ns figure 29.38 tck clock high pulse width t tckh 20 ? ns tck clock low pulse width t tckl 20 ? ns tck clock rising time t tckr ? 5 ns tck clock falling time t tckf ? 5 ns trst pulse width t trstw 20 ? tcyc figure 29.39 tms setup time t tmss 20 ? ns figure 29.40 tms hold time t tmsh 20 ? ns tdi setup time t tdis 20 ? ns tdi hold time t tdih 20 ? ns boundary scan tdo data delay time t tdod ? 23 ns notes: 1. v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group 2. t tckcyc t tckcyc must be satisfied. t1 t prs t prh t pwd t2 p ports 1, 2, 5, 6, a, b, d to f, h, i, m (read) ports 1, 2, 6, a, b, d to f, h, i, m (write) figure 29.26 i/o port input/output timing p output compare output * input capture input * t tocd t tics note: * tioca3 to tioca5, tiocb3 to tiocb5, tiocc3, tiocd3 figure 29.27 tpu input/output timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1305 of 1340 rej09b0499-0200 p tclka to tclkd t tckwl t tckwh t tcks t tcks figure 29.28 tpu clock input timing p po7 to po0 t pod figure 29.29 ppg output timing p tmo0 to tmo3 t tmod figure 29.30 8-bit timer output timing p tmri0 to tmri3 t tmrs figure 29.31 8-bit timer reset input timing p tmci0 to tmci3 t tmcwl t tmcwh t tmcs t tmcs figure 29.32 8-bit timer clock input timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1306 of 1340 rej09b0499-0200 p wdtovf t wovd t wovd figure 29.33 wdt output timing sck0 to sck2, sck4 t sckw t sckr t sckf t scyc figure 29.34 sck clock input timing sck0 to sck2, sck4 t txd t rxs t rxh txd0 to txd2, txd4 (transmit data) rxd0 to rxd2, rxd4 (receive data) figure 29.35 sci input/output timing: clocked synchronous mode p adtrg0 , adtrg1 t trgs figure 29.36 a/d converter external trigger input timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1307 of 1340 rej09b0499-0200 t buf t stah t stas t sp t stos t sclh t scll t sf t sr t scl t sdah t sdas p * p * s * s r * v ih v il sda0 to sda1 scl0 to scl1 note: s, p, and sr represent the following conditions: s: start condition p: stop condition sr: repeated start condition figure 29.37 i 2 c bus interface2 input/output timing (option) t tckl t tckh tck t tckf t tckcyc t tckr figure 29.38 boundary scan tck timing t trstw tck res t rst figure 29.39 boundary scan trst timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1308 of 1340 rej09b0499-0200 t tmss t tmsh tck tms tdi tdo t tdis t tdih t tdod figure 29.40 boundary scan input/output timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1309 of 1340 rej09b0499-0200 29.5 usb characteristics table 29.11 usb characteristics when on-chip usb transceiver is used (usd + , usd ? pin characteristics) conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, v ss = pllv ss = drv ss = av ss = 0 v, cku = 48 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit test conditions input input high voltage v ih 2.0 ? v input low voltage v il ? 0.8 v figures 29.41, 29.42 differential input sensitivity v di 0.2 ? v ? (d + ) ? (d ? ) ? differential common mode range v cm 0.8 2.5 v output output high voltage v oh 2.8 ? v i oh = ? 200 a output low voltage v ol ? 0.3 v i ol = 2 ma crossover voltage v crs 1.3 2.0 v rising time t r 4 20 ns falling time t f 4 20 ns ratio of rising time to falling time t rfm 90 111.11 % (t r /t f ) output resistance z drv 28 44 including r s = 22 note: * vcc = pllvcc = drvcc = 2.95v to 3.60v in the h8sx/1655m group. usd+, usd- differential data lines rise time fall time 10% 10% 90% 90% t r v crs t f figure 29.41 data signal timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1310 of 1340 rej09b0499-0200 usd+ r s = 22 usd- test point test point r s = 22 c l = 50 pf c l = 50 pf figure 29.42 load condition 29.6 a/d conversion characteristics table 29.12 a/d conversion characteristics in peripheral clock mode (icksel = 0) conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, vref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, p = 8 mhz to 35 mhz, when all units operate in icksel = 0, ta = ?20 c to +75 c (regular specifications), ta = ?40 c to +85 c (wide-range specifications) item min. typ. max. unit resolution 10 10 10 bit conversion time 2.7 ? ? s analog input capacitance ? ? 20 pf excks = 0 ? ? 5 k permissible signal source impedance excks = 1 ? ? 1 k nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 4.0 lsb note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1311 of 1340 rej09b0499-0200 table 29.13 a/d conversion characteristics in system clock mode (icksel = 1) conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, vref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, i = 50 mhz, p = 25 mhz, when all units operate in icksel = 1, ta = ?20 c to +75 c (regular specifications), ta = ?40 c to +85 c (wide-range specifications) item min. typ. max. unit resolution 10 10 10 bit conversion time 1.0 ? ? s analog input capacitance ? ? 20 pf permissible signal source impedance ? ? 1 k nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 8.0 lsb note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1312 of 1340 rej09b0499-0200 29.7 d/a conversion characteristics table 29.14 8-bit d/a conversion characteristics conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, p = 8 mhz to 35 mhz, dadt[1:0] = b'00 (used as 8-bit d/a converter), t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item min. typ. max. unit test conditions resolution 8 8 8 bit conversion time ? ? 10 s 20-pf capacitive load absolute accuracy ? 2.0 3.0 lsb 2-m resistive load ? ? 2.0 lsb 4-m resistive load note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. table 29.15 10-bit d/a conversion characteristics conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v*, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, p = 8 mhz to 35 mhz, dadt[1:0] = don't care (used as 10-bit d/a converter), t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time ? ? 10 s 20-pf capacitive load absolute accuracy ? 2.0 3.0 lsb 16-m resistive load note: * v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1313 of 1340 rej09b0499-0200 29.8 flash memory characteristics table 29.16 flash memory characteristics conditions: v cc = pllv cc = drv cc = 3.0 v to 3.6 v* 5 , av cc = 3.0 v to 3.6 v, ref = 3.0 v to av cc , v ss = pllv ss = drv ss = av ss = 0 v, operating temperature range during programming/erasing: operating temperature range : t a = 0 c to +75 c (regular specifications), operating temperature range : t a = 0 c to +85 c (wide-range specifications) operating voltage range: v cc = pllv cc = 3.0 v to 3.6 v, avcc = 3.0 v to 3.6 v, vref = 3.0 v to av cc , v ss = pllv ss = drvss=avss = 0 v item symbol min. typ. max. unit test conditions programming time * 1, * 2, * 4 t p ? 1 10 ms/128 bytes erasure time * 1, * 2, * 4 t e ? 40 130 ms/4-kbyte block ? 300 800 ms/32-kbyte block ? 600 1500 ms/64-kbyte block tp ? 3.4 9 h8sx/1652, h8sx/1652m s/384 kbytes programming time (total) * 1, * 2, * 4 ? 4.5 12 h8sx/1655, h8sx/1655m s/512 kbytes t a = 25 c, for all 0s te ? 3.4 9 h8sx/1652, h8sx/1652m s/384 kbytes erasure time (total) * 1, * 2, * 4 ? 4.5 12 h8sx/1655, h8sx/1655m s/512 kbytes t a = 25 c tpe ? 6.8 18 h8sx/1652, h8sx/1652m s/384 kbytes programming and erasure time (total) * 1, * 2, * 4 ? 9.0 24 h8sx/1655, h8sx/1655m s/512 kbytes t a = 25 c reprogramming count n wec 100 * 3 ? ? times data retention time * 4 t drp 10 ? ? years notes: 1. programming time and erasure time depend on data in the flash memory. 2. programming time and erasure time do not include time for data transfer. 3. all the characteristics after programming are guaranteed within this value (guaranteed value is from 1 to min. value). 4. characteristics when programming is performed within the min. value. 5. v cc = pllv cc = drv cc = 2.95v to 3.60v in the h8sx/1655m group. section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1314 of 1340 rej09b0499-0200 29.9 power-on reset circuit and voltage-detection circuit characteristics (h8sx/1655m group) table 29.17 power-on reset circuit and vo ltage-detection circuit characteristics conditions: v cc = pllv cc , avcc = 3.0v to avcc, v ss = pllv ss = av ss = 0 v, t a = ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit test conditions voltage detection circuit (lvd) v det 3.00 3.10 3.20 figure 29.44 voltage detection level power-on reset (por) v por 2.48 2.58 2.68 v figure 29.43 internal reset time t por 20 35 50 ms power-off time * t voff 200 ? ? s figure 29.43 figure 29.44 note: * power-off time (t voff ) is the time over which v cc is lower than minimum value of the voltage-detection level of the por and lvd. t voff t por v por t por v cc internal reset signal ("l" is enabled) figure 29.43 power-on reset timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1315 of 1340 rej09b0499-0200 t voff t por v det v cc internal reset signal ("l" is enabled) figure 29.44 voltage de tection circuit timing section 29 electric al characteristics rev. 2.00 oct. 20, 2009 page 1316 of 1340 rej09b0499-0200 appendix rev. 2.00 oct. 20, 2009 page 1317 of 1340 rej09b0499-0200 appendix a. port states in each pin state table a.1 port states in each pin state deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state port 1 all hi-z hi-z keep keep keep keep keep port 2 all hi-z hi-z keep keep keep keep keep p55 to p50 all hi-z hi-z hi-z hi-z hi-z hi-z keep p56/ an6/ da0/ irq6 -b all hi-z hi-z hi-z hi-z [daoe0 = 1] keep [daoe0 = 0] hi-z [daoe0 = 1] keep [daoe0 = 0] hi-z keep p57/ an7/ da1/ irq7 -b all hi-z hi-z hi-z hi-z [daoe1 = 1] keep [daoe1 = 0] hi-z [daoe1 = 1] keep [daoe1 = 0] hi-z keep p65 to p60 all hi-z hi-z keep keep keep keep keep [breqo output] hi-z [breqo output] hi-z [ breqo output] hi-z [ breqo output] hi-z [ bs output] keep [ bs output] hi-z [ bs output] keep [ bs output] hi-z pa0/ breqo / bs -a all hi-z hi-z [other than above] keep [other than above] keep [other than above] keep [other than above] keep [ breqo output] breqo [ bs output] hi-z [other than above] keep [ back output] hi-z [ back output] hi-z [ back output] hi-z [ back output] hi-z [rd/ wr output] keep [rd/ wr output] hi-z [rd/ wr output] keep [rd/ wr output] hi-z pa1/ back / (rd/ wr ) all hi-z hi-z [other than above] keep [other than above] keep [other than above] keep [other than above] keep [ back output] back [rd/ wr output] hi-z [other than above] keep appendix rev. 2.00 oct. 20, 2009 page 1318 of 1340 rej09b0499-0200 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state pa2/ breq / wait all hi-z hi-z [ breq input] hi-z [ wait input] hi-z [other than above] keep [ breq input] hi-z [ wait input] hi-z [other than above] keep [ breq input] hi-z [ wait input] hi-z [other than above] keep [ breq input] hi-z [ wait input] hi-z [other than above] keep [ breq input] hi-z ( breq ) [ wait input] hi-z ( wait ) single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep pa3/ llwr / llb external extended mode (expe = 1) h hi-z h hi-z h hi-z hi-z single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep pa4/ lhwr / lub external extended mode (expe = 1) h hi-z [ lhwr , lub output] h [other than above] keep [ lhwr , lub output] hi-z [other than above] keep [ lhwr , lub output] h [other than above] keep [ lhwr , lub output] hi-z [other than above] keep [ lhwr , lub output] hi-z [other than above] keep single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep pa5/ rd external extended mode (expe = 1) h hi-z h hi-z h hi-z hi-z single-chip mode (expe = 0) hi-z hi-z pa6/ as / ah / bs -b external extended mode (expe = 1) h hi-z [ as , bs output] h [ ah output] l [other than above] keep [ as , ah , bs output] hi-z [other than above] keep [ as , bs output] h [ ah output] l [other than above] keep [ as , ah , bs output] hi-z [other than above] keep [ as , ah , bs output] hi-z [other than above] keep appendix rev. 2.00 oct. 20, 2009 page 1319 of 1340 rej09b0499-0200 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state single-chip mode (expe = 0) hi-z hi-z pa7/b external extended mode (expe = 1) clock output hi-z [clock output] h [other than above] keep [clock output] h [other than above] keep [clock output] h [other than above] keep [clock output] h [other than above] keep [clock output] clock output [other than above] keep single-chip mode (expe = 0) hi-z hi-z pb0/ cs0 / cs4 / cs5 -b external extended mode (expe = 1) h hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb2/ cs2 -a/ cs6 -a all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb3/ cs3 / cs7 -a all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep external extended mode (expe = 1) l hi-z keep hi-z keep hi-z hi-z rom enabled extended mode hi-z hi-z keep [address output] hi-z [other than above] keep keep [address output] hi-z [other than above] keep [address output] hi-z [other than above] keep port d single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep appendix rev. 2.00 oct. 20, 2009 page 1320 of 1340 rej09b0499-0200 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state external extended mode (expe = 1) l hi-z keep hi-z keep hi-z hi-z rom enabled extended mode hi-z hi-z keep [address output] hi-z [other than above] keep keep [address output] hi-z [other than above] keep [address output] hi-z [other than above] keep port e single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep external extended mode (expe = 1) l hi-z keep hi-z keep hi-z hi-z rom enabled extended mode hi-z hi-z keep [address output] hi-z [other than above] keep keep [address output] hi-z [other than above] keep [address output] hi-z [other than above] keep pf3 to pf0 single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep external extended mode (expe = 1) hi-z hi-z keep [address output] hi-z [other than above] keep keep [address output] hi-z [other than above] keep [address output] hi-z [other than above] keep pf4 single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep appendix rev. 2.00 oct. 20, 2009 page 1321 of 1340 rej09b0499-0200 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep port h external extended mode (expe = 1) hi-z hi-z hi-z hi-z hi-z hi-z hi-z single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep 8-bit bus mode hi-z hi-z keep keep keep keep keep port i external extended mode (expe = 1) 16-bit bus mode hi-z hi-z hi-z hi-z hi-z hi-z hi-z port j hi-z hi-z hi-z keep keep keep keep keep port k hi-z hi-z hi-z keep keep keep keep keep port m hi-z hi-z hi-z keep keep keep keep keep [legend] h: high-level output l: low-level output keep: input pins become high-impedanc e, output pins retain their state. hi-z: high impedance appendix rev. 2.00 oct. 20, 2009 page 1322 of 1340 rej09b0499-0200 b. product lineup product classification part no. marking package (package code) r5f61652fpv plqp0120la-a (fp-120bv) * h8sx/1652 r5f61652 r5f61652lgv ptlg0145jb-a (tlp-145v) * r5f61655fpv plqp0120la-a (fp-120bv )* h8sx/1655 r5f61655 r5f61655lgv ptlg0145jb-a (tlp-145v) * r5f61652mfpv plqp0120la-a (fp-120bv) * h8sx/1652m r5f61652m r5f61652mlgv ptlg0145jb-a (tlp-145v) * r5f61655mfpv plqp0120la-a (fp-120bv) * h8sx/1655m r5f61655m r5f61655mlgv ptlg0145jb-a (tlp-145v) * note: * pb-free version appendix rev. 2.00 oct. 20, 2009 page 1323 of 1340 rej09b0499-0200 c. package dimensions for the package dimensions, data in the renesas ic package general catalog has priority. terminal cross section b 1 c 1 b p c include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. detail f c a a 2 a 1 l l 1 * 2 * 3 * 1 f 120 91 90 61 60 31 30 1 x index mark y d h d b p e h e z d z e 1.0 0.125 0.16 1.2 1.2 0.07 0.20 0.145 0.09 0.23 0.18 0.13 max nom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.4 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp120-14x14-0.40 0.7g mass[typ.] 120p6r-a / fp-120b / fp-120bv plqp0120la-a renesas code jeita package code previous code e figure c.1 package dimensions (fp-120bv) appendix rev. 2.00 oct. 20, 2009 page 1324 of 1340 rej09b0499-0200 b a s x n b a b ws a ws s ys 1 y s v x4 k j h g f e d c b a 10 9 8 7 6 5 4 3 2 1 d e l 11 12 13 m n z e z e b a e d ptlg0145jb-a p-tflga145-9x9-0.65 0.15g mass[typ.] previous code jeita package code renesas code - e a 1 max nom min dimension in millimeters symbol reference a b x y 9.0 0.1 0.65 0.30 0.35 0.40 1.2 9.0 0.08 v w 0.6 0.6 y 1 0.20 0.20 0.15 z e z d s e s d e d figure c.2 package dimensions (tlp-145v) appendix rev. 2.00 oct. 20, 2009 page 1325 of 1340 rej09b0499-0200 d. treatment of unused pins the treatments of unused pins are listed in table d.1 table d.1 treatment of unused pins pin name mode 4 mode 5 mode 6 modes 3, 7 res (always used as a reset pin) stby ? connect this pin to v cc via a pull-up resistor emle ? connect this pin to vss via a pull-down resistor md_clk (always used as mode pins) md2 to md0 (always used as mode pins) nmi ? connect this pin to vcc via a pull-up resistor extal (always used as a clock pin) xtal ? leave this pin open wdtovf ? leave this pin open usd + ? leave this pin open usd ? ? leave this pin open vbus ? leave this pin open port 1 port 2 port 6 pa2 to pa0 pb3 to pb1 port j port k port m ? connect these pins to v cc via a pull-up resistor or to vss via a pull-down resistor, respectively port 5 ? connect these pins to avcc via a pull-up resistor or to avss via a pull-down resistor, respectively appendix rev. 2.00 oct. 20, 2009 page 1326 of 1340 rej09b0499-0200 pin name mode 4 mode 5 mode 6 modes 3,7 pa7 ? this pin is left open in the initial state for the b output. pa6 ? this pin is left open in the initial state for the as output. pa5 ? this pin is left open in the initial state for the rd output. pa4 ? this pin is left open in the initial state for the lhwr output. pa3 ? this pin is left open in the initial state for the llwr output. pb0 ? this pin is left open in the initial state for the cs0 output. port d port e pf4 to pf0 ? these pins are left open in the initial state for the address output. port h (used as a data bus) port i (used as a data bus) ? connect these pins to vcc via a pull-up resistor or to vss via a pull- down resistor, respectively, in the initial state for the general input. ? connect these pins to vcc via a pull-up resistor or to vss via a pull- down resistor, respectively vref ? connect this pin to avcc notes: 1. do not change the initial value (input-b uffer disabled) of pnicr, where n corresponds to an unused pin. 2. when the pin function is changed from its initial state, use a pull-up or pull-down resistor as needed. rev. 2.00 oct. 20, 2009 page 1327 of 1340 rej09b0499-0200 main revisions and add itions in this edition common revised items due to the version upgrade from rev.1.00 to rev.2.00. item page revision (s ee manual for details) all ? group name added: h8sx/1655m group accordingly, descriptions related to the h8sx/1655m group also added. all ? descriptions related to power-on reset (por) and voltage detection circuit (lvd) added rev. 2.00 oct. 20, 2009 page 1328 of 1340 rej09b0499-0200 item page revision (s ee manual for details) all ? amended section, table, and figure numbers were amended due to the addition of the section 5. structure of the rev. 2.00 1. overview 2. cpu 3. mcu operating modes 4. reset 5. voltage detection circuit (lvd) 6. exception handling 7. interrupt controller 8. user break controller (ubc) 9. bus controller (bsc) 10. dma controller (dmac) 11. exdma controller (exdmac) 12. data transfer controller (dtc) 13. i/o ports 14. 16-bit timer pulse unit (tpu) 15. programmable pulse generator (ppg) 16. 8-bit timers (tmr) 17. watchdog timer (wdt) 18. serial communication interface (sci, irda, crc) 19. usb function module (usb) 20. i 2 c bus interface 2 (iic2) 21. a/d converter 22. d/a converter 23. ram 24. flash memory 25. boundary scan 26. clock pulse generator 27. power-down modes 28. list of registers 29. electrical characteristics appendix rev. 2.00 oct. 20, 2009 page 1329 of 1340 rej09b0499-0200 item page revision (s ee manual for details) section 13 i/o ports 13.1 register descriptions table 13.2 register configuration in each port 512 notes added notes: 1. do not access port d or e registers when pcjke = 1. 2. do not access port j or k registers when pcjke = 0. 3. the lower six bits are valid and the upper two bits are reserved for port 6 registers. the write value should be the same as the initial value. 4. the lower four bits are valid and the upper four bits are reserved for port b registers. the write value should be the same as the initial value. 5. the lower five bits are valid and the upper three bits are reserved for port f registers. the write value should be the same as the initial value. 6. the lower five bits are valid and the upper three bits are reserved for port m registers. the write value should be the same as the initial value. section 21 a/d converter 21.4 operation input sampling and 21.4.3 a/d conversion time 997 to 999 the following tables replaced table 21.3 characteristics of a/d conversion (unit 0: when excks * = 0, icksel = 0, and adsstr * = h'0f) (1) table 21.3 characteristics of a/d conversion (unit 0: when excks * = 1, icksel = 0, and adsstr * = h'0f) (2) table 21.4 characteristics of a/d conversion (unit 1: when excks = 0, icksel = 0, and adsstr * = h'0f) (1) table 21.4 characteristics of a/d conversion (unit 1: when excks = 1, icksel = 0, and adsstr * = h'0f) (2) table 21.5 characteristics of a/d conversion (when excks * 1 = 1, icksel * 1 = 0, and adsstr * 2 = h'19) table 21.6 period of a/d conversion (scan mode) (units 0 and 1) 1000 notes added notes: 1. make the sampling setting15 (adssrt = d'15). 2. when p = i /2, make the sampling setting 25 (adssrt = d'25). 3. unit 0: the full-spec emulator (e6000h) should not be used, but the on-chip emulator (e10a-usb) is usable. 4. unit 1: access to the full-spec emulator (e6000h) is prohibited but the on-chip emulator (e10a-usb) is usable. rev. 2.00 oct. 20, 2009 page 1330 of 1340 rej09b0499-0200 item page revision (s ee manual for details) 21.7 usage notes 21.7.5 permissible signal source impedance 1009 note amended notes: 1. unit 0: the full-spec emulator (e6000h) should not be used, but the on-chip emulat or (e10a-usb) is usable. 2. unit 1: access to the full-spec emulator (e6000h) is prohibited, but the on-chip emulator (e10a-usb) is usable. 21.7.8 notes on board design 1011 amended in board design, follow the notes below. 1. ? moreover, digital circuitry must be isolated from the analog reference power supply pin (v ref ), analog power supply pin (av cc ), and analog ground pin (av ss ) by shielding the analog input pins (an0 to an7) with the analog ground pin (av ss ). 21.7.9 notes on noise countermeasures 1011 amended a protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an7) should be connected to av cc and av ss as shown in figure 21.14. also, the bypass capacitors connected to av cc and v ref and the filter capacitor connected to the an0 to an7 pins must be connected to av ss . ? if a filter capacitor is connected, the input currents at the an0 to an7 pins are averaged, and so an error may arise. ? figure 21.14 example of analog input protection circuit 1012 amended av cc vref av ss an0 to an7 rev. 2.00 oct. 20, 2009 page 1331 of 1340 rej09b0499-0200 item page revision (s ee manual for details) section 29 electrical characteristics 29.2 dc characteristics (h8sx/1655 group) table 29.2 dc characteristics 1273 amended item symbol three-state leakage current (off state) ports 1, 2, 6, a, b, d to f, h to k, m | i tsi | input pull-up mos current ports d to f, h, i ?i p rev. 2.00 oct. 20, 2009 page 1332 of 1340 rej09b0499-0200 rev. 2.00 oct. 20, 2009 page 1333 of 1340 rej09b0499-0200 index numerics 0 output/1 output..................................... 643 0-output/1-output .................................... 643 16-bit access space.................................. 222 16-bit counter mode................................ 748 16-bit timer pulse unit (tpu) ................. 577 8-bit access space.................................... 221 8-bit timers (tmr) ................................. 721 a a/d conversion accuracy...................... 1004 absolute accu racy................................. 1004 acknowledge .......................................... 952 address error .......................................... 112 address map ............................................. 81 address mode ......................................... 440 address modes................................ 310, 390 address/data multiplexed i/o interface .......................................... 215, 250 all-module-clock-stop mode ...... 1150, 1174 area 0 ..................................................... 216 area 1 ..................................................... 217 area 2 ..................................................... 217 area 3 ..................................................... 218 area 4 ..................................................... 218 area 5 ..................................................... 219 area 6 ..................................................... 220 area 7 ..................................................... 220 area division........................................... 210 asynchronous mode ............................... 814 at-cut parallel-resonance type............. 1142 available output signal and settings in each port ................................................. 552 average transfer rate generator............... 770 b b clock output control......................... 1196 basic bus interf ace .......................... 214, 224 big endian ............................................... 213 bit rate ..................................................... 797 bit synchronous circuit ........................... 967 block structure ...................................... 1031 block transfer mode ................ 316, 396, 491 boot mode................................... 1028, 1057 boundary scan commands .................... 1127 buffer operation ...................................... 648 bulk-in transfer ....................................... 921 bulk-out transfer ..................................... 920 burst access mode................................... 322 burst mode.............................................. 401 burst rom interface....................... 214, 245 bus access modes.................................... 321 bus arbitration......................................... 276 bus configuration.................................... 202 bus controller (bsc)............................... 177 bus cycle division ................................... 485 bus mode ................................................ 400 bus width ................................................ 213 bus-released state...................................... 71 byte control sram interface ......... 214, 237 c cascaded conn ection............................... 748 cascaded operation ................................. 652 chain transfer.......................................... 492 chip select signals................................... 211 clock pulse generator ........................... 1137 clock synchronizati on cycle (tsy).......... 204 clocked synchronous mode .................... 831 rev. 2.00 oct. 20, 2009 page 1334 of 1340 rej09b0499-0200 cluster transfer dual address mode......... 440 cluster transfer modes ............................ 389 cluster transfer read address mode......... 442 cluster transfer write address mode ....... 444 communications protocol..................... 1094 compare match a................................... 745 compare match b ................................... 746 compare match count mode ................... 748 compare match signal ............................ 745 control transfer....................................... 914 counter operation ................................... 640 cpu priority control function over dtc and dmac ............................................. 158 crc operation circuit ........................... 860 crystal resona tor................................... 1142 cycle steal mode..................................... 400 cycle steali ng mode................................ 321 d d/a converter ....................................... 1013 data direction register ............................ 513 data register............................................ 514 data stage ............................................... 916 data transfer controller (dtc) ............... 467 direct convention ................................... 839 dma controller (dmac)....................... 283 double-buffered structure....................... 814 download pass/fail result parameter..... 1046 dtc vector address ................................ 480 dtc vector address offset ...... 480, 481, 482 dual address mode.......................... 310, 390 e endian and data alignment ..................... 221 endian format ......................................... 213 error protec tion .................................... 1086 error signal ............................................. 839 exception handling ................................. 105 exception-handling state........................... 71 exdma controller (exdmac) ............ 361 extended repeat area ............................... 307 extended repeat area function......... 323, 401 extension of chip select ( cs ) assertion period ...................................................... 234 external access bus ................................. 202 external bus ............................................ 207 external bus clock (b ) ................ 203, 1137 external bus interface ............................. 212 external clock ....................................... 1143 external interrupts................................... 141 f flash erase block select parameter........ 1055 flash memory ....................................... 1025 flash multipurpose address area parameter .............................................. 1053 flash multipurpose data destination parameter .............................................. 1054 flash pass and fail parameter ................ 1047 flash program/erase frequency parameter .................................... 1051, 1069 free-running count operation.................. 641 frequency divider ....................... 1137, 1144 full address mode ................................... 478 full-scale error...................................... 1004 g general illegal in structions ..................... 120 h hardware protection ............................. 1085 hardware standby mode ............. 1150, 1191 rev. 2.00 oct. 20, 2009 page 1335 of 1340 rej09b0499-0200 i i/o ports.................................................. 505 i 2 c bus format......................................... 952 i 2 c bus interface2 (iic2) ........................ 935 id code ................................................... 825 idle cycle ................................................ 260 illegal instru ction.................................... 120 input buffer control register.................... 515 input capture function............................. 644 internal interrupts ................................... 142 internal peripheral bus ............................ 202 internal system bus ................................. 202 interrupt .................................................. 116 interrupt control mode 0 ......................... 149 interrupt control mode 2 ......................... 151 interrupt controller.................................. 123 interrupt exception handling sequence ... 153 interrupt exception handling vector table ........................................................ 143 interrupt response times.......................... 154 interrupt sources ..................................... 141 interrupt sources and vector address offsets ..................................................... 143 interrupt-in transfer................................. 923 interval timer .......................................... 764 interval timer mode................................. 764 inverse convention.................................. 840 irqn interrupts ....................................... 141 j jtag interface ....................................... 971 l little endian............................................ 213 m mark state ....................................... 814, 855 master receive mode ............................... 955 master transmit mode ............................. 953 mcu operating modes .............................. 73 memory mat configuration ................ 1030 mode 2 ...................................................... 79 mode 4 ...................................................... 79 mode 5 ...................................................... 80 mode 6 ...................................................... 80 mode 7 ...................................................... 80 mode pin ................................................... 73 multi-clock mode.................................. 1172 multiprocessor bit ................................... 825 multiprocessor communication function ................................................... 825 n nmi interrupt.......................................... 141 noise canceler......................................... 961 nonlinearity error.................................. 1004 non-overlapping pulse output................. 711 normal transfer mode ............................. 488 normal transfer mode ..................... 314, 394 number of access cycles ....................... 214 o offset addition ........................................ 326 offset addition method ........................... 404 offset error............................................ 1004 on-board programming ........................ 1057 on-board programming mode..... 1025, 1057 on-chip baud rate generator.................... 817 on-chip rom disabled extended mode .... 73 on-chip rom enabled extended mode..... 73 open-drain control register ..................... 517 oscillator............................................... 1142 output buffer control .............................. 518 output trigger.......................................... 710 overflow ......................................... 747, 762 rev. 2.00 oct. 20, 2009 page 1336 of 1340 rej09b0499-0200 p package dimensions.................... 1323, 1325 parity bit ................................................. 814 periodic count operation......................... 641 peripheral module clock (p ) ....... 203, 1137 phase counting mode .............................. 660 pin assignments ........................................ 13 pin functions............................................. 21 pll circuit.................................. 1137, 1144 port function controller........................... 559 port register ............................................ 514 power-down modes .............................. 1149 procedure program ............................... 1079 processing states ....................................... 71 product lineup....................................... 1322 program execution state............................ 71 program stop state .................................... 71 programmable pulse generator (ppg) .... 687 programmer mode ...................... 1028, 1092 programming/erasing interface............. 1033 programming/erasing interface parameters............................................. 1044 programming/erasing interface register .................................................. 1037 protection.............................................. 1085 pull-up mos control register.................. 516 pwm modes ........................................... 654 q quantization error................................. 1004 r ram..................................................... 1023 read strobe ( rd ) timing......................... 233 register addresses ................................... 1200 register bits ........................................... 1219 register configuration in each port......... 512 registers abwcr.............................................. 181 adcsr ............................................... 977 astcr ............................................... 182 bcr1 .................................................. 194 bcr2 .................................................. 196 bromcr ........................................... 199 brr .................................................... 797 ccr ...................................................... 39 clsbr................................................ 387 cpupcr ............................................. 127 cra .................................................... 473 crb .................................................... 474 crccr ............................................... 861 crcdir ............................................. 862 crcdor............................................ 862 csacr ............................................... 189 ctlr .................................................. 892 cvr .................................................... 892 dacr ................................................. 302 dacr01 ........................................... 1017 dadr01t......................................... 1016 dadr0h .......................................... 1015 dadr0l........................................... 1016 dadr1h .......................................... 1015 dadr1l........................................... 1016 dar.................................................... 473 dasts................................................ 886 dbsr.................................................. 292 ddar ................................................. 289 ddr.................................................... 513 dma ................................................... 888 dmdr ................................................ 293 dmrsr .............................................. 308 dofr.................................................. 290 dpfr ................................................ 1046 dr....................................................... 514 dsar.................................................. 288 dtccr ............................................... 475 dtcer ............................................... 474 rev. 2.00 oct. 20, 2009 page 1337 of 1340 rej09b0499-0200 dtcr ................................................. 291 dtcvbr............................................ 477 edacr............................................... 381 edbsr ............................................... 371 eddar .............................................. 368 edmdr.............................................. 372 edofr ............................................... 369 edsar ............................................... 367 edtcr ............................................... 370 endiancr........................................ 197 epdr.................................................. 882 epdr0i............................................... 880 epdr0o.............................................. 881 epdr0s .............................................. 881 epir ................................................... 894 epstl ................................................ 891 epsz0o............................................... 883 epsz1................................................. 884 exr ...................................................... 40 fccs ................................................ 1037 fclr .................................................. 887 febs................................................. 1055 fecs................................................. 1040 fkey................................................ 1041 fmats............................................. 1042 fmpar............................................. 1053 fmpdr............................................. 1054 fpcs................................................. 1040 fpefeq.................................. 1051, 1069 fpfr................................................. 1047 ftdar ............................................. 1043 general registers ................................... 37 iccra................................................ 939 iccrb ................................................ 941 icdrr................................................ 951 icdrs ................................................ 951 icdrt ................................................ 951 icier.................................................. 944 icmr.................................................. 943 icr ..................................................... 515 icsr.................................................... 947 idlcr ................................................ 192 ier...................................................... 131 ier (usb)........................................... 878 ifr (usb)........................................... 870 intcr ................................................ 126 ipr ...................................................... 129 ircr .................................................... 813 iscrh................................................. 133 iscrl ................................................. 133 isr ...................................................... 138 isr (usb)........................................... 875 lvdcr................................................. 98 mac ..................................................... 41 mdcr................................................... 75 mpxcr .............................................. 201 mra ................................................... 470 mrb.................................................... 471 mstpcra........................................ 1156 mstpcrb ........................................ 1156 mstpcrc ........................................ 1159 nderh............................................... 692 nderl ............................................... 692 ndrh ................................................. 697 ndrl.................................................. 697 odr.................................................... 517 pc ......................................................... 38 pcr..................................................... 701 pcr (i/o port)..................................... 516 pfcr0................................................. 560 pfcr1................................................. 561 pfcr2................................................. 562 pfcr4................................................. 564 pfcr6................................................. 565 pfcr7................................................. 566 pfcr9................................................. 568 pfcrb ................................................ 571 pfcrc ................................................ 573 pmr .................................................... 703 podrh............................................... 694 rev. 2.00 oct. 20, 2009 page 1338 of 1340 rej09b0499-0200 podrl ............................................... 694 port.................................................. 514 ramer............................................ 1056 rdncr .............................................. 188 rdr.................................................... 777 rsr .................................................... 777 rstcsr ............................................. 761 rstsr.................................................. 99 sar ............................................ 472, 950 sbr ...................................................... 41 sbycr............................................. 1153 sckcr............................................. 1139 scmr................................................. 796 scr .................................................... 782 sdbpr ............................................. 1127 sdbsr ............................................. 1127 sdid................................................. 1132 semr ................................................. 804 smr.................................................... 778 sramcr ........................................... 198 ssier ................................................. 140 ssr..................................................... 787 syscr ................................................. 77 tccr.................................................. 732 tcnt.................................................. 637 tcnt (tmr) ..................................... 729 tcnt (wdt)..................................... 759 tcora .............................................. 729 tcorb............................................... 730 tcr .................................................... 591 tcr (tmr) ........................................ 730 tcsr (tmr)...................................... 737 tcsr (wdt) ..................................... 759 tdr .................................................... 778 tgr .................................................... 637 tier ................................................... 632 tior................................................... 598 tmdr ................................................ 596 trg .................................................... 884 trntreg.......................................... 898 tsr ............................................. 633, 778 tstr................................................... 638 tsyr .................................................. 639 vbr ...................................................... 41 wtcra.............................................. 183 wtcrb .............................................. 183 repeat transfer mode .............. 315, 395, 489 reset ....................................................... 108 reset state ................................................. 71 resolution ............................................. 1004 s sample-and-hold circuit.......................... 996 scan mode............................................... 991 serial communication interface (sci)..... 769 setup stage .............................................. 915 short address mode ................................. 478 single address mode ....................... 311, 391 single mode ............................................ 990 slave receive mode ................................. 960 slave transmit mode................................ 957 sleep mode.................................. 1150, 1173 slot illegal inst ructions ........................... 120 smart card interface ................................ 838 software prot ection............................... 1086 software standby mode............... 1150, 1175 space state .............................................. 814 stack status after ex ception handling...... 121 stall operations ....................................... 925 standard serial communication interface specifications for boot mode................. 1092 start bit.................................................... 814 state transition of tap controller ......... 1133 state tran sitions......................................... 72 status stage ............................................. 918 stop bit.................................................... 814 strobe assert/neg ate timing ..................... 216 synchronous clearing.............................. 646 synchronous op eration............................ 646 rev. 2.00 oct. 20, 2009 page 1339 of 1340 rej09b0499-0200 synchronous pr esetting........................... 646 system clock (i ).......................... 203, 1137 t tap controller ...................................... 1133 toggle output.......................................... 643 trace exception handling........................ 111 transfer information............................... 478 transfer information read skip function................................................... 487 transfer information writeback skip function................................................... 488 transfer modes ............................... 314, 394 transmit/receive data.............................. 814 trap instruction ex ception handling ....... 118 u usb function module ............................. 867 usb standard commands........................ 924 user boot ma t..................................... 1030 user boot mode ........................... 1028, 1075 user break controller (ubc)................... 165 user mat ............................................. 1030 user program mode..................... 1028, 1065 v vector table address................................ 106 vector table address offset...................... 106 voltage detection circuit (lvd).............. 97 w wait control ............................................ 231 watchdog timer (wdt) .......................... 757 watchdog timer mode............................. 762 waveform output by compare match...... 642 write data buffer function....................... 274 write data buffer function for external data bus ................................................... 274 write data buffer function for peripheral modules................................................... 275 rev. 2.00 oct. 20, 2009 page 1340 of 1340 rej09b0499-0200 renesas 32-bit cisc microcomputer hardware manual h8sx/1655 group, h8sx/1655m group publication date: rev.1.00, mar. 25, 2009 rev.2.00, oct. 20, 2009 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2009. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.2 h8sx/1655 group, h8sx/1655m group rej09b0499-0200 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan |
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